From f43ea71e9542c1fba1d2873ed523aa0444d9be86 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 16 Jul 2019 15:52:02 +0200 Subject: [PATCH] Minor changes in new timing checker. --- .../memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml | 55 +++++++++++++++++++ DRAMSys/library/src/controller/Controller.cpp | 1 - .../scheduling/checker/CheckerDDR3New.cpp | 12 +--- .../core/scheduling/checker/CheckerDDR3New.h | 1 - 4 files changed, 58 insertions(+), 11 deletions(-) create mode 100644 DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml new file mode 100644 index 00000000..262feb17 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index e9db7911..adc1b75a 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -305,7 +305,6 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload, else if (phase == END_RESP) { // Bandwidth IDLE - // TODO: getTotalNumberOfPayloadsInSystem() == 1 && !idleState ?? if (getTotalNumberOfPayloadsInSystem() == 1) startBandwidthIdleCollector(); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 34ea33fa..451158cf 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -55,7 +55,9 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); - delayToSatisfyACTtoACTsameBank(command); + lastCommand = state.getLastCommand(Command::ACT, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRC); while (!(state.bus.isFree(command.getStart()) && satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command))) command.delayStart(memSpec->clk); @@ -373,14 +375,6 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const /* * ActivateChecker */ - -void CheckerDDR3New::delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const -{ - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); - if (lastActivateOnBank.isValidCommand()) - command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); -} - bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const { for (auto act : state.lastActivates) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index ad202aca..6daff0dc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -24,7 +24,6 @@ private: MemSpecDDR3 *memSpec; //Activate - void delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const; bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const; bool satisfiesNActivateWindow(ScheduledCommand &command) const;