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Moved bandwidth calculation from Dram to Controller.

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This commit is contained in:
Lukas Steiner
2019-06-16 21:12:33 +02:00
parent b96121b4f8
commit bf1a9dc47d
4 changed files with 51 additions and 76 deletions
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49
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -39,6 +39,53 @@
#include "Controller.h"
#include <iostream>
Controller::~Controller()
{
// Bandwidth:
sc_time activeTime = numberOfTransactionsServed
* Configuration::getInstance().memSpec.BurstLength
/ Configuration::getInstance().memSpec.DataRate
* Configuration::getInstance().memSpec.clk;
sc_time idleTime = getIdleTime();
sc_time endTime = getEndTime();
sc_time startTime = getStartTime();
double bandwidth = (activeTime / (endTime - startTime) * 100);
double bandwidth_IDLE = ((activeTime) / (endTime - startTime - idleTime) * 100);
double maxBandwidth = (
// clk in Mhz e.g. 800 [MHz]:
(1000000 / Configuration::getInstance().memSpec.clk.to_double())
// DataRate e.g. 2
* Configuration::getInstance().memSpec.DataRate
// BusWidth e.g. 8 or 64
* Configuration::getInstance().memSpec.bitWidth
// Number of devices on a DIMM e.g. 8
* Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
cout << name() << string(" Total Time: ")
<< (endTime - startTime).to_string()
<< endl;
cout << name() << string(" AVG BW: ")
<< std::fixed << std::setprecision(2)
<< ((bandwidth / 100)*maxBandwidth)
<< " Gibit/s (" << bandwidth << " %)"
<< endl;
cout << name() << string(" AVG BW/IDLE: ")
<< std::fixed << std::setprecision(2)
<< ((bandwidth_IDLE / 100)*maxBandwidth)
<< " Gibit/s (" << (bandwidth_IDLE) << " %)"
<< endl;
cout << name() << string(" MAX BW: ")
<< std::fixed << std::setprecision(2)
<< maxBandwidth << " Gibit/s"
<< endl;
delete controllerCore;
delete scheduler;
}
void Controller::buildScheduler()
{
string selectedScheduler = Configuration::getInstance().Scheduler;
@@ -470,6 +517,8 @@ void Controller::sendToDram(tlm_generic_payload &payload,
{
tlm_phase TPhase = phase;
sc_time TDelay = delay;
if (phase == BEGIN_WR || phase == BEGIN_RD || phase == BEGIN_WRA || phase == BEGIN_RDA)
numberOfTransactionsServed++;
iSocket->nb_transport_fw(payload, TPhase, TDelay);
}

7
DRAMSys/library/src/controller/Controller.h
View File

@@ -94,11 +94,7 @@ public:
tSocket.register_transport_dbg(this, &Controller::transport_dbg);
}
virtual ~Controller()
{
delete controllerCore;
delete scheduler;
}
virtual ~Controller();
void terminateSimulation();
@@ -172,6 +168,7 @@ protected:
sc_time endTime;
sc_time startTime;
int startTimeSet = false;
unsigned long long int numberOfTransactionsServed = 0;
void startBandwidthIdleCollector();
void endBandwidthIdleCollector();

1
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -260,7 +260,6 @@ void DRAMSys::instantiateModules(const string &traceName,
dram = new RecordableDram(str.c_str(), tlmRecorders[i]);
else
dram = new Dram(str.c_str());
dram->setDramController(controllers[i]);
drams.push_back(dram);
if (Configuration::getInstance().CheckTLM2Protocol) {

70
DRAMSys/library/src/simulation/Dram.h
View File

@@ -74,11 +74,6 @@ struct Dram : sc_module {
bool powerAnalysis = Configuration::getInstance().PowerAnalysis;
libDRAMPower *DRAMPower;
// Bandwidth realted:
unsigned long long int numberOfTransactionsServed;
sc_time firstAccess;
sc_time lastAccess;
// Error Model related:
StorageMode StoreMode = Configuration::getInstance().StoreMode;
std::vector<errorModel *> ememory;
@@ -86,14 +81,11 @@ struct Dram : sc_module {
// Data Storage:
unsigned char *memory;
Controller *dramController;
SC_CTOR(Dram) : tSocket("socket")
{
// Adjust number of bytes per burst dynamically to the selected ecc controller
bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC(
bytesPerBurst);
dramController = NULL;
std::uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes();
if (Configuration::getInstance().UseMalloc) {
@@ -214,11 +206,6 @@ struct Dram : sc_module {
DRAMPower = new libDRAMPower( memSpec, 0 );
}
// Bandwidth Calculation:
numberOfTransactionsServed = 0;
firstAccess = SC_ZERO_TIME;
lastAccess = SC_ZERO_TIME;
// For each bank in a channel a error Model is created:
if (StoreMode == StorageMode::ErrorModel) {
for (unsigned i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks;
@@ -261,47 +248,6 @@ struct Dram : sc_module {
<< string(" mW") << endl;
}
// Bandwidth:
sc_time activeTime = numberOfTransactionsServed
* Configuration::getInstance().memSpec.BurstLength
/ Configuration::getInstance().memSpec.DataRate
* Configuration::getInstance().memSpec.clk;
sc_time idleTime = dramController->getIdleTime();
sc_time endTime = dramController->getEndTime();
sc_time startTime = dramController->getStartTime();
double bandwidth = (activeTime / (endTime - startTime) * 100);
double bandwidth_IDLE = ((activeTime) / (endTime - startTime - idleTime) * 100);
double maxBandwidth = (
// clk in Mhz e.g. 800 [MHz]:
(1000000 / Configuration::getInstance().memSpec.clk.to_double())
// DataRate e.g. 2
* Configuration::getInstance().memSpec.DataRate
// BusWidth e.g. 8 or 64
* Configuration::getInstance().memSpec.bitWidth
// Number of devices on a DIMM e.g. 8
* Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
cout << name() << string(" Total Time: ")
<< (endTime - startTime).to_string()
<< endl;
cout << name() << string(" AVG BW: ")
<< std::fixed << std::setprecision(2)
<< ((bandwidth / 100)*maxBandwidth)
<< " Gibit/s (" << bandwidth << " %)"
<< endl;
cout << name() << string(" AVG BW/IDLE: ")
<< std::fixed << std::setprecision(2)
<< ((bandwidth_IDLE / 100)*maxBandwidth)
<< " Gibit/s (" << (bandwidth_IDLE) << " %)"
<< endl;
cout << name() << string(" MAX BW: ")
<< std::fixed << std::setprecision(2)
<< maxBandwidth << " Gibit/s"
<< endl;
// Clean up:
for (auto e : ememory) {
delete e;
@@ -315,12 +261,6 @@ struct Dram : sc_module {
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay)
{
if (numberOfTransactionsServed == 0) {
firstAccess = sc_time_stamp();
} else {
lastAccess = sc_time_stamp();
}
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
// This is only needed for power simulation:
@@ -376,7 +316,6 @@ struct Dram : sc_module {
if (powerAnalysis == true) {
DRAMPower->doCommand(MemCommand::WR, bank, cycle);
}
numberOfTransactionsServed++;
//save data:
if (StoreMode == StorageMode::NoStorage) {
@@ -393,8 +332,6 @@ struct Dram : sc_module {
#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5)
assert(payload.get_data_length() == bytesPerBurst);
#endif
numberOfTransactionsServed++;
if (powerAnalysis == true) {
DRAMPower->doCommand(MemCommand::RD, bank, cycle);
}
@@ -411,7 +348,6 @@ struct Dram : sc_module {
sendToController(payload, END_RD, delay + getExecutionTime(Command::Read,
payload));
} else if (phase == BEGIN_WRA) {
numberOfTransactionsServed++;
if (powerAnalysis == true) {
DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
}
@@ -428,7 +364,6 @@ struct Dram : sc_module {
sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA,
payload));
} else if (phase == BEGIN_RDA) {
numberOfTransactionsServed++;
if (powerAnalysis == true) {
DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
}
@@ -576,11 +511,6 @@ struct Dram : sc_module {
{
DebugManager::getInstance().printDebugMessage(name(), message);
}
void setDramController(Controller *contr)
{
dramController = contr;
}
};
#endif /* DRAM_H_ */