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Renaming of timings.

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This commit is contained in:
Lukas Steiner (2)
2019-06-28 15:14:47 +02:00
parent 7da2aacfa3
commit a5fb1327a1
13 changed files with 47 additions and 46 deletions
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16
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
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@@ -216,8 +216,8 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
@@ -295,8 +295,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2");
@@ -379,8 +379,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP");
memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XS");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB");
// TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
@@ -459,8 +459,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXPDLL = memSpec->tXP;
memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
memSpec->tXSRDLL = memSpec->tXSR;
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tXSDLL = memSpec->tXS;
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");

17
DRAMSys/library/src/controller/core/configuration/MemSpec.h
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@@ -73,7 +73,6 @@ struct MemSpec
std::string MemoryType = "not defined.";
unsigned int NumberOfBanks;
unsigned int NumberOfBankGroups;
unsigned int NumberOfRanks;
unsigned int BurstLength;
unsigned int nActivate;
@@ -100,9 +99,12 @@ struct MemSpec
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXSR; // min delay to row access command after srefx
sc_time tXS; // min delay to row access command after srefx
unsigned int NumberOfBankGroups;
sc_time tNAW; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else
sc_time tRP; // precharge-time (pre -> act same bank)
sc_time tRFC; //min ref->act delay 1X mode
sc_time tRFC2; //min ref->act delay 2X mode
@@ -114,11 +116,10 @@ struct MemSpec
sc_time tCCD_L;
sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group)
sc_time tRRD_L; //.. (same bank group)
sc_time tNAW; //n activate window
sc_time tWTR_S; //write to read (different bank group)
sc_time tWTR_L; //.. (same bank group)
sc_time tXPDLL; // min delay to row access command after pdnpx pdnax for dll commands
sc_time tXSRDLL; // min delay to row access command after srefx for dll commands
sc_time tXSDLL; // min delay to row access command after srefx for dll commands
// Currents and Voltages:
double iDD0;
@@ -170,7 +171,7 @@ struct MemSpec
struct MemSpecDDR3 : public MemSpec
{
sc_time tCCD;
// sc_time tFAW;
sc_time tFAW;
sc_time tWTR;
// sc_time tREFI;
// sc_time tRFC;
@@ -184,7 +185,7 @@ struct MemSpecDDR4 : public MemSpec
{
// sc_time tCCD_S;
// sc_time tCCD_L;
// sc_time tFAW;
sc_time tFAW;
// sc_time tWTR_S;
// sc_time tWTR_L;
// sc_time tREFI;
@@ -203,7 +204,7 @@ struct MemSpecWideIO : public MemSpec
{
// sc_time tCCD;
// sc_time tWTR;
// sc_time tTAW;
sc_time tTAW;
// sc_time tREFI;
// sc_time tRFC;
// sc_time tRP;
@@ -217,7 +218,7 @@ struct MemSpecLPDDR4 : public MemSpec
// sc_time tCCD;
// sc_time tCCDMW;
// sc_time tESCKE;
// sc_time tFAW;
sc_time tFAW;
// sc_time tWTR;
// sc_time tPPD;
// sc_time tREFIAB;

2
DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp
View File

@@ -73,7 +73,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
|| lcb.getCommand() == Command::PDNAX) {
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP);
} else if (lcb.getCommand() == Command::SREFX) {
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXSR);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS);
} else {
reportFatal("ActB Checker",
"ActB can not follow " + commandToString(lcb.getCommand()));

2
DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -81,7 +81,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
config.memSpec->tXP);
} else if (lastCommandOnBank.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec->tXSR);
config.memSpec->tXS);
} else
reportFatal("Activate Checker",
"Activate can not follow " + commandToString(lastCommandOnBank.getCommand()));

12
DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp
View File

@@ -46,7 +46,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
break;
case Command::SREFX:
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
memSpec->tXSR);
memSpec->tXS);
break;
case Command::AutoRefresh:
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
@@ -208,7 +208,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
break;
case Command::SREFX:
command.establishMinDistanceFromStart(lastCommand.getStart(),
memSpec->tXSR);
memSpec->tXS);
break;
case Command::AutoRefresh:
command.establishMinDistanceFromStart(lastCommand.getStart(),
@@ -264,7 +264,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
break;
case Command::SREFX:
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
memSpec->tXSR);
memSpec->tXS);
break;
default:
reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow "
@@ -326,7 +326,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
break;
case Command::SREFX:
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
memSpec->tXSR);
memSpec->tXS);
break;
default:
reportFatal("Checker DDR3",
@@ -373,7 +373,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const
break;
case Command::SREFX:
command.establishMinDistanceFromStart(lastCommand.getStart(),
memSpec->tXSR);
memSpec->tXS);
break;
default:
reportFatal("Checker DDR3",
@@ -481,7 +481,7 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const
{
ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank());
if (lastSREFX.isValidCommand())
read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSRDLL);
read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL);
}

2
DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp
View File

@@ -64,7 +64,7 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd,
} else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) {
constraint = config.memSpec->tXP;
} else if (lastCmd == Command::SREFX) {
constraint = config.memSpec->tXSR;
constraint = config.memSpec->tXS;
} else if (lastCmd == Command::Precharge || lastCmd == Command::PrechargeAll) {
constraint = config.memSpec->tRP;
} else {

2
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
View File

@@ -86,7 +86,7 @@ const
config.memSpec->tXP);
} else if (lastCommand.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tXSR);
config.memSpec->tXS);
} else
reportFatal("Precharge All Checker",
"Precharge All can not follow " + commandToString(lastCommand.getCommand()));

2
DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp
View File

@@ -112,7 +112,7 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const
read.getBank());
if (lastSREFX.isValidCommand())
read.establishMinDistanceFromStart(lastSREFX.getStart(),
config.memSpec->tXSRDLL);
config.memSpec->tXSDLL);
}
sc_time ReadChecker::readToRead(ScheduledCommand &firstRead,

4
DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp
View File

@@ -64,7 +64,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
config.memSpec->tXP);
} else if (lastCommandOnBank.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec->tXSR);
config.memSpec->tXS);
} else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) {
} else
reportFatal("Refresh Checker",
@@ -96,7 +96,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
config.memSpec->tXP);
} else if (lastCommand.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tXSR);
config.memSpec->tXS);
} else if (lastCommand.getCommand() == Command::AutoRefresh) {
} else
reportFatal("Refresh Checker",

4
DRAMSys/library/src/simulation/DramDDR3.cpp
View File

@@ -107,8 +107,8 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
memTimingSpec.WTR_S = memSpec->tWTR_S / clk;
memTimingSpec.XP = memSpec->tXP / clk;
memTimingSpec.XPDLL = memSpec->tXPDLL / clk;
memTimingSpec.XS = memSpec->tXSR / clk;
memTimingSpec.XSDLL = memSpec->tXSRDLL / clk;
memTimingSpec.XS = memSpec->tXS / clk;
memTimingSpec.XSDLL = memSpec->tXSDLL / clk;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;

4
DRAMSys/library/src/simulation/DramDDR4.cpp
View File

@@ -107,8 +107,8 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
memTimingSpec.WTR_S = memSpec->tWTR_S / clk;
memTimingSpec.XP = memSpec->tXP / clk;
memTimingSpec.XPDLL = memSpec->tXPDLL / clk;
memTimingSpec.XS = memSpec->tXSR / clk;
memTimingSpec.XSDLL = memSpec->tXSRDLL / clk;
memTimingSpec.XS = memSpec->tXS / clk;
memTimingSpec.XSDLL = memSpec->tXSDLL / clk;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;

4
DRAMSys/library/src/simulation/DramWideIO.cpp
View File

@@ -125,8 +125,8 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
memTimingSpec.WTR_S = memSpec->tWTR_S / clk;
memTimingSpec.XP = memSpec->tXP / clk;
memTimingSpec.XPDLL = memSpec->tXPDLL / clk;
memTimingSpec.XS = memSpec->tXSR / clk;
memTimingSpec.XSDLL = memSpec->tXSRDLL / clk;
memTimingSpec.XS = memSpec->tXS / clk;
memTimingSpec.XSDLL = memSpec->tXSDLL / clk;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;

22
DRAMSys/traceAnalyzer/scripts/tests.py
View File

@@ -36,8 +36,8 @@ class DramConfig(object):
tCKE = 0 # min time in pdna or pdnp
tXP = 0 # min delay to row access command after pdnpx pdnax
tXPDLL = 0 # min delay to row access command after pdnpx pdnax for dll commands
tXSR = 0 # min delay to row access command after srefx
tXSRDLL = 0 # min delay to row access command after srefx for dll commands
tXS = 0 # min delay to row access command after srefx
tXSDLL = 0 # min delay to row access command after srefx for dll commands
tAL = 0 # additive delay (delayed execution in dram)
tRFC = 0 # min ref->act delay 1X
tRFC2 = 0 # min ref->act delay 2X
@@ -84,8 +84,8 @@ class DramConfig(object):
self.tCKE = self.clk * memspec.getIntValue("CKE")
self.tXP = self.clk * memspec.getIntValue("XP")
self.tXPDLL = self.tXP
self.tXSR = self.clk * memspec.getIntValue("XS")
self.tXSRDLL = self.tXSR
self.tXS = self.clk * memspec.getIntValue("XS")
self.tXSDLL = self.tXS
self.tAL = self.clk * memspec.getIntValue("AL")
self.tRFC = self.clk * memspec.getIntValue("RFC")
self.tREFI = self.clk * memspec.getIntValue("REFI")
@@ -111,8 +111,8 @@ class DramConfig(object):
self.tCKE = self.clk * memspec.getIntValue("CKE")
self.tXP = self.clk * memspec.getIntValue("XP")
self.tXPDLL = self.clk * memspec.getIntValue("XPDLL")
self.tXSR = self.clk * memspec.getIntValue("XS")
self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL")
self.tXS = self.clk * memspec.getIntValue("XS")
self.tXSDLL = self.clk * memspec.getIntValue("XSDLL")
self.tAL = self.clk * memspec.getIntValue("AL")
self.tRFC = self.clk * memspec.getIntValue("RFC")
self.tRFC2 = self.clk * memspec.getIntValue("RFC2")
@@ -140,8 +140,8 @@ class DramConfig(object):
self.tCKE = self.clk * memspec.getIntValue("CKE")
self.tXP = self.clk * memspec.getIntValue("XP")
self.tXPDLL = self.clk * memspec.getIntValue("XPDLL")
self.tXSR = self.clk * memspec.getIntValue("XS")
self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL")
self.tXS = self.clk * memspec.getIntValue("XS")
self.tXSDLL = self.clk * memspec.getIntValue("XSDLL")
self.tAL = self.clk * memspec.getIntValue("AL")
self.tRFC = self.clk * memspec.getIntValue("RFC")
self.tREFI = self.clk * memspec.getIntValue("REFI")
@@ -374,7 +374,7 @@ def timing_constraint(FirstPhase, SecondPhase):
return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXP - dramconfig.clk
elif (FirstPhaseName == "SREF"):
return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXSR - dramconfig.clk
return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXS - dramconfig.clk
return 0
@@ -694,8 +694,8 @@ def read_holds_dll_constraint_after_sref(connection):
for currentRow in cursor:
if (currentRow[2] in ["RD", "RDA"] and lastRow[2] == 'SREF'):
srefEndToRead = currentRow[1] - (lastRow[1] - dramconfig.clk)
if (srefEndToRead < dramconfig.tXSRDLL):
return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}".format(currentRow[0], formatTime(srefEndToRead), lastRow[0], formatTime(dramconfig.tXSRDLL)))
if (srefEndToRead < dramconfig.tXSDLL):
return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}".format(currentRow[0], formatTime(srefEndToRead), lastRow[0], formatTime(dramconfig.tXSDLL)))
lastRow = currentRow
return TestSuceeded()