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Added specific MemSpecs, commit not running!

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This commit is contained in:
Lukas Steiner (2)
2019-06-17 17:41:46 +02:00
parent 24a8f7f483
commit a97a20b148
3 changed files with 96 additions and 43 deletions
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3
DRAMSys/library/src/controller/core/ControllerCore.cpp
View File

@@ -87,6 +87,8 @@ ControllerCore::ControllerCore(sc_module_name /*name*/,
if (config.RowGranularRef) {
refreshManager = new RGR("RGR", *this);
// TODO: How to use asserts with new memspec?
/*
assert(config.getTrasb() <= config.memSpec.tRAS);
assert(config.getTrasb() >= config.memSpec.tRCD);
assert(config.getTrrdb_L() <= config.memSpec.tRRD_L);
@@ -94,6 +96,7 @@ ControllerCore::ControllerCore(sc_module_name /*name*/,
assert(config.getTrpb() <= config.memSpec.tRP);
assert(config.getTrcb() <= config.memSpec.tRC);
assert(config.getTfawb() <= config.memSpec.tNAW);
*/
} else {
if (config.BankwiseLogic) {
refreshManager = new RefreshManagerBankwise("refManagerBw", *this);

70
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
View File

@@ -101,34 +101,6 @@ void ConfigurationLoader::loadConfigFromUri(Configuration &config,
loadConfig(config, e);
}
void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri)
{
tinyxml2::XMLDocument doc;
config.memspecUri = memspecUri;
loadXML(memspecUri, doc);
XMLElement *memspec = doc.FirstChildElement("memspec");
loadMemSpec(config, memspec);
}
void ConfigurationLoader::loadMemSpec(Configuration &config,
XMLElement *memspec)
{
config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId");
config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType");
if (config.memSpec.MemoryType == "DDR4") {
loadDDR4(config, memspec);
} else if (config.memSpec.MemoryType == "DDR3") {
loadDDR3(config, memspec);
} else if (config.memSpec.MemoryType == "LPDDR4") {
loadLPDDR4(config, memspec);
} else if (config.memSpec.MemoryType == "WIDEIO_SDR") {
loadWideIO(config, memspec);
} else {
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
}
void ConfigurationLoader::loadMCConfig(Configuration &config,
string mcconfigUri)
{
@@ -155,6 +127,48 @@ void ConfigurationLoader::loadMCConfig(Configuration &config,
}
void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri)
{
tinyxml2::XMLDocument doc;
config.memspecUri = memspecUri;
loadXML(memspecUri, doc);
XMLElement *memspec = doc.FirstChildElement("memspec");
loadMemSpec(config, memspec);
}
void ConfigurationLoader::loadMemSpec(Configuration &config,
XMLElement *memspec)
{
config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId");
config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType");
std::cout << "Before" << std::endl;
if (config.memSpec.MemoryType == "DDR4") {
delete(&Configuration::getInstance().memSpec);
Configuration::getInstance().memSpec =
*new MemSpecDDR4;
loadDDR4(config, memspec);
} else if (config.memSpec.MemoryType == "DDR3") {
delete(&Configuration::getInstance().memSpec);
Configuration::getInstance().memSpec =
*new MemSpecDDR3;
loadDDR3(config, memspec);
} else if (config.memSpec.MemoryType == "LPDDR4") {
delete(&Configuration::getInstance().memSpec);
Configuration::getInstance().memSpec =
*new MemSpecLPDDR4;
loadLPDDR4(config, memspec);
} else if (config.memSpec.MemoryType == "WIDEIO_SDR") {
delete(&Configuration::getInstance().memSpec);
Configuration::getInstance().memSpec =
*new MemSpecWideIO;
loadWideIO(config, memspec);
} else {
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
std::cout << "After" << std::endl;
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
{
//MemArchitecture

66
DRAMSys/library/src/controller/core/configuration/MemSpec.h
View File

@@ -41,7 +41,8 @@
#include <map>
#include "../../../common/dramExtensions.h"
struct RefreshTiming {
struct RefreshTiming
{
RefreshTiming() {}
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tRFC2(SC_ZERO_TIME),
tRFC4(SC_ZERO_TIME), tREFI(tREFI) {}
@@ -53,7 +54,8 @@ struct RefreshTiming {
sc_time tREFI;
};
struct MemSpec {
struct MemSpec
{
MemSpec()
{
//default DDR4
@@ -89,24 +91,31 @@ struct MemSpec {
// Memspec Variables:
double clkMHz;
sc_time clk;
sc_time tRP; //precharge-time (pre -> act same bank)
sc_time tRP; //precharge-time (pre -> act same bank
sc_time tRTP; //Read to precharge
sc_time tRCD; //act -> read/write
sc_time tRL; //read latency (read command start to data strobe)
sc_time tWL; //write latency
sc_time tWR; //write recovery (write to precharge)
sc_time tCKESR; //min time in sref
sc_time tCKE; //min time in pdna or pdnp
sc_time tRFC; //min ref->act delay 1X mode
sc_time tRFC2; //min ref->act delay 2X mode
sc_time tRFC4; //min ref->act delay 4X mode
sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI
// TODO: move to specific memspecs
sc_time tRPAB; //precharge-all time only for LPDDR4
sc_time tRAS; //active-time (act -> pre same bank)
sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd
sc_time tCCD_L;
sc_time tRTP; //Read to precharge
sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group)
sc_time tRRD_L; //.. (same bank group)
sc_time tRCD; //act -> read/write
sc_time tNAW; //n activate window
sc_time tRL; //read latency (read command start to data strobe)
sc_time tWL; //write latency
sc_time tWR; //write recovery (write to precharge)
sc_time tWTR_S; //write to read (different bank group)
sc_time tWTR_L; //.. (same bank group)
sc_time tCKESR; //min time in sref
sc_time tCKE; //min time in pdna or pdnp
sc_time tXP; //min delay to row access command after pdnpx pdnax
sc_time tXPDLL; //min delay to row access command after pdnpx pdnax for dll commands
sc_time tXSR; //min delay to row access command after srefx
@@ -114,11 +123,6 @@ struct MemSpec {
sc_time tAL; //additive delay (delayed execution in dram)
sc_time tDQSCK;
sc_time tRFC; //min ref->act delay 1X mode
sc_time tRFC2; //min ref->act delay 2X mode
sc_time tRFC4; //min ref->act delay 4X mode
sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI
// Currents and Voltages:
double iDD0;
double iDD02;
@@ -164,5 +168,37 @@ struct MemSpec {
}
};
struct MemSpecDDR3 : public MemSpec
{
MemSpecDDR3()
{
std::cout << "Generated MemSpecDDR3" << std::endl;
}
};
struct MemSpecDDR4 : public MemSpec
{
MemSpecDDR4()
{
std::cout << "Generated MemSpecDDR4" << std::endl;
}
};
struct MemSpecWideIO : public MemSpec
{
MemSpecWideIO()
{
std::cout << "Generated MemSpecWideIO" << std::endl;
}
};
struct MemSpecLPDDR4 : public MemSpec
{
MemSpecLPDDR4()
{
std::cout << "Generated MemSpecLPDDR4" << std::endl;
}
};
#endif // MEMSPEC_H