Included doxygen config.
This commit is contained in:
1
.gitignore
vendored
1
.gitignore
vendored
@@ -21,3 +21,4 @@ DRAMSys/analyzer/scripts/__pycache__/
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*.autosave
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*__pycache__*
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DRAMSys/gem5/boot_linux/linux-aarch32-ael.img
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DRAMSys/docs/doxygen
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1228
DRAMSys/docs/doxyCfg.cfg
Normal file
1228
DRAMSys/docs/doxyCfg.cfg
Normal file
File diff suppressed because it is too large
Load Diff
@@ -78,7 +78,7 @@ using namespace tlm;
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DECLARE_EXTENDED_PHASE(PendingRequest);
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class Controller: public sc_module, public IController
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class Controller : public sc_module, public IController
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{
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public:
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Controller(sc_module_name /*name*/) :
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@@ -54,7 +54,7 @@
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using namespace std;
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using namespace tlm;
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struct Arbiter: public sc_module {
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struct Arbiter : public sc_module {
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public:
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tlm_utils::multi_passthrough_initiator_socket<Arbiter> iSocket;
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tlm_utils::multi_passthrough_target_socket<Arbiter> tSocket;
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@@ -66,7 +66,8 @@ public:
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// Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called.
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iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);
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for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i) {
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for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i)
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{
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channelIsFree.push_back(true);
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pendingRequests.push_back(queue<tlm_generic_payload *>());
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}
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@@ -84,32 +85,16 @@ private:
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vector<bool> channelIsFree;
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//used to account for the request_accept_delay in the dram controllers
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// used to account for the request_accept_delay in the dram controllers
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// This is a queue of new transactions. The phase of a new request is BEGIN_REQ.
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vector<queue<tlm_generic_payload *>> pendingRequests;
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//used to account for the response_accept_delay in the initiators (traceplayer,core etc.)
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// used to account for the response_accept_delay in the initiators (traceplayer, core etc.)
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// This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP.
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std::map<unsigned int, queue<tlm_generic_payload *>> receivedResponses;
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//used to map the transaction from devices to the arbiter's target socket ID.
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// used to map the transaction from devices to the arbiter's target socket ID.
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std::map<tlm_generic_payload *, int> routeMap;
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// Initiated by dram side
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// This function is called when an arbiter's initiator socket receives a transaction from a memory controller
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tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload,
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tlm_phase &phase, sc_time &bwDelay)
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{
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// Check channel ID
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if ((unsigned int)channelId != DramExtension::getExtension(
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payload).getChannel().ID()) {
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SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted");
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}
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printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " +
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bwDelay.to_string());
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payloadEventQueue.notify(payload, phase, bwDelay);
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return TLM_ACCEPTED;
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}
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// Initiated by initiator side
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// This function is called when an arbiter's target socket receives a transaction from a device
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@@ -118,7 +103,8 @@ private:
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{
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sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) -
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(sc_time_stamp() + fwDelay);
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if (phase == BEGIN_REQ) {
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if (phase == BEGIN_REQ)
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{
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// adjust address offset:
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payload.set_address(payload.get_address() -
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Configuration::getInstance().AddressOffset);
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@@ -130,7 +116,9 @@ private:
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// It will extracted from the payload and used later.
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appendDramExtension(id, payload);
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payload.acquire();
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} else if (phase == END_RESP) {
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}
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else if (phase == END_RESP)
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{
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notDelay += Configuration::getInstance().memSpec.clk;
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// Erase before the payload is released.
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routeMap.erase(&payload);
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@@ -143,6 +131,21 @@ private:
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return TLM_ACCEPTED;
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}
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// Initiated by dram side
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// This function is called when an arbiter's initiator socket receives a transaction from a memory controller
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tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload,
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tlm_phase &phase, sc_time &bwDelay)
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{
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// Check channel ID
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if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID())
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SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted");
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printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " +
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bwDelay.to_string());
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payloadEventQueue.notify(payload, phase, bwDelay);
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return TLM_ACCEPTED;
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}
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virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans)
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{
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// adjust address offset:
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@@ -164,7 +167,8 @@ private:
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assert(channelId < Configuration::getInstance().NumberOfMemChannels);
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// Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter)
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if (phase == BEGIN_REQ) {
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if (phase == BEGIN_REQ)
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{
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if (channelIsFree[channelId]) {
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// This channel was available. Forward the new transaction to the memory controller.
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channelIsFree[channelId] = false;
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@@ -173,21 +177,7 @@ private:
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// This channel is busy. Enqueue the new transaction which phase is BEGIN_REQ.
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pendingRequests[channelId].push(&payload);
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}
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} else if (phase == END_RESP) {
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// Send the END_RESP message to the memory
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sendToChannel(channelId, payload, phase, SC_ZERO_TIME);
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// Drop one element of the queue of BEGIN_RESP from memory to this device
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receivedResponses[initiatorSocket].pop();
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// Check if there are queued transactoins with phase BEGIN_RESP from memory to this device
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if (!receivedResponses[initiatorSocket].empty()) {
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// The queue is not empty.
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tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front();
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// Send ONE extra BEGIN_RESP to the device
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sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME);
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}
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}
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// Phases initiated by the target side from arbiter's point of view (memory side)
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else if (phase == END_REQ) {
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channelIsFree[channelId] = true;
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@@ -207,7 +197,9 @@ private:
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// Mark the channel as busy again.
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channelIsFree[channelId] = false;
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}
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} else if (phase == BEGIN_RESP) {
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}
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else if (phase == BEGIN_RESP)
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{
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// Validate the initiatorSocket ID
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if ((int)initiatorSocket != routeMap[&payload]) {
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SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted");
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@@ -221,10 +213,25 @@ private:
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// Enqueue the transaction in BEGIN_RESP phase until the initiator
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// device acknowledge it (phase changes to END_RESP).
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receivedResponses[initiatorSocket].push(&payload);
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} else {
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}
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else if (phase == END_RESP)
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{
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// Send the END_RESP message to the memory
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sendToChannel(channelId, payload, phase, SC_ZERO_TIME);
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// Drop one element of the queue of BEGIN_RESP from memory to this device
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receivedResponses[initiatorSocket].pop();
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// Check if there are queued transactoins with phase BEGIN_RESP from memory to this device
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if (!receivedResponses[initiatorSocket].empty()) {
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// The queue is not empty.
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tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front();
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// Send ONE extra BEGIN_RESP to the device
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sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME);
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}
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}
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else
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SC_REPORT_FATAL(0,
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"Payload event queue in arbiter was triggered with unknown phase");
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}
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}
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void sendToChannel(unsigned int channelId, tlm_generic_payload &payload,
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