derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Renaming of commands, TODOs in timing checkers.

Browse Source
This commit is contained in:
Lukas Steiner (2)
2019-07-05 16:17:52 +02:00
parent 37b2dc9e4d
commit cb393b8abf
10 changed files with 69 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
DRAMSys/library/src/controller/Command.cpp
View File

@@ -67,29 +67,29 @@ std::string commandToString(Command command)
return "ACT";
break;
case Command::PREA:
return "PRE_ALL";
return "PREA";
break;
case Command::REFA:
return "REF";
return "REFA";
break;
case Command::PDEA:
return "PDNA";
return "PDEA";
break;
case Command::PDXA:
return "PDNAX";
return "PDXA";
break;
case Command::PDEP:
return "PDNP";
return "PDEP";
break;
case Command::PDXP:
return "PDNPX";
return "PDXP";
break;
case Command::SREFEN:
return "SREF";
return "SREFEN";
break;
case Command::SREFEX:
return "SREFX";
return "SREFEX";
break;
case Command::NOP:

2
DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp
View File

@@ -70,7 +70,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS);
} else {
reportFatal("ActB Checker",
"ActB can not follow " + commandToString(lcb.getCommand()));
"ACTB can not follow " + commandToString(lcb.getCommand()));
}
}
ScheduledCommand lc;

2
DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -76,7 +76,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
config.memSpec->tXS);
} else
reportFatal("Activate Checker",
"Activate can not follow " + commandToString(lastCommandOnBank.getCommand()));
"ACT can not follow " + commandToString(lastCommandOnBank.getCommand()));
}
delay_to_satisfy_activateToActivate_sameBank(command);

67
DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp
View File

@@ -38,37 +38,6 @@
#include "PowerDownChecker.h"
#include "../../timingCalculations.h"
sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd,
Command pdnCmd) const
{
sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA
|| pdnCmd == Command::PDEP);
sc_time constraint;
if (lastCmd == Command::RD || lastCmd == Command::RDA) {
constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk;
} else if (lastCmd == Command::WR) {
constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR;
} else if (lastCmd == Command::WRA) {
constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->clk;
} else if (lastCmd == Command::REFA) {
constraint = config.memSpec->tRFC_old;
} else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) {
constraint = config.memSpec->tXP;
} else if (lastCmd == Command::SREFEX) {
constraint = config.memSpec->tXS;
} else if (lastCmd == Command::PRE || lastCmd == Command::PREA) {
constraint = config.memSpec->tRP_old;
} else {
reportFatal("Powerdown checker",
commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd));
}
return constraint;
}
void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand &command)
const
{
@@ -97,7 +66,7 @@ const
{
lastSchedCmd = state.getLastScheduledCommand();
}
// TODO: Why do we only need to check the last scheduled command? bank_0_RDA -> bank_1_PRE -> SREFEN violates timing
if (lastSchedCmd.isValidCommand()) {
// Get the start time for the last scheduled command
sc_time lastSchedCmdStart = lastSchedCmd.getStart();
@@ -129,3 +98,37 @@ const
state.bus.moveCommandToNextFreeSlot(command);
}
sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd,
Command pdnCmd) const
{
sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA
|| pdnCmd == Command::PDEP);
sc_time constraint;
if (lastCmd == Command::RD || lastCmd == Command::RDA) {
constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk;
} else if (lastCmd == Command::WR) {
constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR;
} else if (lastCmd == Command::WRA) {
constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->clk;
// TODO: for SREFEN the constraint is tRFC, for PDEP it is tREFPDEN, PDEA cannot be the next command after REFA (all banks closed)
} else if (lastCmd == Command::REFA) {
constraint = config.memSpec->tRFC_old;
// TODO: for PDEA/PDEP the constraint is tCLK, for SREFEN it is tXP
} else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) {
constraint = config.memSpec->tXP;
} else if (lastCmd == Command::SREFEX) {
constraint = config.memSpec->tXS;
// TODO: for PDEA/PDEP the constraint is tPRPDEN, for SREFEN the constraint is tRP
} else if (lastCmd == Command::PRE || lastCmd == Command::PREA) {
constraint = config.memSpec->tRP_old;
// TODO: ACT -> PDEA missing (tACTPDEN)
} else {
reportFatal("Powerdown checker",
commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd));
}
return constraint;
}

6
DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp
View File

@@ -39,6 +39,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
sc_assert(cmd.getCommand() == Command::PREB);
ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank());
if (lastCmd.isValidCommand()) {
// TODO: unused?
if (lastCmd.getCommand() == Command::PREB) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(),
Configuration::getInstance().getTrpb());
@@ -46,6 +47,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old);
} else if (lastCmd.getCommand() == Command::PREA) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old);
// ------------
} else if (lastCmd.getCommand() == Command::ACTB) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(),
config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok!
@@ -60,13 +62,15 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP);
} else {
reportFatal("PreB Checker",
"PreB can not follow " + commandToString(lastCmd.getCommand()));
"PREB can not follow " + commandToString(lastCmd.getCommand()));
}
}
ScheduledCommand lc;
// TODO: unused?
if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) {
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old);
}
// ------------
if ((lc = state.getLastCommand(Command::ACT,
cmd.getBank())).isValidCommand()) {
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS);

8
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
View File

@@ -48,10 +48,12 @@ const
for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) {
ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank));
if (lastCommand.isValidCommand()) {
// TODO: Where do these dependencies come from?
if (lastCommand.getCommand() == Command::PRE
|| lastCommand.getCommand() == Command::PREB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tRP_old);
// TODO: Why tRCD and not tRAS?
} else if (lastCommand.getCommand() == Command::ACT
|| lastCommand.getCommand() == Command::ACTB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
@@ -59,12 +61,14 @@ const
} else if (lastCommand.getCommand() == Command::RD) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tRTP);
// TODO: missing
} else if (lastCommand.getCommand() == Command::RDA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tRTP + config.memSpec->tRP_old);
} else if (lastCommand.getCommand() == Command::WR) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR);
// TODO: missing
} else if (lastCommand.getCommand() == Command::WRA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR +
@@ -72,6 +76,7 @@ const
} else if (lastCommand.getCommand() == Command::REFA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tRFC_old);
// TODO: PREA after PDXP possible?
} else if (lastCommand.getCommand() == Command::PDXA
|| lastCommand.getCommand() == Command::PDXP) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
@@ -81,12 +86,13 @@ const
config.memSpec->tXS);
} else
reportFatal("Precharge All Checker",
"Precharge All can not follow " + commandToString(lastCommand.getCommand()));
"PREA can not follow " + commandToString(lastCommand.getCommand()));
}
}
ScheduledCommand lastActivate = state.getLastCommand(Command::ACT,
command.getBank());
// TODO: Why do we only check the ACT of one bank? (always bank 0)
if (lastActivate.isValidCommand()) {
command.establishMinDistanceFromStart(lastActivate.getStart(),
config.memSpec->tRAS);

5
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp
View File

@@ -49,6 +49,7 @@ const
if (lastCommand.isValidCommand()) {
// the first two cases happen when a resfresh interrups the command sequence of a transaction
// (e.g. commands to process transaction are PRE-ACT-RD and refresh happens after the PRE or after the ACT)
// TODO: unused?
if (lastCommand.getCommand() == Command::PRE
|| lastCommand.getCommand() == Command::PREB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
@@ -58,7 +59,7 @@ const
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tRCD);
}
// -------------
else if (lastCommand.getCommand() == Command::RD) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tRTP);
@@ -71,7 +72,7 @@ const
config.memSpec->tXP);
} else
reportFatal("Precharge Checker",
"Precharge can not follow " + commandToString(lastCommand.getCommand()));
"PRE can not follow " + commandToString(lastCommand.getCommand()));
}
ScheduledCommand lastActivate = state.getLastCommand(Command::ACT,

7
DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp
View File

@@ -59,13 +59,13 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
} else if (lastCommand.getCommand() == Command::WR) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
ReadChecker::writeToRead(lastCommand, command));
} else if (lastCommand.getCommand() == Command::PDXP
|| lastCommand.getCommand() == Command::PDXA) {
} else if (/*lastCommand.getCommand() == Command::PDXP
|| */lastCommand.getCommand() == Command::PDXA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tXP);
} else
reportFatal("Read Checker",
"Read can not follow " + commandToString(lastCommand.getCommand()));
"RD/RDA can not follow " + commandToString(lastCommand.getCommand()));
}
while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) {
@@ -126,6 +126,7 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead,
MemSpec *config = Configuration::getInstance().memSpec;
sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ?
config->tCCD_L_old : config->tCCD_S_old;
// TODO: When is tCCD smaller than readAccessTime?
return max(tCCD, config->getReadAccessTime());
}

2
DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp
View File

@@ -68,7 +68,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
} else if (lastCommandOnBank.getCommand() == Command::REFA) {
} else
reportFatal("Refresh Checker",
"Refresh can not follow " + commandToString(lastCommandOnBank.getCommand()));
"REFA can not follow " + commandToString(lastCommandOnBank.getCommand()));
}
} else {
for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) {

7
DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp
View File

@@ -59,13 +59,13 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
} else if (lastCommand.getCommand() == Command::WR) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
WriteChecker::writeToWrite(lastCommand, command));
} else if (lastCommand.getCommand() == Command::PDXP
|| lastCommand.getCommand() == Command::PDXA) {
} else if (/*lastCommand.getCommand() == Command::PDXP
|| */lastCommand.getCommand() == Command::PDXA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec->tXP);
} else
reportFatal("Write Checker",
"Write can not follow " + commandToString(lastCommand.getCommand()));
"WR/WRA can not follow " + commandToString(lastCommand.getCommand()));
}
while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) {
@@ -117,6 +117,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite,
MemSpec *config = Configuration::getInstance().memSpec;
sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ?
config->tCCD_L_old : config->tCCD_S_old;
// TODO: When is tCCD smaller than writeAccessTime?
return max(tCCD, config->getWriteAccessTime());
}