From cb393b8abf33c301dddd7088f413c14ac6a99aad Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 5 Jul 2019 16:17:52 +0200 Subject: [PATCH] Renaming of commands, TODOs in timing checkers. --- DRAMSys/library/src/controller/Command.cpp | 16 ++--- .../core/scheduling/checker/ActBChecker.cpp | 2 +- .../scheduling/checker/ActivateChecker.cpp | 2 +- .../scheduling/checker/PowerDownChecker.cpp | 67 ++++++++++--------- .../core/scheduling/checker/PreBChecker.cpp | 6 +- .../checker/PrechargeAllChecker.cpp | 8 ++- .../scheduling/checker/PrechargeChecker.cpp | 5 +- .../core/scheduling/checker/ReadChecker.cpp | 7 +- .../scheduling/checker/RefreshChecker.cpp | 2 +- .../core/scheduling/checker/WriteChecker.cpp | 7 +- 10 files changed, 69 insertions(+), 53 deletions(-) diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index ed6310ab..fc2474ce 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -67,29 +67,29 @@ std::string commandToString(Command command) return "ACT"; break; case Command::PREA: - return "PRE_ALL"; + return "PREA"; break; case Command::REFA: - return "REF"; + return "REFA"; break; case Command::PDEA: - return "PDNA"; + return "PDEA"; break; case Command::PDXA: - return "PDNAX"; + return "PDXA"; break; case Command::PDEP: - return "PDNP"; + return "PDEP"; break; case Command::PDXP: - return "PDNPX"; + return "PDXP"; break; case Command::SREFEN: - return "SREF"; + return "SREFEN"; break; case Command::SREFEX: - return "SREFX"; + return "SREFEX"; break; case Command::NOP: diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 68bff558..31c33d15 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -70,7 +70,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS); } else { reportFatal("ActB Checker", - "ActB can not follow " + commandToString(lcb.getCommand())); + "ACTB can not follow " + commandToString(lcb.getCommand())); } } ScheduledCommand lc; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 34eebb18..db6e0b86 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -76,7 +76,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tXS); } else reportFatal("Activate Checker", - "Activate can not follow " + commandToString(lastCommandOnBank.getCommand())); + "ACT can not follow " + commandToString(lastCommandOnBank.getCommand())); } delay_to_satisfy_activateToActivate_sameBank(command); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 3da88984..48c35d9e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -38,37 +38,6 @@ #include "PowerDownChecker.h" #include "../../timingCalculations.h" -sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, - Command pdnCmd) const -{ - sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA - || pdnCmd == Command::PDEP); - - sc_time constraint; - - if (lastCmd == Command::RD || lastCmd == Command::RDA) { - constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; - } else if (lastCmd == Command::WR) { - constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; - } else if (lastCmd == Command::WRA) { - constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->clk; - } else if (lastCmd == Command::REFA) { - constraint = config.memSpec->tRFC_old; - } else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) { - constraint = config.memSpec->tXP; - } else if (lastCmd == Command::SREFEX) { - constraint = config.memSpec->tXS; - } else if (lastCmd == Command::PRE || lastCmd == Command::PREA) { - constraint = config.memSpec->tRP_old; - } else { - reportFatal("Powerdown checker", - commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); - } - - return constraint; -} - void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { @@ -97,7 +66,7 @@ const { lastSchedCmd = state.getLastScheduledCommand(); } - + // TODO: Why do we only need to check the last scheduled command? bank_0_RDA -> bank_1_PRE -> SREFEN violates timing if (lastSchedCmd.isValidCommand()) { // Get the start time for the last scheduled command sc_time lastSchedCmdStart = lastSchedCmd.getStart(); @@ -129,3 +98,37 @@ const state.bus.moveCommandToNextFreeSlot(command); } +sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, + Command pdnCmd) const +{ + sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA + || pdnCmd == Command::PDEP); + + sc_time constraint; + + if (lastCmd == Command::RD || lastCmd == Command::RDA) { + constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; + } else if (lastCmd == Command::WR) { + constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; + } else if (lastCmd == Command::WRA) { + constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->clk; + // TODO: for SREFEN the constraint is tRFC, for PDEP it is tREFPDEN, PDEA cannot be the next command after REFA (all banks closed) + } else if (lastCmd == Command::REFA) { + constraint = config.memSpec->tRFC_old; + // TODO: for PDEA/PDEP the constraint is tCLK, for SREFEN it is tXP + } else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) { + constraint = config.memSpec->tXP; + } else if (lastCmd == Command::SREFEX) { + constraint = config.memSpec->tXS; + // TODO: for PDEA/PDEP the constraint is tPRPDEN, for SREFEN the constraint is tRP + } else if (lastCmd == Command::PRE || lastCmd == Command::PREA) { + constraint = config.memSpec->tRP_old; + // TODO: ACT -> PDEA missing (tACTPDEN) + } else { + reportFatal("Powerdown checker", + commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); + } + + return constraint; +} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 2d879775..907dcb73 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -39,6 +39,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const sc_assert(cmd.getCommand() == Command::PREB); ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank()); if (lastCmd.isValidCommand()) { + // TODO: unused? if (lastCmd.getCommand() == Command::PREB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), Configuration::getInstance().getTrpb()); @@ -46,6 +47,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); } else if (lastCmd.getCommand() == Command::PREA) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); + // ------------ } else if (lastCmd.getCommand() == Command::ACTB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok! @@ -60,13 +62,15 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP); } else { reportFatal("PreB Checker", - "PreB can not follow " + commandToString(lastCmd.getCommand())); + "PREB can not follow " + commandToString(lastCmd.getCommand())); } } ScheduledCommand lc; + // TODO: unused? if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } + // ------------ if ((lc = state.getLastCommand(Command::ACT, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 5c934c64..aede0f2d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -48,10 +48,12 @@ const for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); if (lastCommand.isValidCommand()) { + // TODO: Where do these dependencies come from? if (lastCommand.getCommand() == Command::PRE || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRP_old); + // TODO: Why tRCD and not tRAS? } else if (lastCommand.getCommand() == Command::ACT || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -59,12 +61,14 @@ const } else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP); + // TODO: missing } else if (lastCommand.getCommand() == Command::RDA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); + // TODO: missing } else if (lastCommand.getCommand() == Command::WRA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + @@ -72,6 +76,7 @@ const } else if (lastCommand.getCommand() == Command::REFA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRFC_old); + // TODO: PREA after PDXP possible? } else if (lastCommand.getCommand() == Command::PDXA || lastCommand.getCommand() == Command::PDXP) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -81,12 +86,13 @@ const config.memSpec->tXS); } else reportFatal("Precharge All Checker", - "Precharge All can not follow " + commandToString(lastCommand.getCommand())); + "PREA can not follow " + commandToString(lastCommand.getCommand())); } } ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + // TODO: Why do we only check the ACT of one bank? (always bank 0) if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), config.memSpec->tRAS); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index de3ff162..50c67c43 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -49,6 +49,7 @@ const if (lastCommand.isValidCommand()) { // the first two cases happen when a resfresh interrups the command sequence of a transaction // (e.g. commands to process transaction are PRE-ACT-RD and refresh happens after the PRE or after the ACT) + // TODO: unused? if (lastCommand.getCommand() == Command::PRE || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -58,7 +59,7 @@ const command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); } - + // ------------- else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP); @@ -71,7 +72,7 @@ const config.memSpec->tXP); } else reportFatal("Precharge Checker", - "Precharge can not follow " + commandToString(lastCommand.getCommand())); + "PRE can not follow " + commandToString(lastCommand.getCommand())); } ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 9abd6981..1683a30b 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -59,13 +59,13 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), ReadChecker::writeToRead(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::PDXP - || lastCommand.getCommand() == Command::PDXA) { + } else if (/*lastCommand.getCommand() == Command::PDXP + || */lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else reportFatal("Read Checker", - "Read can not follow " + commandToString(lastCommand.getCommand())); + "RD/RDA can not follow " + commandToString(lastCommand.getCommand())); } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { @@ -126,6 +126,7 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? config->tCCD_L_old : config->tCCD_S_old; + // TODO: When is tCCD smaller than readAccessTime? return max(tCCD, config->getReadAccessTime()); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index fd618673..48b45eeb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -68,7 +68,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommandOnBank.getCommand() == Command::REFA) { } else reportFatal("Refresh Checker", - "Refresh can not follow " + commandToString(lastCommandOnBank.getCommand())); + "REFA can not follow " + commandToString(lastCommandOnBank.getCommand())); } } else { for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index 1d262b08..e9136ef7 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -59,13 +59,13 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), WriteChecker::writeToWrite(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::PDXP - || lastCommand.getCommand() == Command::PDXA) { + } else if (/*lastCommand.getCommand() == Command::PDXP + || */lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else reportFatal("Write Checker", - "Write can not follow " + commandToString(lastCommand.getCommand())); + "WR/WRA can not follow " + commandToString(lastCommand.getCommand())); } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { @@ -117,6 +117,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? config->tCCD_L_old : config->tCCD_S_old; + // TODO: When is tCCD smaller than writeAccessTime? return max(tCCD, config->getWriteAccessTime()); }