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Included timing parameters for RGR.

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This commit is contained in:
Lukas Steiner (2)
2019-07-02 14:25:53 +02:00
parent ffdc67945a
commit 41cc447d86
4 changed files with 64 additions and 29 deletions
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2
DRAMSys/library/src/controller/core/configuration/Configuration.h
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@@ -88,6 +88,7 @@ struct Configuration
unsigned int NumberOfMemChannels = 1;
bool ControllerCoreRefDisable = false;
bool RowGranularRef = false;
// TODO: will be removed in the future
unsigned int trasbclk = 0;
sc_time getTrasb();
unsigned int trrdblclk = 0;
@@ -100,6 +101,7 @@ struct Configuration
sc_time getTrcb();
unsigned int tfawbclk = 0;
sc_time getTfawb();
// -----------------------------------
bool RGRB0 = true;
bool RGRB1 = true;
bool RGRB2 = true;

38
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
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@@ -199,7 +199,11 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
memSpec->tCL = clk * queryUIntParameter(timings, "CL");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRAS_ORGR = parameterExists(timings, "RAS_ORGR") ?
clk * queryUIntParameter(timings, "RAS_ORGR") : memSpec->tRAS;
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRC_ORGR = parameterExists(timings, "RC_ORGR") ?
clk * queryUIntParameter(timings, "RC_ORGR") : memSpec->tRC;
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
@@ -228,10 +232,16 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
sc_time clk = memSpec->clk;
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ?
clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW;
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ?
clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP;
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ?
clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD;
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
@@ -296,11 +306,19 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ?
clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW;
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ?
clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP;
memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_S_ORGR = parameterExists(timings, "RRD_S_ORGR") ?
clk * queryUIntParameter(timings, "RRD_S_ORGR") : memSpec->tRRD_S;
memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
memSpec->tRRD_L_ORGR = parameterExists(timings, "RRD_L_ORGR") ?
clk * queryUIntParameter(timings, "RRD_L_ORGR") : memSpec->tRRD_L;
memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
@@ -373,19 +391,24 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tCCDMW = clk * queryUIntParameter(timings, "CCDMW");
memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ?
clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW;
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tREFIAB = clk * queryUIntParameter(timings, "REFIAB");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIAB");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCAB = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB");
memSpec->tRPPB = clk * queryUIntParameter(timings, "RPPB");
memSpec->tRPPB_ORGR = parameterExists(timings, "RPPB_ORGR") ?
clk * queryUIntParameter(timings, "RPPB_ORGR") : memSpec->tRPPB;
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ?
clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD;
// TODO: old timings, will me removed
memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB");
memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD");
memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD");
memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD");
@@ -397,6 +420,7 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XS");
memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB");
memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB");
memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) {
@@ -444,11 +468,15 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ?
clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP;
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ?
clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD;
memSpec->tTAW = clk * queryUIntParameter(timings, "TAW");
memSpec->tTAW_ORGR = parameterExists(timings, "TAW_ORGR") ?
clk * queryUIntParameter(timings, "TAW_ORGR") : memSpec->tTAW;
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
// TODO: old timings, will me removed

39
DRAMSys/library/src/controller/core/configuration/MemSpec.h
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@@ -90,7 +90,9 @@ struct MemSpec
sc_time tCL; // unused, will be used in the future
sc_time tDQSCK;
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRAS_ORGR;
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRC_ORGR;
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tRTP; // read to precharge
@@ -172,10 +174,13 @@ struct MemSpecDDR3 : public MemSpec
{
sc_time tCCD;
sc_time tFAW;
sc_time tFAW_ORGR;
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tRP_ORGR;
sc_time tRRD;
sc_time tRRD_ORGR;
sc_time tWTR;
sc_time tXPDLL;
sc_time tXSDLL;
@@ -186,11 +191,15 @@ struct MemSpecDDR4 : public MemSpec
sc_time tCCD_S;
sc_time tCCD_L;
sc_time tFAW;
sc_time tFAW_ORGR;
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tRP_ORGR;
sc_time tRRD_S;
sc_time tRRD_S_ORGR;
sc_time tRRD_L;
sc_time tRRD_L_ORGR;
sc_time tWTR_S;
sc_time tWTR_L;
sc_time tXPDLL;
@@ -200,25 +209,13 @@ struct MemSpecDDR4 : public MemSpec
virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override;
};
struct MemSpecWideIO : public MemSpec
{
sc_time tCCD;
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tRRD;
sc_time tTAW;
sc_time tWTR;
sc_time tXPDLL;
sc_time tXSDLL;
};
struct MemSpecLPDDR4 : public MemSpec
{
sc_time tCCD;
sc_time tCCDMW;
sc_time tESCKE;
sc_time tFAW;
sc_time tFAW_ORGR;
sc_time tWTR;
sc_time tPPD;
sc_time tREFIAB;
@@ -227,7 +224,23 @@ struct MemSpecLPDDR4 : public MemSpec
sc_time tRFCPB;
sc_time tRPAB;
sc_time tRPPB;
sc_time tRPPB_ORGR;
sc_time tRRD;
sc_time tRRD_ORGR;
};
struct MemSpecWideIO : public MemSpec
{
sc_time tCCD;
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tRP_ORGR;
sc_time tRRD;
sc_time tRRD_ORGR;
sc_time tTAW;
sc_time tTAW_ORGR;
sc_time tWTR;
};
#endif // MEMSPEC_H

14
DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h
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@@ -46,27 +46,19 @@
class ScheduledCommand
{
public:
ScheduledCommand(Command command, sc_time start, sc_time executionTime,
const DramExtension &extension) :
command(command), start(start), executionTime(executionTime),
end(start + executionTime),
extension(extension)
{
}
end(start + executionTime), extension(extension) {}
ScheduledCommand(Command command, sc_time start, sc_time executionTime,
const tlm::tlm_generic_payload &payload) :
ScheduledCommand(command, start, executionTime,
DramExtension::getExtension(payload))
{
}
DramExtension::getExtension(payload)) {}
ScheduledCommand() :
command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME),
end(SC_ZERO_TIME), extension()
{
}
end(SC_ZERO_TIME), extension() {}
bool isNoCommand() const;
bool isValidCommand() const;