Included GenericController for later verilator inclusion.

DRAMSys/library/library.pro

@@ -229,7 +229,8 @@ HEADERS += \
     src/simulation/DramDDR4.h \
     src/simulation/DramRecordable.h \
     src/simulation/DramWideIO.h \
-    src/controller/core/scheduling/checker/CheckerDDR3.h
+    src/controller/core/scheduling/checker/CheckerDDR3.h \
+    src/controller/GenericController.h
     #src/common/third_party/json/include/nlohmann/json.hpp \
 
 thermalsim = $$(THERMALSIM)

DRAMSys/library/src/controller/Controller.cpp

@@ -35,11 +35,13 @@
  *    Felipe S. Prado
  */
 
-#include "core/configuration/Configuration.h"
 #include "Controller.h"
-#include <iostream>
 
-Controller::Controller(sc_module_name /*name*/) :
+#include <iostream>
+#include "core/configuration/Configuration.h"
+
+Controller::Controller(sc_module_name name) :
+    GenericController(name),
     frontendPEQ(this, &Controller::frontendPEQCallback),
     dramPEQ(this, &Controller::dramPEQCallback),
     controllerCorePEQ(this, &Controller::controllerCorePEQCallback),
@@ -47,9 +49,6 @@ Controller::Controller(sc_module_name /*name*/) :
 {
     controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem);
     buildScheduler();
-    iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw);
-    tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw);
-    tSocket.register_transport_dbg(this, &Controller::transport_dbg);
 }
 
 Controller::~Controller()

DRAMSys/library/src/controller/Controller.h

@@ -71,13 +71,14 @@
 #include "scheduler/FrFcfsGrp.h"
 #include "scheduler/SMS.h"
 #include "scheduler/IScheduler.h"
+#include "GenericController.h"
 
 using namespace std;
 using namespace tlm;
 
 DECLARE_EXTENDED_PHASE(PendingRequest);
 
-class Controller : public sc_module, public IController
+class Controller : public GenericController, public IController
 {
 public:
     Controller(sc_module_name);
@@ -96,9 +97,6 @@ public:
     virtual void send(Trigger trigger, sc_time time,
                       tlm_generic_payload &payload) override;
 
-    tlm_utils::simple_target_socket<Controller> tSocket;
-    tlm_utils::simple_initiator_socket<Controller> iSocket;
-
     unsigned int getTotalNumberOfPayloadsInSystem();
     void scheduleNextFromScheduler(Bank bank) override;
 
@@ -141,7 +139,7 @@ protected:
     IScheduler *scheduler;
     std::map<Bank, int> numberOfPayloadsInSystem;
     std::vector<gp *> refreshCollisionRequets;
-    tlm::tlm_generic_payload *backpressure = NULL;
+    tlm_generic_payload *backpressure = NULL;
     std::queue<gp *> responseQueue;
 
     tlm_utils::peq_with_cb_and_phase<Controller> frontendPEQ;

DRAMSys/library/src/controller/GenericController.h

@@ -0,0 +1,42 @@
+#ifndef GENERICCONTROLLER_H
+#define GENERICCONTROLLER_H
+
+#include <systemc>
+#include <tlm>
+#include <tlm_utils/simple_initiator_socket.h>
+#include <tlm_utils/simple_target_socket.h>
+
+// Utiliy class to pass around the DRAMSys, without having to propagate the template defintions
+// throughout all classes
+class GenericController : public sc_module
+{
+public:
+    // Already create and bind sockets to the virtual functions
+    tlm_utils::simple_target_socket<GenericController> tSocket; // DRAMSys side
+    tlm_utils::simple_initiator_socket<GenericController> iSocket; // DRAM side
+
+    // Bind sockets with virtual functions
+    SC_HAS_PROCESS(GenericController);
+    GenericController(sc_module_name name) :
+        sc_module(name), tSocket("tSocket"), iSocket("iSocket")
+    {
+        tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw);
+        tSocket.register_transport_dbg(this, &GenericController::transport_dbg);
+        iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw);
+    }
+
+    // Destructor
+    virtual ~GenericController() {}
+
+    // Virtual transport functions
+    virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
+                                               tlm::tlm_phase &phase,
+                                               sc_time &delay) = 0;
+    virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans) = 0;
+    virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
+                                               tlm::tlm_phase &phase,
+                                               sc_time &delay) = 0;
+};
+
+
+#endif // GENERICCONTROLLER_H

DRAMSys/library/src/controller/core/configuration/MemSpec.cpp

@@ -40,6 +40,26 @@
 #include "../../Command.h"
 #include "Configuration.h"
 
+const std::vector<Bank> &MemSpec::getBanks() const
+{
+    static std::vector<Bank> banks;
+    if (banks.size() == 0) {
+        for (unsigned int i = 0; i < NumberOfBanks; i++)
+            banks.push_back(Bank(i));
+    }
+    return banks;
+}
+
+sc_time MemSpec::getReadAccessTime() const
+{
+    return clk * (BurstLength / DataRate);
+}
+
+sc_time MemSpec::getWriteAccessTime() const
+{
+    return clk * (BurstLength / DataRate);
+}
+
 sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const
 {
     if (command == Command::PDNA || command == Command::PDNP)

DRAMSys/library/src/controller/core/configuration/MemSpec.h

@@ -58,33 +58,17 @@ struct RefreshTiming
 
 struct MemSpec
 {
-    sc_time getWriteAccessTime() const
-    {
-        return clk * (BurstLength / DataRate);
-    }
+    const std::vector<Bank> &getBanks() const;
 
-    sc_time getReadAccessTime() const
-    {
-        return clk * (BurstLength / DataRate);
-    }
+    sc_time getWriteAccessTime() const;
+
+    sc_time getReadAccessTime() const;
 
     // Returns the minimum execution time for commands that have a variable execution time
     sc_time getMinExecutionTimeForPowerDownCmd(Command command) const;
 
     virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const;
 
-    const std::vector<Bank> &getBanks() const
-    {
-        static std::vector<Bank> banks;
-        if (banks.size() == 0) {
-            for (unsigned int i = 0; i < NumberOfBanks; i++) {
-                banks.push_back(Bank(i));
-            }
-        }
-
-        return banks;
-    }
-
     std::string MemoryId = "not defined.";
     std::string MemoryType = "not defined.";
 

DRAMSys/library/src/simulation/DRAMSys.cpp

@@ -252,7 +252,7 @@ void DRAMSys::instantiateModules(const string &traceName,
             i++) {
         std::string str = "controller" + std::to_string(i);
 
-        Controller *controller;
+        GenericController *controller;
         if (recordingEnabled)
             controller = new RecordableController(str.c_str(), tlmRecorders[i]);
         else

DRAMSys/library/src/simulation/DRAMSys.h

@@ -52,6 +52,7 @@
 #include "../common/third_party/tinyxml2/tinyxml2.h"
 #include "../common/tlm2_base_protocol_checker.h"
 #include "../error/eccbaseclass.h"
+#include "../controller/GenericController.h"
 
 class DRAMSys : public sc_module
 {
@@ -87,7 +88,7 @@ private:
     // All transactions pass through the same arbiter
     Arbiter *arbiter;
     // Each DRAM unit has a controller
-    std::vector<Controller *> controllers;
+    std::vector<GenericController *> controllers;
 
     // TODO: Each DRAM has a reorder buffer (check this!)
     ReorderBuffer *reorder;

DRAMSys/library/src/simulation/Dram.h

@@ -43,7 +43,7 @@
 #include <tlm>
 #include <systemc>
 #include <tlm_utils/simple_target_socket.h>
-#include "../controller/Controller.h"
+#include "../common/protocol.h"
 #include "../controller/core/configuration/Configuration.h"
 #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 

DRAMSys/library/src/simulation/DramDDR3.cpp

@@ -41,5 +41,5 @@
 DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
 {
     if (StoreMode == StorageMode::ErrorModel)
-        SC_REPORT_FATAL("DramDDR3", "Error Model for DDR3 not supported");
+        SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3");
 }

DRAMSys/library/src/simulation/DramDDR3.h

@@ -36,9 +36,9 @@
 #ifndef DRAMDDR3_H
 #define DRAMDDR3_H
 
-#include "Dram.h"
 #include <systemc>
 #include <tlm>
+#include "Dram.h"
 
 class DramDDR3 : public Dram
 {

DRAMSys/library/src/simulation/DramDDR4.cpp

@@ -41,5 +41,5 @@
 DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
 {
     if (StoreMode == StorageMode::ErrorModel)
-        SC_REPORT_FATAL("DramDDR4", "Error Model for DDR4 not supported");
+        SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4");
 }

DRAMSys/library/src/simulation/DramDDR4.h

@@ -36,9 +36,9 @@
 #ifndef DRAMDDR4_H
 #define DRAMDDR4_H
 
-#include "Dram.h"
 #include <systemc>
 #include <tlm>
+#include "Dram.h"
 
 class DramDDR4 : public Dram
 {