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Renaming of ControllerNew to Controller.

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This commit is contained in:
Lukas Steiner (2)
2019-09-11 09:59:51 +02:00
parent 7827a5f869
commit 7fd5f05d3e
7 changed files with 35 additions and 35 deletions
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4
DRAMSys/library/library.pro
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@@ -124,7 +124,7 @@ SOURCES += \
src/simulation/DramWideIO.cpp \
src/controller/core/configuration/MemSpec.cpp \
src/controller/BankMachine.cpp \
src/controller/ControllerNew.cpp \
src/controller/Controller.cpp \
src/controller/scheduler/SchedulerFifo.cpp \
src/controller/scheduler/SchedulerFrFcfs.cpp \
src/controller/cmdmux/CmdMuxStrict.cpp \
@@ -188,7 +188,7 @@ HEADERS += \
src/simulation/DramWideIO.h \
src/controller/GenericController.h \
src/controller/BankMachine.h \
src/controller/ControllerNew.h \
src/controller/Controller.h \
src/controller/scheduler/SchedulerIF.h \
src/controller/scheduler/SchedulerFifo.h \
src/controller/scheduler/SchedulerFrFcfs.h \

2
DRAMSys/library/src/controller/BankMachine.h
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@@ -39,7 +39,7 @@
#include <tlm.h>
#include <utility>
#include "../common/dramExtensions.h"
#include "ControllerNew.h"
#include "Controller.h"
#include "Command.h"
#include "scheduler/SchedulerIF.h"
#include "checker/CheckerIF.h"

34
DRAMSys/library/src/controller/ControllerNew.cpp → DRAMSys/library/src/controller/Controller.cpp
View File

@@ -32,7 +32,7 @@
* Author: Lukas Steiner
*/
#include "ControllerNew.h"
#include "Controller.h"
#include "core/configuration/Configuration.h"
#include "scheduler/SchedulerFifo.h"
@@ -48,7 +48,7 @@
#include "refresh/RefreshManagerDummy.h"
#include "refresh/RefreshManagerBankwise.h"
ControllerNew::ControllerNew(sc_module_name name) :
Controller::Controller(sc_module_name name) :
GenericController(name)
{
SC_METHOD(controllerMethod);
@@ -63,7 +63,7 @@ ControllerNew::ControllerNew(sc_module_name name) :
else if (config.memSpec->MemoryType == "WIDEIO_SDR")
checker = new CheckerWideIO();
else
SC_REPORT_FATAL("ControllerNew", "Unsupported DRAM type");
SC_REPORT_FATAL("Controller", "Unsupported DRAM type");
if (config.ControllerCoreRefDisable)
refreshManager = new RefreshManagerDummy();
@@ -89,7 +89,7 @@ ControllerNew::ControllerNew(sc_module_name name) :
commandMux = new CmdMuxOldest();
}
else
SC_REPORT_FATAL("ControllerNew", "Selected scheduler not supported");
SC_REPORT_FATAL("Controller", "Selected scheduler not supported");
for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++)
bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID));
@@ -97,7 +97,7 @@ ControllerNew::ControllerNew(sc_module_name name) :
startBandwidthIdleCollector();
}
ControllerNew::~ControllerNew()
Controller::~Controller()
{
endBandwithIdleCollector();
@@ -109,7 +109,7 @@ ControllerNew::~ControllerNew()
delete checker;
}
void ControllerNew::controllerMethod()
void Controller::controllerMethod()
{
// (1) Release payload if arbiter has accepted the result
if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/)
@@ -178,7 +178,7 @@ void ControllerNew::controllerMethod()
}
}
tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans,
tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
sc_time notificationDelay = delay;
@@ -205,7 +205,7 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans,
return TLM_ACCEPTED;
}
tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans,
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " +
@@ -220,13 +220,13 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans,
return TLM_ACCEPTED;
}
unsigned int ControllerNew::transport_dbg(tlm_generic_payload &)
unsigned int Controller::transport_dbg(tlm_generic_payload &)
{
SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported");
SC_REPORT_FATAL("Controller", "Debug Transport not supported");
return 0;
}
void ControllerNew::releasePayload()
void Controller::releasePayload()
{
uint64_t id = DramExtension::getPayloadID(payloadToRelease);
PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system.");
@@ -240,7 +240,7 @@ void ControllerNew::releasePayload()
startBandwidthIdleCollector();
}
void ControllerNew::acquirePayload()
void Controller::acquirePayload()
{
uint64_t id = DramExtension::getPayloadID(payloadToAcquire);
PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system.");
@@ -256,13 +256,13 @@ void ControllerNew::acquirePayload()
payloadToAcquire = nullptr;
}
void ControllerNew::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)
void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)
{
sc_time delay = SC_ZERO_TIME;
tSocket->nb_transport_bw(*payload, phase, delay);
}
void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload)
void Controller::sendToDram(Command command, tlm_generic_payload *payload)
{
sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command);
ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload);
@@ -285,12 +285,12 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload)
else if (command == Command::REFB)
phase = BEGIN_REFB;
else
SC_REPORT_FATAL("ControllerNew", "Unknown phase");
SC_REPORT_FATAL("Controller", "Unknown phase");
iSocket->nb_transport_fw(*payload, phase, delay);
}
void ControllerNew::startBandwidthIdleCollector()
void Controller::startBandwidthIdleCollector()
{
if (!isIdle)
{
@@ -300,7 +300,7 @@ void ControllerNew::startBandwidthIdleCollector()
}
}
void ControllerNew::endBandwithIdleCollector()
void Controller::endBandwithIdleCollector()
{
if (isIdle)
{

14
DRAMSys/library/src/controller/ControllerNew.h → DRAMSys/library/src/controller/Controller.h
View File

@@ -32,8 +32,8 @@
* Author: Lukas Steiner
*/
#ifndef CONTROLLERNEW_H
#define CONTROLLERNEW_H
#ifndef CONTROLLER_H
#define CONTROLLER_H
#include <map>
#include <queue>
@@ -57,12 +57,12 @@ using namespace tlm;
class BankMachine;
class SchedulerIF;
class ControllerNew : public GenericController
class Controller : public GenericController
{
public:
ControllerNew(sc_module_name);
SC_HAS_PROCESS(ControllerNew);
virtual ~ControllerNew();
Controller(sc_module_name);
SC_HAS_PROCESS(Controller);
virtual ~Controller();
protected:
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &);
@@ -102,4 +102,4 @@ private:
void endBandwithIdleCollector();
};
#endif // CONTROLLERNEW_H
#endif // CONTROLLER_H

6
DRAMSys/library/src/controller/ControllerRecordable.cpp
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@@ -41,14 +41,14 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
recordPhase(trans, phase, delay);
return ControllerNew::nb_transport_fw(trans, phase, delay);
return Controller::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
recordPhase(trans, phase, delay);
return ControllerNew::nb_transport_bw(trans, phase, delay);
return Controller::nb_transport_bw(trans, phase, delay);
}
void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)
@@ -67,7 +67,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl
TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe();
tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload);
}
ControllerNew::sendToDram(command, payload);
Controller::sendToDram(command, payload);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)

6
DRAMSys/library/src/controller/ControllerRecordable.h
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@@ -35,14 +35,14 @@
#ifndef CONTROLLERRECORDABLE_H
#define CONTROLLERRECORDABLE_H
#include "ControllerNew.h"
#include "Controller.h"
#include "../common/TlmRecorder.h"
class ControllerRecordable final : public ControllerNew
class ControllerRecordable final : public Controller
{
public:
ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) :
ControllerNew(name), tlmRecorder(tlmRecorder) {}
Controller(name), tlmRecorder(tlmRecorder) {}
private:
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans,

4
DRAMSys/library/src/simulation/DRAMSys.cpp
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@@ -56,7 +56,7 @@
#include "DramDDR3.h"
#include "DramDDR4.h"
#include "DramWideIO.h"
#include "../controller/ControllerNew.h"
#include "../controller/Controller.h"
#include "../controller/ControllerRecordable.h"
using namespace std;
@@ -258,7 +258,7 @@ void DRAMSys::instantiateModules(const string &traceName,
if (recordingEnabled)
controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]);
else
controller = new ControllerNew(str.c_str());
controller = new Controller(str.c_str());
controllers.push_back(controller);
str = "dram" + std::to_string(i);