Commit Graph

17808 Commits

Author SHA1 Message Date
Jason Lowe-Power
403817cd0d arch-riscv,dev: Explicitly set num CPUs on platform
Previously, the RISC-V devices queried the system object in
SimObject::init() for the number of CPUs and the number of threads.
However, the system object doesn't actually count the number of
CPUs/threads until it runs init(). Therefore, we've just been getting
lucky in the order that the SimObject init() functions were called.

This change instead decouples these two functions and makes the number
of CPUs/threads a parameter for the RISC-V interrupt devices. This
change also updates the example config script.

Change-Id: Ic4da5604156837cfeec05e58d188b42a02420de1
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49431
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
182f79c3da configs: Fix component classic cache prefetchers
The prefetchers were instatiated as class variables instead of
instance variables. This change fixes the problem

Change-Id: I7263c9e7ddb138d2f9ad10024ea7f0e7d860dda9
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49430
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
0e5aa3da42 configs: Update how private L1/L2 cache handles MMU
This change makes an MMU cache per TLB port as is required by x86 and
RISC-V.

Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49364
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
9ce797e130 configs: Update component API for I/O
This change adds a check for coherent I/O ports from the board. This
change allows us to move some of the cache hierarchy specific code out
of the board and into the cache hierarchies.

Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49363
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
3a4e366042 configs: Update component API for memory size
This change updates the API in the component library for setting the
size of memory. Now, you can set the size of the memory system as an
argument to the memory object. Then, the board is responsible for
figuring out what the overall memory ranges should be which it
communicates back to the memory system.

This should make multi-channel memories easier to implement and it fixes
some confusion around things like the HiFive platform starting at
0x8000000.

Change-Id: Ibef5aafbbb1177a992950cdc2bd2634dcfb81eec
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49348
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
31c7d8cf46 configs: Remove unneeded ddr3 memory component
Change-Id: Id0228b4628c1be6dce3d7092731798bfa07de815
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49347
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
343ef29173 configs: Expose the MMU to the board in components
Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49346
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
3783cc0de0 configs: Move some runtime checks in components
The runtime coherence check should check the cache heirarchy, not the
global protocol so it can differentiate between Ruby and classic.
This patch also removes some unnecessary includes and fails earlier in
MESI_Two_Level if that protocol isn't built.

Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49345
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
b70aa23b5f configs: Create interrupts for ISAs other than x86
All CPUs need to have `createInterrupts()` called. Add a switch to check
for that in the caches and make the ports optional parameters.

Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49344
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-24 23:35:41 +00:00
Jason Lowe-Power
712096b866 configs: Remove KVM from default imports in components
Change-Id: I74028df1f775564ff16a41ab367ddad512db524c
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49343
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 23:35:41 +00:00
Daecheol You
82db312550 mem-ruby: Add (RUSC, LocalHN_Eviction) transition
During full system simulation on CHI, LocalHN_Eviction event on the RUSC
state occured occasionally. Thus, the change adds RUSC state to the transition.

Change-Id: Ibff382c38a092895bc03a4a64cf072ae752decf3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49263
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-24 00:17:32 +00:00
Gabe Black
cccf291c71 python: Get rid of the unused jobfile.py.
This was likely once for managing jobs sent to a batch processing
system, but it's not actually used anywhere in gem5.

Change-Id: I68025eaa45bde9eeb92145a4b91c8f4a184e5250
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49394
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-08-21 07:01:44 +00:00
Gabe Black
c0353b3dc8 scons: Get rid of a redundant import of code_formatter.
This module was already imported at the top of the SConscript.

Change-Id: I1357beda2adcc085c122df15397c769694a73fab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48361
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-08-21 00:58:43 +00:00
Gabe Black
e606db79d0 sim: Remove some code for python versions less than 3.
We no longer support those versions of python.

Change-Id: I8f7312d8c252e4491525aa13c7d091467b96af6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49411
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-08-21 00:56:07 +00:00
Gabe Black
e90cb8ab75 mem,sim: Replace the deprecated chatty_assert with gem5_assert.
The new gem5_assert macro now does the job of both regular asserts, and
chatty_assert, except that its condition must always be valid code. It
is still not evaluated if NDEBUG is set, though.

Change-Id: I7c9435311746b2e02fe7335bce6ba618bf9fd4eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48607
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-08-21 00:54:54 +00:00
Gabe Black
b8b9db1508 base: Extend gem5_assert to subsume chatty_assert.
If given more than just its condition, gem5_assert will assume it
should act like chatty_assert.

Because we have our own custom assert now anyway, we can fold the
behavior of both into one macro and make life easier for users.

Deprecate chatty_assert.

Change-Id: I43497b5333802a265c0ad096681f64ab6f0424b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48606
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-21 00:54:48 +00:00
Gabe Black
790b39848d util: Add USE_SYSTEMC=0 to the scons command line in tlm/README.
The CXX config code is not entirely correct, and will fail with some of
the objects defined for systemc support. If you're going to build gem5
with --with-cxx-config, you have to also disable the systemc support.
This had been updated in the gem5_with_systemc/README file, but not in
the tlm/README file.

Change-Id: Icd933e867c5e51fe8725a4a2c0925c41675ce4fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49453
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-21 00:53:58 +00:00
Gabe Black
92288331c2 gpu-compute: Delete code related to X86PagetableWalker in X86GPUTLB.py.
This code will never be executed since FULL_SYSTEM is not part of the
build environment (and hasn't been for many years), and on top of that,
this declaration redundantly (and incompletely) tries to set up the
X86PagetableWalker that the ISA already sets up.

Change-Id: I40cffbd7f60c1f741b1a14d9009f80185c9ce28c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49405
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-08-20 08:19:57 +00:00
Gabe Black
0eea587189 arm: Add methods to sync vector regs and vector reg elements.
If we've been using one and need to start using the other, this will
sync over the most up to date contents from the old one to the new one.

Change-Id: I8443928ac2d8694ee02fe8d2bf17dbf9a04e5a11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49145
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-17 00:08:32 +00:00
Gabe Black
b9b1de76d5 scons: Turn the ProtoBuf and GrpcProtoBuf classes into methods.
These now instantiate Builders for the protobuf .cc and .h files of the
right flavors, and install the .cc files as sources.

Also, this sets up the builder for .cc files so that it will know how to
build those files from .proto using the protobuf compiler. This is
optional, but will make it possible to pass .proto files in place of .cc
files or even object files as sources for other builders, and for scons
to figure out what chain of rules to use to get the desired results.

This is a step towards handing over more responsibility to scons and
eliminating at least some of our bespoke build code.

Change-Id: I7188a0917e999ad9148f7079830b2c26bcd563db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48134
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-14 14:54:16 +00:00
Gabe Black
5199f6b00d scons: Disable the duplicate-environment warning by default.
Disable warnings when targets can be built with multiple environments
but with the same actions. This can happen intentionally if, for
instance, a generated source file is used to build object files in
different ways in different environments, but generating the source
file itself is exactly the same. This can be re-enabled from the
command line if desired.

Change-Id: I426ca3331267f026553c9a2bccc79494cace8109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48133
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-14 14:54:16 +00:00
Gabe Black
8419df8adb scons: Delay evaluating the EXE_SUFFIX and ENV_LABEL values.
Delay evaluating these so that hopefully the same rules can be reused
between environments.

Change-Id: I4918d3a1a98f49ecad8ab6a8b89898c14316f6f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48132
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-14 14:54:16 +00:00
Gabe Black
0c6f38119d scons: Build up different environments for different binaries.
Rather than collect parameters describing what environments to use for
each binary, build up the environments themselves and skip the middle
man.

Change-Id: I57ff03a3522708396149b7d053dac014477859a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48131
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-14 14:54:16 +00:00
Gabe Black
b070d1523a arch-x86: Use existing constants to simplify some code in operands.isa.
The "predicate"s for reading/writing some condition code registers were
written with constants which were built up from other constants which
represent individual bits in the condition code register. There are
existing constants which already exactly match those sets of bits, so we
can just use those instead of building up the same thing in-situ.

Change-Id: Iab5a5de04d0fd858414451531a357770ca9fde14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49244
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-14 11:10:04 +00:00
Gabe Black
3815ad14d7 arch-x86: Fix how MediaOps sets the size of its operands.
Because MediaOps have two sizes, one for sources and one for
destinations, it does not have a single dataSize member to set the size
of its operands. This was difficult to correct at the time, so a
dataSize member was created which was fixed at 0, and the instructions
themselves would use srcSize and destSize internally to do the actual
computation.

That causes problems when tracing, since the printReg function needs to
know what size to use to print some registers properly, specifically
integer registers.

To now fix that problem, some SFINAE constructors have been added which
will either pass through a dataSize member if one exists, or pass
through a pointer to the instruction itself so that operand index
selector class can pick out the member that makes sense for it (destSize
for DestOp, srcSize for Src1Op and Src2Op).

Change-Id: I6b8259a5ab27f809b81453bcf987cc6d1be4811a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49203
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-08-14 05:41:54 +00:00
Gabe Black
a759336a08 arch-arm: Fix style in utility.hh.
Change-Id: I66262e63695680f5638ef057be05274445ba38ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49144
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-08-14 00:35:07 +00:00
Gabe Black
29b20c9742 arch-x86: Stop printing a source operand for the monitor instruction.
Like CPUID, all operands for this instruction are implicit and are not
written out when putting it into assembly. Stop printing a source
operand when generating disassembly in gem5.

Change-Id: I95898afdd9101ad393b3aace99536db602752a64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49225
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-08-14 00:31:43 +00:00
Gabe Black
4ee5461300 arch-x86: Stop printing a source register for CPUID.
When disassembling the CPUID instruction, we were (for some reason)
printing a source register after the mneomic. The registers CPUID uses
are fixed, and it has no operands when written in assembly.

Change-Id: I5aee7f7a93cb84977cfe1fe387c5184aa740bc0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49224
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-08-14 00:31:23 +00:00
Gabe Black
6903547957 cpu-o3: Fix minor style issue in rename_map.hh.
Change-Id: I670e504320b41e38666dab6eb7a83e4a39bc3b00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49146
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-12 22:01:30 +00:00
Gabe Black
7ffa9f8597 cpu: Simplify or eliminate set${type}Result methods for o3 and checker.
These methods are all identical now. The O3 versions can all be
consolidated into a single method. For the checker CPU, they can
actually be eliminated entirely, and the result queue's "emplace()"
method can be used to add items using less text than just calling the
original helper method.

Change-Id: Ifaeb3beeea257c8bbf951ee1dd8d2d5fd8bb3964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49128
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 20:24:54 +00:00
Gabe Black
91f7486482 cpu: Use std::variant to simplify InstResult.
std::variant is a similar to (and also modestly superior to)
MultiResult. Use it instead to simplify InstResult.

Change-Id: I22338f5e89814c6d13538129757158126013a414
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49127
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 20:24:54 +00:00
Gabe Black
7f540a333d x86: Fix disassembly of syscall instructions.
These *used* to have a source register which was the syscall number.
That was not an actual property of the instruction, it was a property of
the syscall mechanism in Linux which had leaked into the implementation
of the instructions themselves.

That was corrected by removing that source register and letting the
syscall handling layer figure out which system call to invoke.

Unfortunately the SyscallInst format wasn't also updated, and when
printing the disassembly for those instructions, it would try to print
that source register. That instruction doesn't bother to set up a source
operand array since it doesn't actually have any, so that ended up
accessing random memory.

Change-Id: I20890ad69605983305a13f414ca59a5fa35d4d06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49183
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 20:23:35 +00:00
Giacomo Travaglini
0a31476e1c arch-arm: Replace std::tie with C++17 structured binding
Change-Id: I856b60e91a0c8089ccc3560bdf9024b42206e170
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49084
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 08:20:34 +00:00
Gabe Black
1a4b6fbfe9 cpu: Get rid of double in InstResult::MultiResult.
Change-Id: Ib02b0e270e0a4fdfa036c0a271ff9c3ce2a98342
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
d5aeb809a7 cpu: Stop treating VecElem as its own case in InstResult.
Since this is now a RegVal, we can treat it as a Scalar result.

Change-Id: I0afd7815c1ebf20b50ce27a00b27bb408d2a32ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49125
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
9b1abd4d83 cpu: Use RegVal for VecElems instead of TheISA::VecElem.
If VecElem is a basic type, which is a reasonable assumption, it can be
contained in a RegVal. We still need to use the TheISA::VecElem type to
extract it from an actual vector, but then it can be passed around as a
RegVal.

Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49124
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
b7c1c9561b cpu: Fix style in the checker CPU class.
Change-Id: Ief2d716b515ab38aaa202be49ef144f2c04f532e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49129
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 23:22:01 +00:00
Gabe Black
27c186f436 cpu: Fix style in inst_res.hh.
Change-Id: Ifc6d980f5dc0cec8b6ac58e4fb390ed49e3e1a39
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49123
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 23:21:46 +00:00
Bobby R. Bruce
d8da636bbb tests: Fix ExcludeInterleavingRanges test for .fast comp
Change-Id: Ie3ebfc0caa52f11649f479066022734ac82e6d1b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49065
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 22:40:56 +00:00
Gabe Black
f183942ab8 cpu: Rename RegClassInfo to RegClass.
Change-Id: I0456462d5d306fc93a1fe160e45ff6b1b49f3c25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49103
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 20:04:51 +00:00
Giacomo Travaglini
aa3344e4a2 system-arm: Remove armv7 DTS from gem5
With this patch we are dropping support for armv7-based DTBs

Change-Id: Ic83b5ee790eda53a2341d8335cb01b86e4f62b0b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48983
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 12:41:41 +00:00
Giacomo Travaglini
4da35850fb python: Provide a repoPath helper function
The function will return the absolute path of the gem5 repo
hosting the m5 library.
One of the use of this helper is to effectively refer/import
gem5 modules from EXTRAS repositories.

If I wanted to import the Ruby module from configs/ruby I could
do that with:

from m5.util import addToPath, repoPath

configs_path = os.path.join(repoPath(), configs)
addToPath(configs_path)

from ruby import Ruby

This isn't an out of tree scripts utility only: most of our configs are
currently relying on doing relative backward imports and could be ported
to use the repoPath utility:

addToPath(../..) is quite a common pattern

This makes the dependencies difficult to read/track and a bit fragile
as it all relies on the relative position between modules.

Change-Id: I26f6ef34b44f20903cc1b6248330b6156378f40b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49083
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 08:42:52 +00:00
Gabe Black
967c076256 cpu: Fix style in src/cpu/o3/cpu.hh.
Change-Id: I08802e184dfc0c9b4d96bc3ddf07af3a3a7f4e81
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49108
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-07 15:15:57 +00:00
Gabe Black
b7aebc1220 scons: Further simplify the_gpu_isa.hh.
Turn the "namespace" function into a simple variable. Also, since the
only thing defined in the file is a macro, we can drop the compiler
guards and use that macro as its own compiler guard.

Change-Id: I1e8559fc7add61105b2990f76226714ba282581d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-07 03:12:56 +00:00
Gabe Black
774f801589 scons: Remove cruft from the_gpu_isa.hh.
Some values in the_gpu_isa.hh were simply copy/pasted from the_isa.hh,
and were not used at all in the code. This change removes them, leaving
only the definition of the TheGpuISA namespace.

Change-Id: I0d66ae84d78e990088eb8099c678b9cf1cc42748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48966
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-07 03:12:56 +00:00
Gabe Black
64168fd4ea scons: Turn the ISA and GPU ISA lists into construction variables.
Change-Id: I4135709f5bceee959b5178a4700656aa782b1d6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48965
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-07 03:12:56 +00:00
Gabe Black
a764139066 scons: Keep the list of all CPU models in a construction variable.
This relaxes ordering around CPU model declaration.

Change-Id: Ie5f8da1903a883bd4d98800dfbef7fd913021f77
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48964
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-07 03:12:56 +00:00
Bobby R. Bruce
c8ba86c214 tests: Update pip prior to installing gem5art packages
This fixes the `invalid command 'bdist_wheel'` error which may be
causing wider problems, as reported in this email thread:
https://www.mail-archive.com/gem5-dev@gem5.org/msg39790.html

The `bdist_wheel` package, a dependency of the `celery` package, was
not being installed correctly. The root cause of this
problem is not known, but solutions are presented here:
https://stackoverflow.com/questions/34819221/why-is-python-setup-py-saying-invalid-command-bdist-wheel-on-travis-ci

Upgrading pip prior to installing the gem5art packages seemed like the
simplest solution.

Change-Id: I1bd4e85871c37d0522e16a90ff6b8acc3fdd9f94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49044
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 17:16:40 +00:00
Bobby R. Bruce
de0e84e875 tests: Remove setuptools upgrade in gem5art-tests.sh
This upgrade is no longer needed as we test using the Ubuntu 20.04 image
which comes with the correct, up-to-date version of setup tools.

Change-Id: I194f26381f59f5ca3edea46696e6d5b2b0418719
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 17:16:40 +00:00
Gabe Black
2f053f1bc5 scons: Use a loop to build binary flavors.
Track structured data related to different binary flavors (opt, debug,
etc), using a class instead of various lists, etc. Also use a loop to
set up SCons environments to build these binaries instead of a spelled
out loop.

Change-Id: Ie35a914ab79342190e4cdc27a945a0fecd54a476
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48130
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-06 15:59:44 +00:00