configs: Expose the MMU to the board in components

Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49346
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

components_library/processors/abstract_core.py

@@ -28,7 +28,7 @@ from abc import ABCMeta, abstractmethod
 from typing import Optional
 from .cpu_types import CPUTypes
 
-from m5.objects import Port, SubSystem
+from m5.objects import BaseMMU, Port, SubSystem
 
 
 class AbstractCore(SubSystem):
@@ -91,3 +91,11 @@ class AbstractCore(SubSystem):
         optional ports can be implemented as cache ports.
         """
         raise NotImplementedError
+
+    @abstractmethod
+    def get_mmu(self) -> BaseMMU:
+        """ Return the MMU for this core.
+
+        This is used in the board to setup system-specific MMU settings.
+        """
+        raise NotImplementedError

components_library/processors/simple_core.py

@@ -33,6 +33,7 @@ from ..isas import ISA
 from ..utils.override import overrides
 
 from m5.objects import (
+    BaseMMU,
     Port,
     AtomicSimpleCPU,
     DerivO3CPU,
@@ -96,3 +97,7 @@ class SimpleCore(AbstractCore):
             self.core.interrupts[0].pio = interrupt_requestor
             self.core.interrupts[0].int_requestor = interrupt_responce
             self.core.interrupts[0].int_responder = interrupt_requestor
+
+    @overrides(AbstractCore)
+    def get_mmu(self) -> BaseMMU:
+        return self.core.mmu