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configs: Move some runtime checks in components

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The runtime coherence check should check the cache heirarchy, not the
global protocol so it can differentiate between Ruby and classic.
This patch also removes some unnecessary includes and fails earlier in
MESI_Two_Level if that protocol isn't built.

Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49345
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Jason Lowe-Power
2021-08-13 13:30:59 -07:00
committed by Jason Lowe-Power
parent b70aa23b5f
commit 3783cc0de0
3 changed files with 11 additions and 15 deletions
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3
components_library/boards/abstract_board.py
View File

@@ -29,9 +29,6 @@ from .mem_mode import MemMode
from m5.objects import System, Port, IOXBar, ClockDomain
from ..isas import ISA
from ..coherence_protocol import CoherenceProtocol
from typing import List

19
components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
View File

@@ -67,6 +67,16 @@ class MESITwoLevelCacheHierarchy(
l2_assoc: str,
num_l2_banks: int,
):
if (
get_runtime_coherence_protocol()
!= CoherenceProtocol.MESI_TWO_LEVEL
):
raise EnvironmentError(
"The MESITwoLevelCacheHierarchy must be used with with the "
"MESI_Two_Level coherence protocol."
)
AbstractRubyCacheHierarchy.__init__(self=self)
AbstractTwoLevelCacheHierarchy.__init__(
self,
@@ -81,15 +91,6 @@ class MESITwoLevelCacheHierarchy(
self._num_l2_banks = num_l2_banks
def incorporate_cache(self, board: AbstractBoard) -> None:
if (
get_runtime_coherence_protocol()
!= CoherenceProtocol.MESI_TWO_LEVEL
):
raise EnvironmentError(
"The MESITwoLevelCacheHierarchy must be used with with the "
"MESI_Two_Level coherence protocol."
)
cache_line_size = board.get_cache_line_size()
self.ruby_system = RubySystem()

4
components_library/processors/simple_processor.py
View File

@@ -34,8 +34,6 @@ from m5.util import warn
from .abstract_processor import AbstractProcessor
from .cpu_types import CPUTypes
from ..boards.abstract_board import AbstractBoard
from ..coherence_protocol import is_ruby
from ..runtime import get_runtime_coherence_protocol
from typing import List
@@ -79,7 +77,7 @@ class SimpleProcessor(AbstractProcessor):
elif self._cpu_type == CPUTypes.KVM:
board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
elif self._cpu_type == CPUTypes.ATOMIC:
if is_ruby(get_runtime_coherence_protocol()):
if board.get_cache_hierarchy().is_ruby():
warn(
"Using an atomic core with Ruby will result in "
"'atomic_noncaching' memory mode. This will skip caching "