diff --git a/components_library/boards/abstract_board.py b/components_library/boards/abstract_board.py
index 653c589895..4bece04f88 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -29,9 +29,6 @@ from .mem_mode import MemMode
 
 from m5.objects import System, Port, IOXBar, ClockDomain
 
-from ..isas import ISA
-from ..coherence_protocol import CoherenceProtocol
-
 from typing import List
 
 
diff --git a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index cc643e5b7e..0650613028 100644
--- a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++ b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -67,6 +67,16 @@ class MESITwoLevelCacheHierarchy(
         l2_assoc: str,
         num_l2_banks: int,
     ):
+
+        if (
+            get_runtime_coherence_protocol()
+            != CoherenceProtocol.MESI_TWO_LEVEL
+        ):
+            raise EnvironmentError(
+                "The MESITwoLevelCacheHierarchy must be used with with the "
+                "MESI_Two_Level coherence protocol."
+            )
+
         AbstractRubyCacheHierarchy.__init__(self=self)
         AbstractTwoLevelCacheHierarchy.__init__(
             self,
@@ -81,15 +91,6 @@ class MESITwoLevelCacheHierarchy(
         self._num_l2_banks = num_l2_banks
 
     def incorporate_cache(self, board: AbstractBoard) -> None:
-        if (
-            get_runtime_coherence_protocol()
-            != CoherenceProtocol.MESI_TWO_LEVEL
-        ):
-            raise EnvironmentError(
-                "The MESITwoLevelCacheHierarchy must be used with with the "
-                "MESI_Two_Level coherence protocol."
-            )
-
         cache_line_size = board.get_cache_line_size()
 
         self.ruby_system = RubySystem()
diff --git a/components_library/processors/simple_processor.py b/components_library/processors/simple_processor.py
index 4b45171221..e449173bd6 100644
--- a/components_library/processors/simple_processor.py
+++ b/components_library/processors/simple_processor.py
@@ -34,8 +34,6 @@ from m5.util import warn
 from .abstract_processor import AbstractProcessor
 from .cpu_types import CPUTypes
 from ..boards.abstract_board import AbstractBoard
-from ..coherence_protocol import is_ruby
-from ..runtime import get_runtime_coherence_protocol
 
 from typing import List
 
@@ -79,7 +77,7 @@ class SimpleProcessor(AbstractProcessor):
         elif self._cpu_type == CPUTypes.KVM:
             board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
         elif self._cpu_type == CPUTypes.ATOMIC:
-            if is_ruby(get_runtime_coherence_protocol()):
+            if board.get_cache_hierarchy().is_ruby():
                 warn(
                     "Using an atomic core with Ruby will result in "
                     "'atomic_noncaching' memory mode. This will skip caching "