configs: Create interrupts for ISAs other than x86

All CPUs need to have `createInterrupts()` called. Add a switch to check
for that in the caches and make the ports optional parameters.

Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49344
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

components_library/cachehierarchies/classic/no_cache.py

@@ -113,6 +113,8 @@ class NoCache(AbstractClassicCacheHierarchy):
                 int_req_port = self.membus.mem_side_ports
                 int_resp_port = self.membus.cpu_side_ports
                 core.connect_interrupt(int_req_port, int_resp_port)
+            else:
+                core.connect_interrupt()
 
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)

components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -157,3 +157,5 @@ class PrivateL1PrivateL2CacheHierarchy(
                 int_req_port = self.membus.mem_side_ports
                 int_resp_port = self.membus.cpu_side_ports
                 cpu.connect_interrupt(int_req_port, int_resp_port)
+            else:
+                cpu.connect_interrupt()

components_library/processors/abstract_core.py

@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from abc import ABCMeta, abstractmethod
+from typing import Optional
 from .cpu_types import CPUTypes
 
 from m5.objects import Port, SubSystem
@@ -81,6 +82,12 @@ class AbstractCore(SubSystem):
 
     @abstractmethod
     def connect_interrupt(
-        self, interrupt_requestor: Port, interrupt_responce: Port
+        self, interrupt_requestor: Optional[Port] = None,
+        interrupt_responce: Optional[Port] = None
     ) -> None:
+        """ Connect the core interrupts to the interrupt controller
+
+        This function is usually called from the cache hierarchy since the
+        optional ports can be implemented as cache ports.
+        """
         raise NotImplementedError

components_library/processors/simple_core.py

@@ -24,6 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from typing import Optional
 from components_library.runtime import get_runtime_isa
 from components_library.processors.abstract_core import AbstractCore
 
@@ -83,7 +84,8 @@ class SimpleCore(AbstractCore):
 
     @overrides(AbstractCore)
     def connect_interrupt(
-        self, interrupt_requestor: Port, interrupt_responce: Port
+        self, interrupt_requestor: Optional[Port] = None,
+        interrupt_responce: Optional[Port] = None
     ) -> None:
 
         # TODO: This model assumes that we will only create an interrupt