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cpu: Use RegVal for VecElems instead of TheISA::VecElem.

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If VecElem is a basic type, which is a reasonable assumption, it can be
contained in a RegVal. We still need to use the TheISA::VecElem type to
extract it from an actual vector, but then it can be passed around as a
RegVal.

Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49124
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-09 00:15:27 -07:00
parent b7c1c9561b
commit 9b1abd4d83
15 changed files with 48 additions and 54 deletions
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9
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -292,7 +292,7 @@ class ThreadContext : public gem5::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
const ArmISA::VecElem &
RegVal
readVecElem(const RegId &reg) const override
{
panic("%s not implemented.", __FUNCTION__);
@@ -327,7 +327,7 @@ class ThreadContext : public gem5::ThreadContext
}
void
setVecElem(const RegId& reg, const ArmISA::VecElem& val) override
setVecElem(const RegId& reg, RegVal val) override
{
panic("%s not implemented.", __FUNCTION__);
}
@@ -425,14 +425,13 @@ class ThreadContext : public gem5::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
const ArmISA::VecElem&
RegVal
readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
const ArmISA::VecElem &val) override
setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, RegVal val) override
{
panic("%s not implemented.", __FUNCTION__);
}

5
src/cpu/checker/cpu.hh
View File

@@ -213,7 +213,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->getWritableVecReg(reg);
}
TheISA::VecElem
RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -314,8 +314,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override
setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));

8
src/cpu/checker/thread_context.hh
View File

@@ -253,7 +253,7 @@ class CheckerThreadContext : public ThreadContext
return actualTC->getWritableVecReg(reg);
}
const TheISA::VecElem &
RegVal
readVecElem(const RegId& reg) const override
{
return actualTC->readVecElem(reg);
@@ -299,7 +299,7 @@ class CheckerThreadContext : public ThreadContext
}
void
setVecElem(const RegId& reg, const TheISA::VecElem& val) override
setVecElem(const RegId& reg, RegVal val) override
{
actualTC->setVecElem(reg, val);
checkerTC->setVecElem(reg, val);
@@ -449,7 +449,7 @@ class CheckerThreadContext : public ThreadContext
actualTC->setVecRegFlat(idx, val);
}
const TheISA::VecElem &
RegVal
readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
{
return actualTC->readVecElemFlat(idx, elem_idx);
@@ -457,7 +457,7 @@ class CheckerThreadContext : public ThreadContext
void
setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
const TheISA::VecElem& val) override
RegVal val) override
{
actualTC->setVecElemFlat(idx, elem_idx, val);
}

5
src/cpu/exec_context.hh
View File

@@ -123,12 +123,11 @@ class ExecContext
/** Vector Elem Interfaces. */
/** @{ */
/** Reads an element of a vector register. */
virtual TheISA::VecElem readVecElemOperand(
const StaticInst *si, int idx) const = 0;
virtual RegVal readVecElemOperand(const StaticInst *si, int idx) const = 0;
/** Sets a vector register to a value. */
virtual void setVecElemOperand(
const StaticInst *si, int idx, const TheISA::VecElem val) = 0;
const StaticInst *si, int idx, RegVal val) = 0;
/** @} */
/** Predicate registers interface. */

7
src/cpu/inst_res.hh
View File

@@ -41,6 +41,7 @@
#include <type_traits>
#include "arch/generic/vec_reg.hh"
#include "base/types.hh"
namespace gem5
{
@@ -50,10 +51,10 @@ class InstResult
public:
union MultiResult
{
uint64_t integer;
RegVal integer;
double dbl;
TheISA::VecRegContainer vector;
TheISA::VecElem vecElem;
RegVal vecElem;
TheISA::VecPredRegContainer pred;
MultiResult() {}
};
@@ -200,7 +201,7 @@ class InstResult
panic_if(!isVector(), "Converting scalar (or invalid) to vector!!");
return result.vector;
}
const TheISA::VecElem&
const RegVal&
asVectorElem() const
{
panic_if(!isVecElem(), "Converting scalar (or invalid) to vector!!");

5
src/cpu/minor/exec_context.hh
View File

@@ -176,7 +176,7 @@ class ExecContext : public gem5::ExecContext
return thread.getWritableVecReg(reg);
}
TheISA::VecElem
RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -235,8 +235,7 @@ class ExecContext : public gem5::ExecContext
}
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override
setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));

8
src/cpu/o3/cpu.cc
View File

@@ -1170,7 +1170,7 @@ CPU::getWritableVecReg(PhysRegIdPtr phys_reg)
return regFile.getWritableVecReg(phys_reg);
}
const TheISA::VecElem&
RegVal
CPU::readVecElem(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
@@ -1220,7 +1220,7 @@ CPU::setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer& val)
}
void
CPU::setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem& val)
CPU::setVecElem(PhysRegIdPtr phys_reg, RegVal val)
{
cpuStats.vecRegfileWrites++;
regFile.setVecElem(phys_reg, val);
@@ -1277,7 +1277,7 @@ CPU::getWritableArchVecReg(int reg_idx, ThreadID tid)
return getWritableVecReg(phys_reg);
}
const TheISA::VecElem&
RegVal
CPU::readArchVecElem(
const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const
{
@@ -1343,7 +1343,7 @@ CPU::setArchVecReg(int reg_idx, const TheISA::VecRegContainer& val,
void
CPU::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const TheISA::VecElem& val, ThreadID tid)
RegVal val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecElemClass, reg_idx, ldx));

8
src/cpu/o3/cpu.hh
View File

@@ -346,7 +346,7 @@ class CPU : public BaseCPU
vecMode = vec_mode;
}
const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
RegVal readVecElem(PhysRegIdPtr reg_idx) const;
const TheISA::VecPredRegContainer&
readVecPredReg(PhysRegIdPtr reg_idx) const;
@@ -361,7 +361,7 @@ class CPU : public BaseCPU
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer& val);
void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem& val);
void setVecElem(PhysRegIdPtr reg_idx, RegVal val);
void setVecPredReg(PhysRegIdPtr reg_idx,
const TheISA::VecPredRegContainer& val);
@@ -377,7 +377,7 @@ class CPU : public BaseCPU
/** Read architectural vector register for modification. */
TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
RegVal readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid) const;
const TheISA::VecPredRegContainer& readArchVecPredReg(
@@ -404,7 +404,7 @@ class CPU : public BaseCPU
ThreadID tid);
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const TheISA::VecElem& val, ThreadID tid);
RegVal val, ThreadID tid);
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);

5
src/cpu/o3/dyn_inst.hh
View File

@@ -1255,7 +1255,7 @@ class DynInst : public ExecContext, public RefCounted
return this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
}
TheISA::VecElem
RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
return this->cpu->readVecElem(this->regs.renamedSrcIdx(idx));
@@ -1306,8 +1306,7 @@ class DynInst : public ExecContext, public RefCounted
}
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override
setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
int reg_idx = idx;
this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);

6
src/cpu/o3/regfile.hh
View File

@@ -226,12 +226,12 @@ class PhysRegFile
}
/** Reads a vector element. */
const TheISA::VecElem &
RegVal
readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->is(VecElemClass));
auto ret = vectorRegFile[phys_reg->index()].as<TheISA::VecElem>();
const TheISA::VecElem& val = ret[phys_reg->elemIndex()];
RegVal val = ret[phys_reg->elemIndex()];
DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
" has data %#x\n", phys_reg->elemIndex(),
int(phys_reg->index()), val);
@@ -311,7 +311,7 @@ class PhysRegFile
/** Sets a vector register to the given value. */
void
setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem val)
setVecElem(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->is(VecElemClass));

4
src/cpu/o3/thread_context.cc
View File

@@ -176,7 +176,7 @@ ThreadContext::getWritableVecRegFlat(RegIndex reg_id)
return cpu->getWritableArchVecReg(reg_id, thread->threadId());
}
const TheISA::VecElem&
RegVal
ThreadContext::readVecElemFlat(RegIndex idx, const ElemIndex& elemIndex) const
{
return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
@@ -227,7 +227,7 @@ ThreadContext::setVecRegFlat(
void
ThreadContext::setVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex, const TheISA::VecElem& val)
const ElemIndex& elemIndex, RegVal val)
{
cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
conditionalSquash();

8
src/cpu/o3/thread_context.hh
View File

@@ -212,7 +212,7 @@ class ThreadContext : public gem5::ThreadContext
return getWritableVecRegFlat(flattenRegId(id).index());
}
const TheISA::VecElem &
RegVal
readVecElem(const RegId& reg) const override
{
return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
@@ -258,7 +258,7 @@ class ThreadContext : public gem5::ThreadContext
}
void
setVecElem(const RegId& reg, const TheISA::VecElem& val) override
setVecElem(const RegId& reg, RegVal val) override
{
setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
@@ -372,10 +372,10 @@ class ThreadContext : public gem5::ThreadContext
void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) override;
const TheISA::VecElem &readVecElemFlat(RegIndex idx,
RegVal readVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex) const override;
void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
const TheISA::VecElem& val) override;
RegVal val) override;
const TheISA::VecPredRegContainer&
readVecPredRegFlat(RegIndex idx) const override;

5
src/cpu/simple/exec_context.hh
View File

@@ -362,7 +362,7 @@ class SimpleExecContext : public ExecContext
}
/** Reads an element of a vector register. */
TheISA::VecElem
RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
execContextStats.numVecRegReads++;
@@ -373,8 +373,7 @@ class SimpleExecContext : public ExecContext
/** Sets an element of a vector register to a value. */
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override
setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);

11
src/cpu/simple_thread.hh
View File

@@ -306,13 +306,12 @@ class SimpleThread : public ThreadState, public ThreadContext
return regVal;
}
const TheISA::VecElem &
RegVal
readVecElem(const RegId &reg) const override
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < vecRegs.size());
const TheISA::VecElem& regVal =
readVecElemFlat(flatIndex, reg.elemIndex());
RegVal regVal = readVecElemFlat(flatIndex, reg.elemIndex());
DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
return regVal;
@@ -389,7 +388,7 @@ class SimpleThread : public ThreadState, public ThreadContext
}
void
setVecElem(const RegId &reg, const TheISA::VecElem &val) override
setVecElem(const RegId &reg, RegVal val) override
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < vecRegs.size());
@@ -520,7 +519,7 @@ class SimpleThread : public ThreadState, public ThreadContext
vecRegs[reg] = val;
}
const TheISA::VecElem &
RegVal
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
{
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
@@ -528,7 +527,7 @@ class SimpleThread : public ThreadState, public ThreadContext
void
setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
const TheISA::VecElem &val) override
RegVal val) override
{
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
}

8
src/cpu/thread_context.hh
View File

@@ -200,7 +200,7 @@ class ThreadContext : public PCEventScope
readVecReg(const RegId& reg) const = 0;
virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
virtual RegVal readVecElem(const RegId& reg) const = 0;
virtual const TheISA::VecPredRegContainer& readVecPredReg(
const RegId& reg) const = 0;
@@ -216,7 +216,7 @@ class ThreadContext : public PCEventScope
virtual void setVecReg(const RegId& reg,
const TheISA::VecRegContainer& val) = 0;
virtual void setVecElem(const RegId& reg, const TheISA::VecElem& val) = 0;
virtual void setVecElem(const RegId& reg, RegVal val) = 0;
virtual void setVecPredReg(const RegId& reg,
const TheISA::VecPredRegContainer& val) = 0;
@@ -291,10 +291,10 @@ class ThreadContext : public PCEventScope
virtual void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) = 0;
virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
virtual RegVal readVecElemFlat(RegIndex idx,
const ElemIndex& elem_idx) const = 0;
virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
const TheISA::VecElem& val) = 0;
RegVal val) = 0;
virtual const TheISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const = 0;