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arch-x86: Use existing constants to simplify some code in operands.isa.

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The "predicate"s for reading/writing some condition code registers were
written with constants which were built up from other constants which
represent individual bits in the condition code register. There are
existing constants which already exactly match those sets of bits, so we
can just use those instead of building up the same thing in-situ.

Change-Id: Iab5a5de04d0fd858414451531a357770ca9fde14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49244
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-13 17:36:30 -07:00
parent 3815ad14d7
commit b070d1523a
1 changed files with 15 additions and 20 deletions
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35
src/arch/x86/isa/operands.isa
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@@ -153,27 +153,22 @@ def operands {{
# would be retained, the write predicate checks if any of the bits
# are being written.
'PredccFlagBits': ('CCReg', 'uqw', '(X86ISA::CCREG_ZAPS)', None,
'PredccFlagBits': ('CCReg', 'uqw', 'X86ISA::CCREG_ZAPS', None,
60, None, None,
'''(((ext & (X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) !=
(X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) &&
((ext & (X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) != 0))''',
'''((ext & (X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) != 0)'''),
'PredcfofBits': ('CCReg', 'uqw', '(X86ISA::CCREG_CFOF)', None,
61, None, None, '''(((ext & X86ISA::CFBit) == 0 ||
(ext & X86ISA::OFBit) == 0) &&
((ext & (X86ISA::CFBit | X86ISA::OFBit)) != 0))''',
'((ext & (X86ISA::CFBit | X86ISA::OFBit)) != 0)'),
'PreddfBit': ('CCReg', 'uqw', '(X86ISA::CCREG_DF)', None,
62, None, None, '(false)', '((ext & X86ISA::DFBit) != 0)'),
'PredecfBit': ('CCReg', 'uqw', '(X86ISA::CCREG_ECF)', None,
63, None, None, '(false)', '((ext & X86ISA::ECFBit) != 0)'),
'PredezfBit': ('CCReg', 'uqw', '(X86ISA::CCREG_EZF)', None,
64, None, None, '(false)', '((ext & X86ISA::EZFBit) != 0)'),
'(ext & X86ISA::ccFlagMask) != X86ISA::ccFlagMask && '
'(ext & X86ISA::ccFlagMask) != 0',
'(ext & X86ISA::ccFlagMask) != 0'),
'PredcfofBits': ('CCReg', 'uqw', 'X86ISA::CCREG_CFOF', None,
61, None, None,
'(ext & X86ISA::cfofMask) != X86ISA::cfofMask && '
'(ext & X86ISA::cfofMask) != 0',
'(ext & X86ISA::cfofMask) != 0'),
'PreddfBit': ('CCReg', 'uqw', 'X86ISA::CCREG_DF', None,
62, None, None, 'false', '(ext & X86ISA::DFBit) != 0'),
'PredecfBit': ('CCReg', 'uqw', 'X86ISA::CCREG_ECF', None,
63, None, None, 'false', '(ext & X86ISA::ECFBit) != 0'),
'PredezfBit': ('CCReg', 'uqw', 'X86ISA::CCREG_EZF', None,
64, None, None, 'false', '(ext & X86ISA::EZFBit) != 0'),
# These register should needs to be more protected so that later
# instructions don't map their indexes with an old value.