From b070d1523adb1600b751123e2c09542319cf4533 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabe.black@gmail.com>
Date: Fri, 13 Aug 2021 17:36:30 -0700
Subject: [PATCH] arch-x86: Use existing constants to simplify some code in
 operands.isa.

The "predicate"s for reading/writing some condition code registers were
written with constants which were built up from other constants which
represent individual bits in the condition code register. There are
existing constants which already exactly match those sets of bits, so we
can just use those instead of building up the same thing in-situ.

Change-Id: Iab5a5de04d0fd858414451531a357770ca9fde14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49244
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/x86/isa/operands.isa | 35 +++++++++++++++--------------------
 1 file changed, 15 insertions(+), 20 deletions(-)

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 2bf253e7af..f07db14224 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -153,27 +153,22 @@ def operands {{
         # would be retained, the write predicate checks if any of the bits
         # are being written.
 
-        'PredccFlagBits': ('CCReg', 'uqw', '(X86ISA::CCREG_ZAPS)', None,
+        'PredccFlagBits': ('CCReg', 'uqw', 'X86ISA::CCREG_ZAPS', None,
                 60, None, None,
-                '''(((ext & (X86ISA::PFBit | X86ISA::AFBit |
-                          X86ISA::ZFBit | X86ISA::SFBit)) !=
-                  (X86ISA::PFBit | X86ISA::AFBit |
-                   X86ISA::ZFBit | X86ISA::SFBit)) &&
-                ((ext & (X86ISA::PFBit | X86ISA::AFBit |
-                         X86ISA::ZFBit | X86ISA::SFBit)) != 0))''',
-                '''((ext & (X86ISA::PFBit | X86ISA::AFBit |
-                            X86ISA::ZFBit | X86ISA::SFBit)) != 0)'''),
-        'PredcfofBits':   ('CCReg', 'uqw', '(X86ISA::CCREG_CFOF)', None,
-                61, None, None, '''(((ext & X86ISA::CFBit) == 0 ||
-                (ext & X86ISA::OFBit) == 0) &&
-                    ((ext & (X86ISA::CFBit | X86ISA::OFBit)) != 0))''',
-                '((ext & (X86ISA::CFBit | X86ISA::OFBit)) != 0)'),
-        'PreddfBit':   ('CCReg', 'uqw', '(X86ISA::CCREG_DF)', None,
-                62, None, None, '(false)', '((ext & X86ISA::DFBit) != 0)'),
-        'PredecfBit':   ('CCReg', 'uqw', '(X86ISA::CCREG_ECF)', None,
-                63, None, None, '(false)', '((ext & X86ISA::ECFBit) != 0)'),
-        'PredezfBit':   ('CCReg', 'uqw', '(X86ISA::CCREG_EZF)', None,
-                64, None, None, '(false)', '((ext & X86ISA::EZFBit) != 0)'),
+                '(ext & X86ISA::ccFlagMask) != X86ISA::ccFlagMask && '
+                '(ext & X86ISA::ccFlagMask) != 0',
+                '(ext & X86ISA::ccFlagMask) != 0'),
+        'PredcfofBits':   ('CCReg', 'uqw', 'X86ISA::CCREG_CFOF', None,
+                61, None, None,
+                '(ext & X86ISA::cfofMask) != X86ISA::cfofMask && '
+                '(ext & X86ISA::cfofMask) != 0',
+                '(ext & X86ISA::cfofMask) != 0'),
+        'PreddfBit':     ('CCReg', 'uqw', 'X86ISA::CCREG_DF', None,
+                62, None, None, 'false', '(ext & X86ISA::DFBit) != 0'),
+        'PredecfBit':    ('CCReg', 'uqw', 'X86ISA::CCREG_ECF', None,
+                63, None, None, 'false', '(ext & X86ISA::ECFBit) != 0'),
+        'PredezfBit':    ('CCReg', 'uqw', 'X86ISA::CCREG_EZF', None,
+                64, None, None, 'false', '(ext & X86ISA::EZFBit) != 0'),
 
         # These register should needs to be more protected so that later
         # instructions don't map their indexes with an old value.