derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

configs: Remove unneeded ddr3 memory component

Browse Source 
Change-Id: Id0228b4628c1be6dce3d7092731798bfa07de815
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49347
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Jason Lowe-Power
2021-08-16 17:45:14 -07:00
committed by Jason Lowe-Power
parent 343ef29173
commit 31c7d8cf46
3 changed files with 4 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

66
components_library/memory/ddr3_1600_8x8.py
View File

@@ -1,66 +0,0 @@
# Copyright (c) 2021 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import abstractmethod
from typing import Optional
from m5.objects import DDR3_1600_8x8 as DIMM
from m5.objects import MemCtrl
from m5.params import Port, AddrRange
from .abstract_memory_system import AbstractMemorySystem
from ..boards.abstract_board import AbstractBoard
from ..utils.override import *
from typing import Tuple, Sequence, List
class DDR3_1600_8x8(AbstractMemorySystem):
def __init__(self, size: Optional[str] = "512MiB") -> None:
super(DDR3_1600_8x8, self).__init__()
# The DDR3_1600_8x8 has a lot of variables with sensible defaults that
# make sense for a DDR3_1600_8x8 device. Only the size has been
# exposed.
self._dram = DIMM(range=size)
self.mem_cntrls = [MemCtrl(dram=self._dram)]
@overrides(AbstractMemorySystem)
def incorporate_memory(self, board: AbstractBoard) -> None:
pass
@overrides(AbstractMemorySystem)
def get_mem_ports(self) -> Tuple[Sequence[AddrRange], Port]:
return [(self._dram.range, ctrl.port) for ctrl in self.mem_cntrls]
@overrides(AbstractMemorySystem)
def get_memory_controllers(self) -> List[MemCtrl]:
return self.mem_cntrls
@overrides(AbstractMemorySystem)
def get_memory_ranges(self):
return [self._dram.range]

4
configs/example/components-library/boot_exit_disk_run.py
View File

@@ -55,7 +55,7 @@ from components_library.runtime import (
get_runtime_isa,
)
from components_library.boards.x86_board import X86Board
from components_library.memory.ddr3_1600_8x8 import DDR3_1600_8x8
from components_library.memory.single_channel import SingleChannelDDR3_1600
from components_library.processors.simple_processor import SimpleProcessor
from components_library.processors.cpu_types import CPUTypes
from components_library.isas import ISA
@@ -94,7 +94,7 @@ cache_hierarchy = MESITwoLevelCacheHierarchy(
# Setup the system memory.
# Warning: This must be kept at 3GB for now. X86Motherboard does not support
# anything else right now!
memory = DDR3_1600_8x8(size="3GB")
memory = SingleChannelDDR3_1600(size="3GB")
# Setup a single core Timing Processor.
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)

4
configs/example/components-library/parsec_disk_run.py
View File

@@ -57,7 +57,7 @@ from components_library.cachehierarchies.classic.\
private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from components_library.memory.ddr3_1600_8x8 import DDR3_1600_8x8
from components_library.memory.single_channel import SingleChannelDDR3_1600
from components_library.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
)
@@ -84,7 +84,7 @@ cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
# Setup the memory system.
# Warning!!! This must be kept at 3GB for now. X86Motherboard does not support
# anything else right now!
memory = DDR3_1600_8x8(size="3GB")
memory = SingleChannelDDR3_1600(size="3GB")
# The processor. In this case we use the special "SwitchableProcessor" which