cpu: Rename RegClassInfo to RegClass.

Change-Id: I0456462d5d306fc93a1fe160e45ff6b1b49f3c25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49103
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/generic/isa.hh

@@ -54,7 +54,7 @@ class ThreadContext;
 class BaseISA : public SimObject
 {
   public:
-    typedef std::vector<RegClassInfo> RegClasses;
+    typedef std::vector<RegClass> RegClasses;
 
   protected:
     using SimObject::SimObject;

src/cpu/o3/regfile.cc

@@ -41,7 +41,6 @@
 
 #include "cpu/o3/regfile.hh"
 
-#include "cpu/o3/free_list.hh"
 #include "cpu/o3/free_list.hh"
 
 namespace gem5

src/cpu/o3/rename_map.cc

@@ -60,15 +60,14 @@ SimpleRenameMap::SimpleRenameMap()
 
 
 void
-SimpleRenameMap::init(const RegClassInfo &reg_class_info,
-        SimpleFreeList *_freeList)
+SimpleRenameMap::init(const RegClass &reg_class, SimpleFreeList *_freeList)
 {
     assert(freeList == NULL);
     assert(map.empty());
 
-    map.resize(reg_class_info.size());
+    map.resize(reg_class.size());
     freeList = _freeList;
-    zeroReg = RegId(IntRegClass, reg_class_info.zeroReg());
+    zeroReg = RegId(IntRegClass, reg_class.zeroReg());
 }
 
 SimpleRenameMap::RenameInfo

src/cpu/o3/rename_map.hh

@@ -100,7 +100,7 @@ class SimpleRenameMap
      * it's awkward to initialize this object via the constructor.
      * Instead, this method is used for initialization.
      */
-    void init(const RegClassInfo &reg_class_info, SimpleFreeList *_freeList);
+    void init(const RegClass &reg_class, SimpleFreeList *_freeList);
 
     /**
      * Pair of a physical register and a physical register.  Used to

src/cpu/reg_class.hh

@@ -80,7 +80,7 @@ class DefaultRegClassOps : public RegClassOps
     std::string regName(const RegId &id) const override;
 };
 
-class RegClassInfo
+class RegClass
 {
   private:
     size_t _size;
@@ -90,11 +90,11 @@ class RegClassInfo
     RegClassOps *_ops = &defaultOps;
 
   public:
-    RegClassInfo(size_t new_size, RegIndex new_zero=-1) :
+    RegClass(size_t new_size, RegIndex new_zero=-1) :
         _size(new_size), _zeroReg(new_zero)
     {}
-    RegClassInfo(size_t new_size, RegClassOps &new_ops, RegIndex new_zero=-1) :
-        RegClassInfo(new_size, new_zero)
+    RegClass(size_t new_size, RegClassOps &new_ops, RegIndex new_zero=-1) :
+        RegClass(new_size, new_zero)
     {
         _ops = &new_ops;
     }