derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu: Simplify or eliminate set${type}Result methods for o3 and checker.

Browse Source 
These methods are all identical now. The O3 versions can all be
consolidated into a single method. For the checker CPU, they can
actually be eliminated entirely, and the result queue's "emplace()"
method can be used to add items using less text than just calling the
original helper method.

Change-Id: Ifaeb3beeea257c8bbf951ee1dd8d2d5fd8bb3964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49128
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-09 01:27:35 -07:00
parent 91f7486482
commit 7ffa9f8597
2 changed files with 14 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
src/cpu/checker/cpu.hh
View File

@@ -244,34 +244,13 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->readCCReg(reg.index());
}
template<typename T>
void
setScalarResult(T&& t)
{
result.push(InstResult(std::forward<T>(t)));
}
template<typename T>
void
setVecResult(T&& t)
{
result.push(InstResult(std::forward<T>(t)));
}
template<typename T>
void
setVecPredResult(T&& t)
{
result.push(InstResult(std::forward<T>(t)));
}
void
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(IntRegClass));
thread->setIntReg(reg.index(), val);
setScalarResult(val);
result.emplace(val);
}
void
@@ -280,7 +259,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(FloatRegClass));
thread->setFloatReg(reg.index(), val);
setScalarResult(val);
result.emplace(val);
}
void
@@ -289,7 +268,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(CCRegClass));
thread->setCCReg(reg.index(), val);
setScalarResult((uint64_t)val);
result.emplace(val);
}
void
@@ -299,7 +278,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecRegClass));
thread->setVecReg(reg, val);
setVecResult(val);
result.emplace(val);
}
void
@@ -308,7 +287,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));
thread->setVecElem(reg, val);
setScalarResult(val);
result.emplace(val);
}
void
@@ -318,7 +297,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecPredRegClass));
thread->setVecPredReg(reg, val);
setVecPredResult(val);
result.emplace(val);
}
bool readPredicate() const override { return thread->readPredicate(); }

37
src/cpu/o3/dyn_inst.hh
View File

@@ -771,33 +771,12 @@ class DynInst : public ExecContext, public RefCounted
/** Pushes a result onto the instResult queue. */
/** @{ */
/** Scalar result. */
template<typename T>
void
setScalarResult(T &&t)
setResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t)));
}
}
/** Full vector result. */
template<typename T>
void
setVecResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t)));
}
}
/** Predicate result. */
template<typename T>
void
setVecPredResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t)));
instResult.emplace(std::forward<T>(t));
}
}
/** @} */
@@ -1273,14 +1252,14 @@ class DynInst : public ExecContext, public RefCounted
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
this->cpu->setIntReg(this->regs.renamedDestIdx(idx), val);
setScalarResult(val);
setResult(val);
}
void
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
this->cpu->setFloatReg(this->regs.renamedDestIdx(idx), val);
setScalarResult(val);
setResult(val);
}
void
@@ -1288,7 +1267,7 @@ class DynInst : public ExecContext, public RefCounted
const TheISA::VecRegContainer& val) override
{
this->cpu->setVecReg(this->regs.renamedDestIdx(idx), val);
setVecResult(val);
setResult(val);
}
void
@@ -1296,7 +1275,7 @@ class DynInst : public ExecContext, public RefCounted
{
int reg_idx = idx;
this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
setScalarResult(val);
setResult(val);
}
void
@@ -1304,14 +1283,14 @@ class DynInst : public ExecContext, public RefCounted
const TheISA::VecPredRegContainer& val) override
{
this->cpu->setVecPredReg(this->regs.renamedDestIdx(idx), val);
setVecPredResult(val);
setResult(val);
}
void
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val);
setScalarResult(val);
setResult(val);
}
};