From 7ffa9f859713a52d24291350cce21cf963b10640 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 9 Aug 2021 01:27:35 -0700 Subject: [PATCH] cpu: Simplify or eliminate set${type}Result methods for o3 and checker. These methods are all identical now. The O3 versions can all be consolidated into a single method. For the checker CPU, they can actually be eliminated entirely, and the result queue's "emplace()" method can be used to add items using less text than just calling the original helper method. Change-Id: Ifaeb3beeea257c8bbf951ee1dd8d2d5fd8bb3964 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49128 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/cpu/checker/cpu.hh | 33 ++++++--------------------------- src/cpu/o3/dyn_inst.hh | 37 ++++++++----------------------------- 2 files changed, 14 insertions(+), 56 deletions(-) diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index e32d12d560..a83fe08010 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -244,34 +244,13 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->readCCReg(reg.index()); } - template - void - setScalarResult(T&& t) - { - result.push(InstResult(std::forward(t))); - } - - template - void - setVecResult(T&& t) - { - result.push(InstResult(std::forward(t))); - } - - template - void - setVecPredResult(T&& t) - { - result.push(InstResult(std::forward(t))); - } - void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.is(IntRegClass)); thread->setIntReg(reg.index(), val); - setScalarResult(val); + result.emplace(val); } void @@ -280,7 +259,7 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& reg = si->destRegIdx(idx); assert(reg.is(FloatRegClass)); thread->setFloatReg(reg.index(), val); - setScalarResult(val); + result.emplace(val); } void @@ -289,7 +268,7 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& reg = si->destRegIdx(idx); assert(reg.is(CCRegClass)); thread->setCCReg(reg.index(), val); - setScalarResult((uint64_t)val); + result.emplace(val); } void @@ -299,7 +278,7 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& reg = si->destRegIdx(idx); assert(reg.is(VecRegClass)); thread->setVecReg(reg, val); - setVecResult(val); + result.emplace(val); } void @@ -308,7 +287,7 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& reg = si->destRegIdx(idx); assert(reg.is(VecElemClass)); thread->setVecElem(reg, val); - setScalarResult(val); + result.emplace(val); } void @@ -318,7 +297,7 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& reg = si->destRegIdx(idx); assert(reg.is(VecPredRegClass)); thread->setVecPredReg(reg, val); - setVecPredResult(val); + result.emplace(val); } bool readPredicate() const override { return thread->readPredicate(); } diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 24c34b05b1..f26ea22979 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -771,33 +771,12 @@ class DynInst : public ExecContext, public RefCounted /** Pushes a result onto the instResult queue. */ /** @{ */ - /** Scalar result. */ template void - setScalarResult(T &&t) + setResult(T &&t) { if (instFlags[RecordResult]) { - instResult.push(InstResult(std::forward(t))); - } - } - - /** Full vector result. */ - template - void - setVecResult(T &&t) - { - if (instFlags[RecordResult]) { - instResult.push(InstResult(std::forward(t))); - } - } - - /** Predicate result. */ - template - void - setVecPredResult(T &&t) - { - if (instFlags[RecordResult]) { - instResult.push(InstResult(std::forward(t))); + instResult.emplace(std::forward(t)); } } /** @} */ @@ -1273,14 +1252,14 @@ class DynInst : public ExecContext, public RefCounted setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { this->cpu->setIntReg(this->regs.renamedDestIdx(idx), val); - setScalarResult(val); + setResult(val); } void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override { this->cpu->setFloatReg(this->regs.renamedDestIdx(idx), val); - setScalarResult(val); + setResult(val); } void @@ -1288,7 +1267,7 @@ class DynInst : public ExecContext, public RefCounted const TheISA::VecRegContainer& val) override { this->cpu->setVecReg(this->regs.renamedDestIdx(idx), val); - setVecResult(val); + setResult(val); } void @@ -1296,7 +1275,7 @@ class DynInst : public ExecContext, public RefCounted { int reg_idx = idx; this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val); - setScalarResult(val); + setResult(val); } void @@ -1304,14 +1283,14 @@ class DynInst : public ExecContext, public RefCounted const TheISA::VecPredRegContainer& val) override { this->cpu->setVecPredReg(this->regs.renamedDestIdx(idx), val); - setVecPredResult(val); + setResult(val); } void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override { this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val); - setScalarResult(val); + setResult(val); } };