diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index e32d12d560..a83fe08010 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -244,34 +244,13 @@ class CheckerCPU : public BaseCPU, public ExecContext
         return thread->readCCReg(reg.index());
     }
 
-    template<typename T>
-    void
-    setScalarResult(T&& t)
-    {
-        result.push(InstResult(std::forward<T>(t)));
-    }
-
-    template<typename T>
-    void
-    setVecResult(T&& t)
-    {
-        result.push(InstResult(std::forward<T>(t)));
-    }
-
-    template<typename T>
-    void
-    setVecPredResult(T&& t)
-    {
-        result.push(InstResult(std::forward<T>(t)));
-    }
-
     void
     setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.is(IntRegClass));
         thread->setIntReg(reg.index(), val);
-        setScalarResult(val);
+        result.emplace(val);
     }
 
     void
@@ -280,7 +259,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.is(FloatRegClass));
         thread->setFloatReg(reg.index(), val);
-        setScalarResult(val);
+        result.emplace(val);
     }
 
     void
@@ -289,7 +268,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.is(CCRegClass));
         thread->setCCReg(reg.index(), val);
-        setScalarResult((uint64_t)val);
+        result.emplace(val);
     }
 
     void
@@ -299,7 +278,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.is(VecRegClass));
         thread->setVecReg(reg, val);
-        setVecResult(val);
+        result.emplace(val);
     }
 
     void
@@ -308,7 +287,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.is(VecElemClass));
         thread->setVecElem(reg, val);
-        setScalarResult(val);
+        result.emplace(val);
     }
 
     void
@@ -318,7 +297,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.is(VecPredRegClass));
         thread->setVecPredReg(reg, val);
-        setVecPredResult(val);
+        result.emplace(val);
     }
 
     bool readPredicate() const override { return thread->readPredicate(); }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 24c34b05b1..f26ea22979 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -771,33 +771,12 @@ class DynInst : public ExecContext, public RefCounted
 
     /** Pushes a result onto the instResult queue. */
     /** @{ */
-    /** Scalar result. */
     template<typename T>
     void
-    setScalarResult(T &&t)
+    setResult(T &&t)
     {
         if (instFlags[RecordResult]) {
-            instResult.push(InstResult(std::forward<T>(t)));
-        }
-    }
-
-    /** Full vector result. */
-    template<typename T>
-    void
-    setVecResult(T &&t)
-    {
-        if (instFlags[RecordResult]) {
-            instResult.push(InstResult(std::forward<T>(t)));
-        }
-    }
-
-    /** Predicate result. */
-    template<typename T>
-    void
-    setVecPredResult(T &&t)
-    {
-        if (instFlags[RecordResult]) {
-            instResult.push(InstResult(std::forward<T>(t)));
+            instResult.emplace(std::forward<T>(t));
         }
     }
     /** @} */
@@ -1273,14 +1252,14 @@ class DynInst : public ExecContext, public RefCounted
     setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setIntReg(this->regs.renamedDestIdx(idx), val);
-        setScalarResult(val);
+        setResult(val);
     }
 
     void
     setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setFloatReg(this->regs.renamedDestIdx(idx), val);
-        setScalarResult(val);
+        setResult(val);
     }
 
     void
@@ -1288,7 +1267,7 @@ class DynInst : public ExecContext, public RefCounted
                      const TheISA::VecRegContainer& val) override
     {
         this->cpu->setVecReg(this->regs.renamedDestIdx(idx), val);
-        setVecResult(val);
+        setResult(val);
     }
 
     void
@@ -1296,7 +1275,7 @@ class DynInst : public ExecContext, public RefCounted
     {
         int reg_idx = idx;
         this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
-        setScalarResult(val);
+        setResult(val);
     }
 
     void
@@ -1304,14 +1283,14 @@ class DynInst : public ExecContext, public RefCounted
                          const TheISA::VecPredRegContainer& val) override
     {
         this->cpu->setVecPredReg(this->regs.renamedDestIdx(idx), val);
-        setVecPredResult(val);
+        setResult(val);
     }
 
     void
     setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val);
-        setScalarResult(val);
+        setResult(val);
     }
 };