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arch-arm: Replace std::tie with C++17 structured binding

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Change-Id: I856b60e91a0c8089ccc3560bdf9024b42206e170
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49084
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-08-06 15:27:48 +01:00
parent 1a4b6fbfe9
commit 0a31476e1c
3 changed files with 19 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/arm/insts/static_inst.cc
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@@ -1129,8 +1129,7 @@ illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
return true;
bool spsr_mode_is_aarch32 = (spsr.width == 1);
bool known, target_el_is_aarch32;
std::tie(known, target_el_is_aarch32) = ELUsingAArch32K(tc, target_el);
auto [known, target_el_is_aarch32] = ELUsingAArch32K(tc, target_el);
assert(known || (target_el == EL0 && ELIs64(tc, EL1)));
if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))

35
src/arch/arm/isa/insts/misc.isa
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@@ -891,9 +891,8 @@ let {{
mrc14code = '''
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, op1)).index();
bool can_read, undefined;
std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
if (!can_read || undefined) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
@@ -917,9 +916,8 @@ let {{
mcr14code = '''
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, dest)).index();
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
if (undefined || !can_write) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
@@ -947,9 +945,8 @@ let {{
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
bool can_read, undefined;
std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of whether
// the register is accessable, in other modes we trap if only if the register
// IS accessable.
@@ -980,9 +977,8 @@ let {{
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of whether
// the register is accessable, in other modes we trap if only if the register
@@ -1014,9 +1010,8 @@ let {{
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
bool can_read, undefined;
std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of whether
// the register is accessable, in other modes we trap if only if the register
// IS accessable.
@@ -1047,9 +1042,8 @@ let {{
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of whether
// the register is accessable, in other modes we trap if only if the register
@@ -1125,9 +1119,8 @@ let {{
bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we

10
src/arch/arm/utility.cc
View File

@@ -287,8 +287,7 @@ ELIs64(ThreadContext *tc, ExceptionLevel el)
bool
ELIs32(ThreadContext *tc, ExceptionLevel el)
{
bool known, aarch32;
std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
auto [known, aarch32] = ELUsingAArch32K(tc, el);
panic_if(!known, "EL state is UNKNOWN");
return aarch32;
}
@@ -375,11 +374,10 @@ ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
return std::make_pair(known, aarch32);
}
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
bool
ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
{
bool known, aarch32;
std::tie(known, aarch32) = ELStateUsingAArch32K(tc, el, secure);
auto [known, aarch32] = ELStateUsingAArch32K(tc, el, secure);
panic_if(!known, "EL state is UNKNOWN");
return aarch32;
}