configs: Update component API for I/O

This change adds a check for coherent I/O ports from the board. This
change allows us to move some of the cache hierarchy specific code out
of the board and into the cache hierarchies.

Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49363
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

components_library/boards/abstract_board.py

@@ -144,6 +144,24 @@ class AbstractBoard(System):
         """
         raise NotImplementedError
 
+    @abstractmethod
+    def has_coherent_io(self) -> bool:
+        """Determine whether the board needs coherent I/O
+
+        :returns: True if the board needs coherent I/O, false otherwise
+        """
+        raise NotImplementedError
+
+    @abstractmethod
+    def get_mem_side_coherent_io_port(self):
+        """Get the memory-side coherent I/O port.
+        This abstract method must be implemented if has_coherent_io is true.
+
+        This returns a *port* (not a bus) that should be connected to a
+        CPU-side port for which coherent I/O (DMA) is issued.
+        """
+        raise NotImplementedError
+
     @abstractmethod
     def get_clock_domain(self) -> ClockDomain:
         """Get the clock domain.

components_library/boards/simple_board.py

@@ -125,6 +125,17 @@ class SimpleBoard(AbstractBoard):
             "Use `has_dma_ports()` to check this."
         )
 
+    @overrides(AbstractBoard)
+    def has_coherent_io(self) -> bool:
+        return False
+
+    @overrides(AbstractBoard)
+    def get_mem_side_coherent_io_port(self) -> Port:
+        raise NotImplementedError(
+            "SimpleBoard does not have any I/O ports. Use has_coherent_io to "
+            "check this."
+        )
+
     @overrides(AbstractBoard)
     def setup_memory_ranges(self) -> None:
         memory = self.get_memory()

components_library/boards/test_board.py

@@ -105,6 +105,17 @@ class TestBoard(AbstractBoard):
             "Use `has_dma_ports()` to check this."
         )
 
+    @overrides(AbstractBoard)
+    def has_coherent_io(self) -> bool:
+        return False
+
+    @overrides(AbstractBoard)
+    def get_mem_side_coherent_io_port(self):
+        raise NotImplementedError(
+            "SimpleBoard does not have any I/O ports. Use has_coherent_io to "
+            "check this."
+        )
+
     @overrides(AbstractBoard)
     def set_mem_mode(self, mem_mode: MemMode) -> None:
         self.mem_mode = mem_mode_to_string(mem_mode=mem_mode)

components_library/boards/x86_board.py

@@ -99,6 +99,9 @@ class X86Board(SimpleBoard):
 
         self.workload = X86FsLinux()
 
+        # North Bridge
+        self.iobus = IOXBar()
+
     def _setup_io_devices(self):
         """ Sets up the x86 IO devices.
 
@@ -112,9 +115,6 @@ class X86Board(SimpleBoard):
         interrupts_address_space_base = 0xA000000000000000
         APIC_range_size = 1 << 12
 
-        # North Bridge
-        self.iobus = IOXBar()
-
         # Setup memory system specific settings.
         if self.get_cache_hierarchy().is_ruby():
             self.pc.attachIO(self.get_io_bus(), [self.pc.south_bridge.ide.dma])
@@ -154,22 +154,6 @@ class X86Board(SimpleBoard):
             ]
             self.pc.attachIO(self.get_io_bus())
 
-            self.iocache = Cache(
-                assoc=8,
-                tag_latency=50,
-                data_latency=50,
-                response_latency=50,
-                mshrs=20,
-                size="1kB",
-                tgts_per_mshr=12,
-                addr_ranges=self.mem_ranges,
-            )
-
-            self.iocache.cpu_side = self.get_io_bus().mem_side_ports
-            self.iocache.mem_side = (
-                self.get_cache_hierarchy().get_cpu_side_port()
-            )
-
         # Add in a Bios information structure.
         self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
 
@@ -360,6 +344,14 @@ class X86Board(SimpleBoard):
     def get_dma_ports(self) -> Sequence[Port]:
         return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports]
 
+    @overrides(AbstractBoard)
+    def has_coherent_io(self) -> bool:
+        return True
+
+    @overrides(AbstractBoard)
+    def get_mem_side_coherent_io_port(self) -> Port:
+        return self.iobus.mem_side_ports
+
     @overrides(AbstractBoard)
     def setup_memory_ranges(self):
         memory = self.get_memory()

components_library/cachehierarchies/classic/no_cache.py

@@ -33,7 +33,7 @@ from ...boards.abstract_board import AbstractBoard
 from ...isas import ISA
 from ...runtime import get_runtime_isa
 
-from m5.objects import BaseXBar, SystemXBar, BadAddr, Port
+from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port
 
 from typing import Optional
 
@@ -101,6 +101,9 @@ class NoCache(AbstractClassicCacheHierarchy):
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
 
+        if board.has_coherent_io():
+            self._setup_coherent_io_bridge(board)
+
         for core in board.get_processor().get_cores():
 
             core.connect_icache(self.membus.cpu_side_ports)
@@ -121,3 +124,9 @@ class NoCache(AbstractClassicCacheHierarchy):
 
         for cntr in board.get_memory().get_memory_controllers():
             cntr.port = self.membus.mem_side_ports
+
+    def _setup_coherent_io_bridge(self, board: AbstractBoard) -> None:
+        """Create a bridge from I/O back to membus"""
+        self.iobridge = Bridge(delay="10ns", ranges=board.mem_ranges)
+        self.iobridge.mem_side_port = self.membus.cpu_side_ports
+        self.iobridge.cpu_side_port = board.get_mem_side_coherent_io_port()

components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -159,3 +159,17 @@ class PrivateL1PrivateL2CacheHierarchy(
                 cpu.connect_interrupt(int_req_port, int_resp_port)
             else:
                 cpu.connect_interrupt()
+    def _setup_io_cache(self, board: AbstractBoard) -> None:
+        """Create a cache for coherent I/O connections"""
+        self.iocache = Cache(
+            assoc=8,
+            tag_latency=50,
+            data_latency=50,
+            response_latency=50,
+            mshrs=20,
+            size="1kB",
+            tgts_per_mshr=12,
+            addr_ranges=board.mem_ranges,
+        )
+        self.iocache.mem_side = self.membus.cpu_side_ports
+        self.iocache.cpu_side = board.get_mem_side_coherent_io_port()