Commit Graph

60 Commits

Author SHA1 Message Date
Giacomo Travaglini
e73655d038 misc: Use python f-strings for string formatting
This patch has been generated by applying flynt to the
gem5 repo (ext has been excluded)

JIRA: https://gem5.atlassian.net/browse/GEM5-831

Change-Id: I0935db6223d5426b99515959bde78e374cbadb04
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-16 09:05:29 +00:00
Sascha Bischoff
fe8eda9c4e arch, arch-arm, cpu: Add matrix reg support to the ISA Parser
The ISA parser now emits the code required to access matrix
registers. In the case where a register is both a source and a
destination, the ISA parser generates appropriate code to make sure
that the contents of the source is copied to the destination. This is
required for the O3 CPU which treats these as two different physical
registers, and hence data is lost if not explicitly preserved.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289

Change-Id: I8796bd1ea55b5edf5fb8ab92ef1a6060ccc58fa1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64338
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-01-17 10:09:56 +00:00
Hoa Nguyen
eac06ad681 python: Fix multiline quotes in a single line
An example case,
```python
mem_side_port = RequestPort(
    "This port sends requests and " "receives responses"
)
```

This is the residue of running the python formatter.
This is done by finding all tokens matching the regex `"\s"(?![.;"])`
and manually replacing them by empty strings.

Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66111
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-11-29 23:44:38 +00:00
Bobby R. Bruce
2bc5a8b71a misc: Run pre-commit run on all files in repo
The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-08-24 21:47:07 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-03 09:10:41 +00:00
Gabe Black
e425bcabd2 arch,cpu,sim: Store registers in InstRecord with InstResult.
The InstResult knows how to print registers without having to know about
their actual types.

Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-08-02 12:44:25 +00:00
Gabe Black
654451c2be arch,cpu: Keep a RegClass pointer in RegId instead of a RegClassType.
This makes it easy to get access to the RegClass that goes with a
register without having to look it up in a separate structure.

Change-Id: I4cfff2069d63f3c1c3fb0fea5dee3baf357bd478
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49786
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 13:54:32 +00:00
Gabe Black
a52f92dccb arch: Remove plumbing for an op_idx value in ISA operands.
Now that op_idx is trivial to calculate (just src_reg_idx or
dest_reg_idx), there's no need to have the indirection and extra
mechanism to funnel a precalculated value around.

Change-Id: I37daeb646b85e050c4b832af28d054ecc3c338b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49750
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-06-08 07:07:35 +00:00
Gabe Black
a1b439f91c arch: Remove plumbing for operand predication.
The operand predication mechanism has been replaced by mapping
predicate-false register reads/writes to InvalidRegClass.

Change-Id: I57e7aadb7a0d682c225f6a5fe673cba8ddf1c4f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49749
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-08 07:07:15 +00:00
Gabe Black
851c86af6d arch: Improve the regular expression that finds operands.
This regular expression currently has a negative lookbehind assertion
that the operand name isn't preceded by any numbers or letters. Expand
that to also include the : character, since no operand should have a
namespace specifier in front of it.

Change-Id: I0bd84b69b9dad278191831d82db762ae75ce4bf1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49751
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-07 19:00:12 +00:00
Gabe Black
7cc384c308 arch: Eliminate the now unused read_code and write_code args.
Also eliminate the buildReadCode and buildWriteCode methods.

Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-12 23:50:52 +00:00
Gabe Black
886154b958 arch: Split up src/dest register ID creation.
This will allow us to selectively change the RegID of an operand to, for
instance, convert it to InvalidRegClass just as a source so it never
actually gets read.

Change-Id: I9f8117cbb2088f8150080f815cdb5cb84bd7218e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49747
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 23:52:35 +00:00
Gabe Black
225b515f48 arch: Add a mechanism to override methods of the Operand classes.
The classes defined by the ISA description are actually just descriptors
which are used to make more specialized Operand classes, and then those
classes are instantiated to represent actual operands in a given
instruction. There they encode the actual index of the register, any
extensions used, etc.

To make defining operand types in the ISA more flexible and to take less
explicit machinery, this change defines a mechanism to allow overriding
individual methods of the operand class. This should for instance make
the read_code and write_code members of those classes unnecessary.

Change-Id: I1a1f787970ba56bd2884a80df4618a77eb454605
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49740
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-03-25 18:50:02 +00:00
Gabe Black
218d6b239d arch: Add some indirection for Operand RegId generation.
That introduces a place to hook in to override what actual register
index is passed to the rest of gem5.

Change-Id: I77d778849410ee5d32bab669bba411e80603a002
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49739
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-17 20:50:19 +00:00
Gabe Black
93b7c8c321 arch: Consolidate "op_idx" generating code.
Change-Id: I6c715d8931b7943c798674c19a1e7307d0e182be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49738
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-17 20:49:47 +00:00
Gabe Black
1dad34a403 arch: Eliminate the "func" parameter to build(Read|Write)Code.
The correct accessor is well known by the code providing a template for
buildReadCode/buildWriteCode, and so can be simply inserted without the
indirection. This makes the code a little easier to read, and those
templating functions simpler and easier to understand.

Change-Id: I403c6e4c291708f8b58cce08bfa32ee2a930c296
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49737
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-16 08:58:38 +00:00
Gabe Black
543035e90d arch: Disable unused read/write code overrides in the ISA parser.
Some operand types had read/write code overrides, I think largely by
pattern matching other operand types, and not because that code was
actually expected to be used or to work. Instead, we should just assert
that that code isn't used and remove the implementation. This method of
affecting reading and writing code is going away anyway, and if this is
needed in the future it can be replaced in the new system.

Change-Id: Idae886153aa343570109069cbe54e2c1699a34e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49736
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-16 08:58:22 +00:00
Gabe Black
971ee4aded arch: Update the default "func" value in the ISA parser.
Now that there is a unified (get|set)RegOperand accessor for all
register based operands, that can be used as a reasonable default in the
ISA parser code.

Change-Id: Icef62aa6c16fb8b929ee0fa0d60b23553e0bf515
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49735
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-11 08:39:07 +00:00
Gabe Black
2a525325df arch: Delete now unused operand types.
These have been subsumed into the RegOperand type, and are fronted by
the *RegOperandDesc OperandDesc classes.

Change-Id: If57b683b06f3002004863c2d74f2a645882fbd41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49734
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-11 08:38:54 +00:00
Gabe Black
ae8e8e2d3c arch: Pass through the actual base class in OperandDesc.
Rather than pass through part of the base class name, we can pass
through the actual base class and remove some unnecessary historical
complexity.

Change-Id: I77edc07b54b264254700fb9c26b8c9b626709779
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57449
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-11 08:38:35 +00:00
Gabe Black
1856bec959 arch: Remove support for lists in def operands.
Change-Id: I4e9f4e0ff215a60443d408c0b8d53f1ff450a784
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49733
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-03-11 08:38:21 +00:00
Gabe Black
988f7573f6 arch: Create a new operand desc type which takes a class as a parameter.
This will be the basis for an operand type which can override its
register class if needed.

Change-Id: I415b70d6d655efc9f6b32102a8482e2cca2fa613
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49727
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-10 21:52:18 +00:00
Gabe Black
a84c987eef arch: Add desc subclasses for the various operand types.
These correspond to the existing operand types like IntRegOperand, or as
it's called in the operand table 'IntReg'. These subclasses
automatically set the base type name ('IntReg' for IntRegOperands),
which results in some mildly more familiar looking syntax, but is still
not that different from what we have today.

Change-Id: Id77c4e5a5e1b93c10aa9ad85e1a615f6c145832a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49725
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-09 02:54:23 +00:00
Gabe Black
4a3a1b92b4 arch: Put operand properties into an object constructed with the list.
Currently, to specify operands for an ISA, you define a dict from
operand names to properties in the ISA description. The properties are
in a list which has well defined positions for each entry, some of which
are optional.

These lists are fairly opaque since they don't have any way to, for
instance, accept keyword arguments. Also, these specifications simply
list as their first element what type of operand they're going to be.

This change is the first step in turning these specifications into
something more robust like a small temporary object. This object can be
constructed from a class which has a proper constructor that can take
keyword arguments, can have defaults, and can be subclassed.

Change-Id: I5f24d0b41f3e30b24a1ddd10157965d700d6c906
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49724
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-08 21:47:33 +00:00
Gabe Black
38e06033fa arch: Consolidate most of the RegVal based operands into a base class.
All the RegVal based operands except MiscRegs are consolidated, and
those classes are almost all consolidated, except for the RegClassType
they use.

Change-Id: I8494c7066e9d19411fd97d7cc5ac2078f799c2ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49723
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-08 21:47:11 +00:00
Gabe Black
c0d380b4d7 arch: Simplify the VecElemOperand class.
Oddly, makeDecl would conditionally declare the operand, but only
because makeRead would also declare it. Instead, make makeRead work like
normal, and get rid of the custom makeDecl.

Change-Id: I26c6f01f971778ad5075f8d3f49d9816f371f5b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49722
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-02 23:41:31 +00:00
Gabe Black
81d2f9f10a arch: Consolidate all the make_constructor methods in the ISA parser.
These methods were all identical, except that IntRegOperand and
CCRegOperand classes had logic to handle operand predication. Since the
other operand types won't have predicates set, we can use the superset
version, and the other types will reduce to what they used to in
practice.

Change-Id: I51eeedcacb7cfc6e2c136742701ee9bf80ec4e15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49721
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-02 21:26:48 +00:00
Gabe Black
f1b421baf5 arch: Get rid of the is${Type}Reg methods of the Operand class.
These are not used, and would prevent creating a truly generic register
operand class.

Change-Id: Ibffadc7a682b878aee8e632a0f85c06e91a60614
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49720
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-01 22:01:45 +00:00
Gabe Black
d8e04d25a6 arch: Introduce an intermediate RegOperand class in operand_types.py.
There are a number of operand types which are registers. Define a
RegOperand type which they can all inherit from to get register generic
functionality. This will also become a way to add generic register types
with malleable properties at the ISA level.

Change-Id: I01a1d5d133d8f64106d005a744631f64e6808e57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-01 22:01:25 +00:00
Gabe Black
a5ab19d3ef arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).
Change-Id: I32be58cce831c8c7d5b9e3d3f49f428a06c722a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49713
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-01 01:36:07 +00:00
Gabe Black
967bada8db arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array.
The array is indexed using the register class.

Change-Id: I6cfd9735afa03e386e01e9e255fd6e55b7ba7272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49712
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-01 01:36:07 +00:00
Gabe Black
2d012222c2 arch: Get rid of the unused numAccessNeeded variable.
This was defined in a few operand classes makeConstructor methods, but
never used for anything.

Change-Id: If2f62ff0a29a26ae7067728651440f864999fc67
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49718
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-02-28 22:05:25 +00:00
Gabe Black
3ba623d673 arch: Stop using TheISA:: in the ISA parser.
The ISA description provides us with a namespace to use, so we can use
that instead of TheISA.

Change-Id: If1a13c39a09ab22c7cab1138220fa0162fc2effa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49707
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-02-24 09:10:26 +00:00
Gabe Black
6d27a3bb50 cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.
This simplifies and generalizes the ExecContext interface significantly.
This does *not* change the "Writeable" accessors for the vec and pred
registers, and it also ignores MiscRegs which have some different
semantics.

Change-Id: I8cb80da890fc8915f03be04e136662a257d06946
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49114
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-19 20:23:51 +00:00
Gabe Black
528d184ac7 misc: Linearlize VecElem indexing.
These registers used to be accessed with a two dimensional index, with
one dimension specifying the register, and the second index specifying
the element within that register. This change linearizes that index down
to one dimension, where the elements of each register are laid out one
after the other in sequence.

Change-Id: I41110f57b505679a327108369db61c826d24922e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49148
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-21 23:05:47 +00:00
Gabe Black
39584edc72 arch,cpu: Convert ExecContext::pcState to use PCStateBase.
Some places need persistent temporaries for the return values of
ThreadContext::pcState(), which is currently by value.

Change-Id: Icd4924f1d16ebe1c99c54ed47616733422340cfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52057
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-29 22:00:54 +00:00
Gabe Black
ba5f68db3d misc: Use python 3's argumentless super().
When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 13:04:44 +00:00
Gabe Black
ebef94707e arch: Use the actual ISA namespace for PCState in the parser.
Change-Id: Id716c809fb6a33b170727c0e08fc15019f2468c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52030
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-26 19:15:48 +00:00
Gabe Black
7d92144e1b arch,sparc: Get rid of the unused checkVecEnableFault mechanism.
The method was only defined in SPARC, and SPARC does not use the vector
register file.

Change-Id: I4112eadaecb1f1c6c6db12975bec0cd1fa245d6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48715
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-10-13 07:59:52 +00:00
Gabe Black
cc75a47b84 python,scons: Move grammar.py and code_formatter.py into build_tools.
These are only used in a build, and so don't need to be built into gem5.
grammar.py is used by slicc and the fast model project file parser, and
code_formatter.py is only used by SConscripts.

Change-Id: Id43e62459d69f07fdb2ed125548a83e38bbb7590
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49396
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-09-24 21:23:27 +00:00
Gabe Black
00876fff20 misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
The [[maybe_unused]] attribute is now standard, so we can use that
directly without hiding it behind a macro.

Change-Id: If24ffd7e50bdb503cb3e6ea61f226ea794e84b8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48511
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-29 10:17:51 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Gabe Black
c480558532 misc: Replace M5_UNREACHABLE with GEM5_UNREACHABLE.
Change-Id: Id4cbdb8ae58c1077411e01579ac3a2d72b3b7465
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45238
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
fb3befcc6d misc: Replace M5_VAR_USED with GEM5_VAR_USED.
Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
cba6374f57 arch: Set %(op_idx)s properly when predicated operands are present.
This should be either the fixed index if there are no predicated
operands (ie operands which may not be used), and an auto incrementing
index otherwise. This is still not bulletproof since the auto
incrementing index is just code which ++-es the index, and so the index
will be different and incremented each time that value is substituted
in.

Also, the mixture of predicated operands and the vector operands is
broken and will not generate compilable code, but I'm not going to try
to fix that here.

Change-Id: I1ceae519649762e54eaa019610e51bb8c21d28d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42970
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-11 04:52:32 +00:00
Gabe Black
e837fdc65c base,misc: Collapse and eliminate the ULL and LL macros.
These just move the ULL or LL suffix to the value in question, and cast
to a uint64_t or an int64_t. We should be able to drop the cast
entirely, and turn the macro into a suffix for the literals in question.

Change-Id: Ia3db35d56137b57def6cf8e27e8457357eb83f62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 04:14:17 +00:00
Gabe Black
0343b506c7 arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.
This field wasn't used for anything.

Change-Id: I81f38743a7b4f87c56adb8ffeda6f9a096d09842
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41895
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-03 01:06:15 +00:00
Gabe Black
d37a0dab73 arch: Get rid of global maximums for numbers of source/dest/misc regs.
Change-Id: I6881572daedf0f0e9ff6aee4f174671d02ef743d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-02-15 19:21:21 +00:00
Gabe Black
d7083448e7 arch: Fix the code that computes MaxMiscDestReg.
This code was simplified a little while ago, and the wrong variable name
was used in that computation accidentally. Fortunately the "wrong" value
would be too large, and so nothing bad would happen except a pair of
arrays would be overly large in the O3 instruction class.

Change-Id: I9694f1a8c79a62a172ef63bdd2f98fa0ace06acd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38383
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-19 00:12:52 +00:00
Gabe Black
544a172800 arch: Wrap InstObjParams with a class and not a function.
When parsing an ISA description, the InstObjParams class needs to have a
reference to the current parser. It does that by exposing a wrapper to
the description rather than the actual InstObjParams class. That wrapper
injects an additional argument into the InstObjParams constructor.

Originally, the wrapper which injectect the additional argument was a
function which masqueraded as a class. That made it impossible to
subclass InstObjParams.

Instead, this change replaces that function wrapper with a class
wrapper, and injects the extra argument in the __init__ method. This
preserves the fact that the InstObjParams name refers to a class, and
allows any sort of interaction that's normally allowed with a class like
subclassing.

Change-Id: I550ea2e60eadac3c7c0b9afa7d71f4607b49a5d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39275
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-19 00:12:19 +00:00