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arch: Set %(op_idx)s properly when predicated operands are present.

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This should be either the fixed index if there are no predicated
operands (ie operands which may not be used), and an auto incrementing
index otherwise. This is still not bulletproof since the auto
incrementing index is just code which ++-es the index, and so the index
will be different and incremented each time that value is substituted
in.

Also, the mixture of predicated operands and the vector operands is
broken and will not generate compilable code, but I'm not going to try
to fix that here.

Change-Id: I1ceae519649762e54eaa019610e51bb8c21d28d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42970
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-03-13 23:30:37 -08:00
parent 0d390f1593
commit cba6374f57
1 changed files with 22 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
src/arch/isa_parser/operand_types.py
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@@ -47,24 +47,26 @@ class Operand(object):
src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));'
dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s));'
def buildReadCode(self, func = None):
def buildReadCode(self, predRead, func=None):
subst_dict = {"name": self.base_name,
"func": func,
"reg_idx": self.reg_spec,
"ctype": self.ctype}
if hasattr(self, 'src_reg_idx'):
subst_dict['op_idx'] = self.src_reg_idx
subst_dict['op_idx'] = \
'_sourceIndex++' if predRead else str(self.src_reg_idx)
code = self.read_code % subst_dict
return '%s = %s;\n' % (self.base_name, code)
def buildWriteCode(self, func = None):
def buildWriteCode(self, predWrite, func=None):
subst_dict = {"name": self.base_name,
"func": func,
"reg_idx": self.reg_spec,
"ctype": self.ctype,
"final_val": self.base_name}
if hasattr(self, 'dest_reg_idx'):
subst_dict['op_idx'] = self.dest_reg_idx
subst_dict['op_idx'] = \
'_destIndex++' if predWrite else str(self.dest_reg_idx)
code = self.write_code % subst_dict
return '''
{
@@ -200,7 +202,7 @@ class IntRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read integer register as FP')
if self.read_code != None:
return self.buildReadCode('readIntRegOperand')
return self.buildReadCode(predRead, 'readIntRegOperand')
int_reg_val = ''
if predRead:
@@ -217,7 +219,7 @@ class IntRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to write integer register as FP')
if self.write_code != None:
return self.buildWriteCode('setIntRegOperand')
return self.buildWriteCode(predWrite, 'setIntRegOperand')
if predWrite:
wp = 'true'
@@ -264,7 +266,7 @@ class FloatRegOperand(Operand):
def makeRead(self, predRead):
if self.read_code != None:
return self.buildReadCode('readFloatRegOperandBits')
return self.buildReadCode(predRead, 'readFloatRegOperandBits')
if predRead:
rindex = '_sourceIndex++'
@@ -280,7 +282,7 @@ class FloatRegOperand(Operand):
def makeWrite(self, predWrite):
if self.write_code != None:
return self.buildWriteCode('setFloatRegOperandBits')
return self.buildWriteCode(predWrite, 'setFloatRegOperandBits')
if predWrite:
wp = '_destIndex++'
@@ -369,7 +371,7 @@ class VecRegOperand(Operand):
def makeReadW(self, predWrite):
func = 'getWritableVecRegOperand'
if self.read_code != None:
return self.buildReadCode(func)
return self.buildReadCode(predWrite, func)
if predWrite:
rindex = '_destIndex++'
@@ -407,7 +409,7 @@ class VecRegOperand(Operand):
def makeRead(self, predRead):
func = 'readVecRegOperand'
if self.read_code != None:
return self.buildReadCode(func)
return self.buildReadCode(predRead, func)
if predRead:
rindex = '_sourceIndex++'
@@ -437,7 +439,7 @@ class VecRegOperand(Operand):
def makeWrite(self, predWrite):
func = 'setVecRegOperand'
if self.write_code != None:
return self.buildWriteCode(func)
return self.buildWriteCode(predWrite, func)
wb = '''
if (traceData) {
@@ -537,7 +539,7 @@ class VecPredRegOperand(Operand):
def makeRead(self, predRead):
func = 'readVecPredRegOperand'
if self.read_code != None:
return self.buildReadCode(func)
return self.buildReadCode(predRead, func)
if predRead:
rindex = '_sourceIndex++'
@@ -555,7 +557,7 @@ class VecPredRegOperand(Operand):
def makeReadW(self, predWrite):
func = 'getWritableVecPredRegOperand'
if self.read_code != None:
return self.buildReadCode(func)
return self.buildReadCode(predWrite, func)
if predWrite:
rindex = '_destIndex++'
@@ -573,7 +575,7 @@ class VecPredRegOperand(Operand):
def makeWrite(self, predWrite):
func = 'setVecPredRegOperand'
if self.write_code != None:
return self.buildWriteCode(func)
return self.buildWriteCode(predWrite, func)
wb = '''
if (traceData) {
@@ -619,7 +621,7 @@ class CCRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read condition-code register as FP')
if self.read_code != None:
return self.buildReadCode('readCCRegOperand')
return self.buildReadCode(predRead, 'readCCRegOperand')
int_reg_val = ''
if predRead:
@@ -636,7 +638,7 @@ class CCRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to write condition-code register as FP')
if self.write_code != None:
return self.buildWriteCode('setCCRegOperand')
return self.buildWriteCode(predWrite, 'setCCRegOperand')
if predWrite:
wp = 'true'
@@ -685,7 +687,7 @@ class ControlRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read control register as FP')
if self.read_code != None:
return self.buildReadCode('readMiscRegOperand')
return self.buildReadCode(predRead, 'readMiscRegOperand')
if predRead:
rindex = '_sourceIndex++'
@@ -699,7 +701,7 @@ class ControlRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to write control register as FP')
if self.write_code != None:
return self.buildWriteCode('setMiscRegOperand')
return self.buildWriteCode(predWrite, 'setMiscRegOperand')
if predWrite:
windex = '_destIndex++'
@@ -726,12 +728,12 @@ class MemOperand(Operand):
def makeRead(self, predRead):
if self.read_code != None:
return self.buildReadCode()
return self.buildReadCode(predRead)
return ''
def makeWrite(self, predWrite):
if self.write_code != None:
return self.buildWriteCode()
return self.buildWriteCode(predWrite)
return ''
class PCStateOperand(Operand):