arch: Use the actual ISA namespace for PCState in the parser.

Change-Id: Id716c809fb6a33b170727c0e08fc15019f2468c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52030
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-07 13:04:15 -07:00
parent 258a1ad47d
commit ebef94707e
2 changed files with 10 additions and 6 deletions

View File

@@ -121,9 +121,11 @@ class Template(object):
&std::remove_pointer_t<decltype(this)>::destRegIdxArr));
'''
pcstate_decl = f'{self.parser.namespace}::PCState ' \
'__parserAutoPCState;\n'
myDict['op_decl'] = operands.concatAttrStrings('op_decl')
if operands.readPC or operands.setPC:
myDict['op_decl'] += 'TheISA::PCState __parserAutoPCState;\n'
myDict['op_decl'] += pcstate_decl
# In case there are predicated register reads and write, declare
# the variables for register indicies. It is being assumed that
@@ -144,11 +146,9 @@ class Template(object):
myDict['op_dest_decl'] = \
operands.concatSomeAttrStrings(is_dest, 'op_dest_decl')
if operands.readPC:
myDict['op_src_decl'] += \
'TheISA::PCState __parserAutoPCState;\n'
myDict['op_src_decl'] += pcstate_decl
if operands.setPC:
myDict['op_dest_decl'] += \
'TheISA::PCState __parserAutoPCState;\n'
myDict['op_dest_decl'] += pcstate_decl
myDict['op_rd'] = operands.concatAttrStrings('op_rd')
if operands.readPC:

View File

@@ -737,6 +737,10 @@ class MemOperand(Operand):
return ''
class PCStateOperand(Operand):
def __init__(self, parser, *args, **kwargs):
super(PCStateOperand, self).__init__(parser, *args, **kwargs)
self.parser = parser
def makeConstructor(self, predRead, predWrite):
return ''
@@ -759,7 +763,7 @@ class PCStateOperand(Operand):
return 'xc->pcState(%s);\n' % self.base_name
def makeDecl(self):
ctype = 'TheISA::PCState'
ctype = f'{self.parser.namespace}::PCState'
if self.isPCPart():
ctype = self.ctype
# Note that initializations in the declarations are solely