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python: Fix multiline quotes in a single line

Browse Source 
An example case,
```python
mem_side_port = RequestPort(
    "This port sends requests and " "receives responses"
)
```

This is the residue of running the python formatter.
This is done by finding all tokens matching the regex `"\s"(?![.;"])`
and manually replacing them by empty strings.

Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66111
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Hoa Nguyen
2022-11-28 03:26:32 +00:00
parent f99947059d
commit eac06ad681
66 changed files with 256 additions and 268 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
build_tools/cxx_config_cc.py
View File

@@ -255,9 +255,7 @@ for param in sim_object._params.values():
code('} else if (name == "${{param.name}}") {')
code.indent()
code("${{param.name}}.clear();")
code(
"for (auto i = values.begin(); " "ret && i != values.end(); i ++)"
)
code("for (auto i = values.begin(); ret && i != values.end(); i ++)")
code("{")
code.indent()
code("${{param.ptype.cxx_type}} elem;")

2
build_tools/enum_cc.py
View File

@@ -87,7 +87,7 @@ namespace gem5
)
if enum.wrapper_is_struct:
code("const char *${wrapper_name}::${name}Strings" "[Num_${name}] =")
code("const char *${wrapper_name}::${name}Strings[Num_${name}] =")
else:
if enum.is_class:
code(

4
configs/common/Options.py
View File

@@ -217,7 +217,7 @@ def addNoISAOptions(parser):
"--maxtime",
type=float,
default=None,
help="Run to the specified absolute simulated time in " "seconds",
help="Run to the specified absolute simulated time in seconds",
)
parser.add_argument(
"-P",
@@ -691,7 +691,7 @@ def addSEOptions(parser):
"-o",
"--options",
default="",
help="""The options to pass to the binary, use " "
help="""The options to pass to the binary, use
around the entire string""",
)
parser.add_argument(

18
configs/example/apu_se.py
View File

@@ -85,7 +85,7 @@ parser.add_argument(
"--cu-per-sqc",
type=int,
default=4,
help="number of CUs" "sharing an SQC (icache, and thus icache TLB)",
help="number of CUssharing an SQC (icache, and thus icache TLB)",
)
parser.add_argument(
"--cu-per-scalar-cache",
@@ -94,7 +94,7 @@ parser.add_argument(
help="Number of CUs sharing a scalar cache",
)
parser.add_argument(
"--simds-per-cu", type=int, default=4, help="SIMD units" "per CU"
"--simds-per-cu", type=int, default=4, help="SIMD unitsper CU"
)
parser.add_argument(
"--cu-per-sa",
@@ -140,13 +140,13 @@ parser.add_argument(
"--glbmem-wr-bus-width",
type=int,
default=32,
help="VGPR to Coalescer (Global Memory) data bus width " "in bytes",
help="VGPR to Coalescer (Global Memory) data bus width in bytes",
)
parser.add_argument(
"--glbmem-rd-bus-width",
type=int,
default=32,
help="Coalescer to VGPR (Global Memory) data bus width in " "bytes",
help="Coalescer to VGPR (Global Memory) data bus width in bytes",
)
# Currently we only support 1 local memory pipe
parser.add_argument(
@@ -166,7 +166,7 @@ parser.add_argument(
"--wfs-per-simd",
type=int,
default=10,
help="Number of " "WF slots per SIMD",
help="Number of WF slots per SIMD",
)
parser.add_argument(
@@ -290,13 +290,11 @@ parser.add_argument(
help="Latency for scalar responses from ruby to the cu.",
)
parser.add_argument(
"--TLB-prefetch", type=int, help="prefetch depth for" "TLBs"
)
parser.add_argument("--TLB-prefetch", type=int, help="prefetch depth for TLBs")
parser.add_argument(
"--pf-type",
type=str,
help="type of prefetch: " "PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
)
parser.add_argument("--pf-stride", type=int, help="set prefetch stride")
parser.add_argument(
@@ -369,7 +367,7 @@ parser.add_argument(
type=str,
default="gfx801",
choices=GfxVersion.vals,
help="Gfx version for gpu" "Note: gfx902 is not fully supported by ROCm",
help="Gfx version for gpuNote: gfx902 is not fully supported by ROCm",
)
Ruby.define_options(parser)

8
configs/example/arm/baremetal.py
View File

@@ -242,25 +242,25 @@ def main():
"--semi-stdin",
type=str,
default="stdin",
help="Standard input for semihosting " "(default: gem5's stdin)",
help="Standard input for semihosting (default: gem5's stdin)",
)
parser.add_argument(
"--semi-stdout",
type=str,
default="stdout",
help="Standard output for semihosting " "(default: gem5's stdout)",
help="Standard output for semihosting (default: gem5's stdout)",
)
parser.add_argument(
"--semi-stderr",
type=str,
default="stderr",
help="Standard error for semihosting " "(default: gem5's stderr)",
help="Standard error for semihosting (default: gem5's stderr)",
)
parser.add_argument(
"--semi-path",
type=str,
default="",
help=("Search path for files to be loaded through " "Arm Semihosting"),
help=("Search path for files to be loaded through Arm Semihosting"),
)
parser.add_argument(
"args",

6
configs/example/arm/dist_bigLITTLE.py
View File

@@ -51,7 +51,7 @@ import sw
def addOptions(parser):
# Options for distributed simulation (i.e. dist-gem5)
parser.add_argument(
"--dist", action="store_true", help="Distributed gem5" " simulation."
"--dist", action="store_true", help="Distributed gem5 simulation."
)
parser.add_argument(
"--is-switch",
@@ -71,14 +71,14 @@ def addOptions(parser):
default=0,
action="store",
type=int,
help="Number of gem5 processes within the dist gem5" " run.",
help="Number of gem5 processes within the dist gem5 run.",
)
parser.add_argument(
"--dist-server-name",
default="127.0.0.1",
action="store",
type=str,
help="Name of the message server host\nDEFAULT:" " localhost",
help="Name of the message server host\nDEFAULT: localhost",
)
parser.add_argument(
"--dist-server-port",

16
configs/example/gpufs/amd/AmdGPUOptions.py
View File

@@ -49,7 +49,7 @@ def addAmdGPUOptions(parser):
"--cu-per-sqc",
type=int,
default=4,
help="number of CUs sharing an SQC" " (icache, and thus icache TLB)",
help="number of CUs sharing an SQC (icache, and thus icache TLB)",
)
parser.add_argument(
"--cu-per-scalar-cache",
@@ -102,19 +102,19 @@ def addAmdGPUOptions(parser):
"--issue-period",
type=int,
default=4,
help="Number of cycles per vector instruction issue" " period",
help="Number of cycles per vector instruction issue period",
)
parser.add_argument(
"--glbmem-wr-bus-width",
type=int,
default=32,
help="VGPR to Coalescer (Global Memory) data bus width" " in bytes",
help="VGPR to Coalescer (Global Memory) data bus width in bytes",
)
parser.add_argument(
"--glbmem-rd-bus-width",
type=int,
default=32,
help="Coalescer to VGPR (Global Memory) data bus width" " in bytes",
help="Coalescer to VGPR (Global Memory) data bus width in bytes",
)
# Currently we only support 1 local memory pipe
parser.add_argument(
@@ -204,20 +204,20 @@ def addAmdGPUOptions(parser):
parser.add_argument(
"--LocalMemBarrier",
action="store_true",
help="Barrier does not wait for writethroughs to " " complete",
help="Barrier does not wait for writethroughs to complete",
)
parser.add_argument(
"--countPages",
action="store_true",
help="Count Page Accesses and output in " " per-CU output files",
help="Count Page Accesses and output in per-CU output files",
)
parser.add_argument(
"--TLB-prefetch", type=int, help="prefetch depth for" "TLBs"
"--TLB-prefetch", type=int, help="prefetch depth for TLBs"
)
parser.add_argument(
"--pf-type",
type=str,
help="type of prefetch: " "PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
)
parser.add_argument("--pf-stride", type=int, help="set prefetch stride")
parser.add_argument(

4
configs/example/gpufs/runfs.py
View File

@@ -110,13 +110,13 @@ def addRunFSOptions(parser):
action="store",
type=str,
default="16GB",
help="Specify the dGPU physical memory" " size",
help="Specify the dGPU physical memory size",
)
parser.add_argument(
"--dgpu-num-dirs",
type=int,
default=1,
help="Set " "the number of dGPU directories (memory controllers",
help="Set the number of dGPU directories (memory controllers",
)
parser.add_argument(
"--dgpu-mem-type",

4
src/arch/arm/ArmFsWorkload.py
View File

@@ -78,10 +78,10 @@ class ArmFsWorkload(KernelWorkload):
)
panic_on_panic = Param.Bool(
False, "Trigger a gem5 panic if the " "guest kernel panics"
False, "Trigger a gem5 panic if the guest kernel panics"
)
panic_on_oops = Param.Bool(
False, "Trigger a gem5 panic if the " "guest kernel oopses"
False, "Trigger a gem5 panic if the guest kernel oopses"
)

2
src/arch/arm/ArmPMU.py
View File

@@ -88,7 +88,7 @@ class ArmPMU(SimObject):
or isinstance(newObject, SoftwareIncrement)
):
raise TypeError(
"argument must be of ProbeEvent or " "SoftwareIncrement type"
"argument must be of ProbeEvent or SoftwareIncrement type"
)
if not self._events:

2
src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
View File

@@ -50,7 +50,7 @@ class FastModelCortexA76(IrisBaseCPU):
redistributor = Gicv3CommsTargetSocket("GIC communication target")
core_reset = IntSinkPin(
"Raising this signal will put the core into " "reset mode."
"Raising this signal will put the core into reset mode."
)
poweron_reset = IntSinkPin(
"Power on reset. Initializes all the "

42
src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
View File

@@ -49,7 +49,7 @@ class FastModelCortexR52(IrisBaseCPU):
flash = AmbaInitiatorSocket(64, "Flash")
amba = AmbaInitiatorSocket(64, "AMBA initiator socket")
core_reset = IntSinkPin(
"Raising this signal will put the core into " "reset mode."
"Raising this signal will put the core into reset mode."
)
poweron_reset = IntSinkPin(
"Power on reset. Initializes all the "
@@ -68,7 +68,7 @@ class FastModelCortexR52(IrisBaseCPU):
CFGTE = Param.Bool(False, "Equivalent to CFGTHUMBEXCEPTIONS")
RVBARADDR = Param.UInt32(0, "Equivalent to CFGVECTABLE")
ase_present = Param.Bool(
True, "Set whether the model has been built " "with NEON support"
True, "Set whether the model has been built with NEON support"
)
dcache_size = Param.UInt16(0x8000, "L1 D-Cache size in bytes")
flash_enable = Param.Bool(False, "Equivalent to CFGFLASHEN")
@@ -88,33 +88,33 @@ class FastModelCortexR52(IrisBaseCPU):
"(0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)",
)
semihosting_A32_HLT = Param.UInt16(
0xF000, "A32 HLT number for " "semihosting calls."
0xF000, "A32 HLT number for semihosting calls."
)
semihosting_ARM_SVC = Param.UInt32(
0x123456, "A32 SVC number for " "semihosting calls."
0x123456, "A32 SVC number for semihosting calls."
)
semihosting_T32_HLT = Param.UInt8(
60, "T32 HLT number for semihosting " "calls."
60, "T32 HLT number for semihosting calls."
)
semihosting_Thumb_SVC = Param.UInt8(
171, "T32 SVC number for " "semihosting calls."
171, "T32 SVC number for semihosting calls."
)
semihosting_cmd_line = Param.String(
"", "Command line available to " "semihosting calls."
"", "Command line available to semihosting calls."
)
semihosting_cwd = Param.String(
"", "Base directory for semihosting " "file access."
"", "Base directory for semihosting file access."
)
semihosting_enable = Param.Bool(True, "Enable semihosting SVC/HLT traps.")
semihosting_heap_base = Param.UInt32(0, "Virtual address of heap base.")
semihosting_heap_limit = Param.UInt32(
0xF000000, "Virtual address of " "top of heap."
0xF000000, "Virtual address of top of heap."
)
semihosting_stack_base = Param.UInt32(
0x10000000, "Virtual address of " "base of descending stack."
0x10000000, "Virtual address of base of descending stack."
)
semihosting_stack_limit = Param.UInt32(
0xF000000, "Virtual address of " "stack limit."
0xF000000, "Virtual address of stack limit."
)
tcm_a_enable = Param.Bool(False, "Equivalent to CFGTCMBOOT")
tcm_a_size = Param.UInt32(0x4000, "Sets the size of the ATCM(in bytes)")
@@ -122,7 +122,7 @@ class FastModelCortexR52(IrisBaseCPU):
tcm_c_size = Param.UInt32(0x2000, "Sets the size of the CTCM(in bytes)")
vfp_dp_present = Param.Bool(
True,
"Whether double-precision floating " "point feature is implemented",
"Whether double-precision floating point feature is implemented",
)
vfp_enable_at_reset = Param.Bool(
False,
@@ -171,10 +171,10 @@ class FastModelCortexR52Cluster(SimObject):
PERIPHBASE = Param.UInt32(0x13080000, "Equivalent to CFGPERIPHBASE")
cluster_utid = Param.UInt8(0, "Equivalent to CFGCLUSTERUTID")
cpi_div = Param.UInt32(
1, "Divider for calculating CPI " "(Cycles Per Instruction)"
1, "Divider for calculating CPI (Cycles Per Instruction)"
)
cpi_mul = Param.UInt32(
1, "Multiplier for calculating CPI " "(Cycles Per Instruction)"
1, "Multiplier for calculating CPI (Cycles Per Instruction)"
)
dcache_prefetch_enabled = Param.Bool(
False,
@@ -194,7 +194,7 @@ class FastModelCortexR52Cluster(SimObject):
"upstream bus, this is only used when dcache-state_modelled=true.",
)
dcache_state_modelled = Param.Bool(
False, "Set whether D-cache has " "stateful implementation"
False, "Set whether D-cache has stateful implementation"
)
dcache_write_access_latency = Param.UInt64(
0,
@@ -206,7 +206,7 @@ class FastModelCortexR52Cluster(SimObject):
"is only used when dcache-state_modelled=true.",
)
flash_protection_enable_at_reset = Param.Bool(
False, "Equivalent to " "CFGFLASHPROTEN"
False, "Equivalent to CFGFLASHPROTEN"
)
has_flash_protection = Param.Bool(True, "Equivalent to CFGFLASHPROTIMP")
icache_prefetch_enabled = Param.Bool(
@@ -227,7 +227,7 @@ class FastModelCortexR52Cluster(SimObject):
"upstream bus, this is only used when icache-state_modelled=true.",
)
icache_state_modelled = Param.Bool(
False, "Set whether I-cache has " "stateful implementation"
False, "Set whether I-cache has stateful implementation"
)
memory_ext_slave_base = Param.UInt32(0, "Equivalent to CFGAXISTCMBASEADDR")
memory_flash_base = Param.UInt32(0, "Equivalent to CFGFLASHBASEADDR")
@@ -237,16 +237,16 @@ class FastModelCortexR52Cluster(SimObject):
"memory.flash_size = 0 => CFGFLASHIMP = false",
)
num_protection_regions_s1 = Param.UInt8(
16, "Number of v8-R stage1 " "protection regions"
16, "Number of v8-R stage1 protection regions"
)
num_protection_regions_s2 = Param.UInt8(
16, "Number of v8-R hyp " "protection regions"
16, "Number of v8-R hyp protection regions"
)
num_spi = Param.UInt16(
960, "Number of interrupts (SPI) into the " "internal GIC controller"
960, "Number of interrupts (SPI) into the internal GIC controller"
)
ram_protection_enable_at_reset = Param.Bool(
False, "Equivalent to " "CFGRAMPROTEN"
False, "Equivalent to CFGRAMPROTEN"
)
has_export_m_port = Param.Bool(
True,

114
src/arch/arm/fastmodel/GIC/FastModelGIC.py
View File

@@ -90,10 +90,10 @@ class SCFastModelGIC(SystemC_ScModule):
vPEID_bits = Param.Unsigned(16, "Number of bits of vPEID with GICv4.1.")
print_mmap = Param.Bool(False, "Print memory map to stdout")
monolithic = Param.Bool(
False, "Indicate that the implementation is not " "distributed"
False, "Indicate that the implementation is not distributed"
)
direct_lpi_support = Param.Bool(
False, "Enable support for LPI " "operations through GICR registers"
False, "Enable support for LPI operations through GICR registers"
)
cpu_affinities = Param.String(
"",
@@ -124,42 +124,42 @@ class SCFastModelGIC(SystemC_ScModule):
"SPI signalling register aliases(0:Disabled)",
)
has_two_security_states = Param.Bool(
True, "If true, has two security " "states"
True, "If true, has two security states"
)
DS_fixed_to_zero = Param.Bool(
False, "Enable/disable support of single " "security state"
False, "Enable/disable support of single security state"
)
IIDR = Param.UInt32(0x0, "GICD_IIDR and GICR_IIDR value")
gicv2_only = Param.Bool(
False,
"If true, when using the GICv3 model, " "pretend to be a GICv2 system",
"If true, when using the GICv3 model, pretend to be a GICv2 system",
)
STATUSR_implemented = Param.Bool(
True, "Determines whether the " "GICR_STATUSR register is implemented."
True, "Determines whether the GICR_STATUSR register is implemented."
)
priority_bits_implemented = Param.Unsigned(
5, "Number of implemented " "priority bits"
5, "Number of implemented priority bits"
)
itargets_razwi = Param.Bool(
False, "If true, the GICD_ITARGETS registers " "are RAZ/WI"
False, "If true, the GICD_ITARGETS registers are RAZ/WI"
)
icfgr_sgi_mask = Param.UInt32(
0x0, "Mask for writes to ICFGR registers " "that configure SGIs"
0x0, "Mask for writes to ICFGR registers that configure SGIs"
)
icfgr_ppi_mask = Param.UInt32(
0xAAAAAAAA, "Mask for writes to ICFGR " "registers that configure PPIs"
0xAAAAAAAA, "Mask for writes to ICFGR registers that configure PPIs"
)
icfgr_spi_mask = Param.UInt32(
0xAAAAAAAA, "Mask for writes to ICFGR " "registers that configure SPIs"
0xAAAAAAAA, "Mask for writes to ICFGR registers that configure SPIs"
)
icfgr_sgi_reset = Param.UInt32(
0xAAAAAAAA, "Reset value for ICFGR " "registers that configure SGIs"
0xAAAAAAAA, "Reset value for ICFGR registers that configure SGIs"
)
icfgr_ppi_reset = Param.UInt32(
0x0, "Reset value for ICFGR regesters " "that configure PPIs"
0x0, "Reset value for ICFGR regesters that configure PPIs"
)
icfgr_spi_reset = Param.UInt32(
0x0, "Reset value for ICFGR regesters " "that configure SPIs"
0x0, "Reset value for ICFGR regesters that configure SPIs"
)
icfgr_ppi_rsvd_bit = Param.Bool(
False,
@@ -167,16 +167,16 @@ class SCFastModelGIC(SystemC_ScModule):
"bits i.e. bit 0,2,4..30 of ICFGRn for n>0",
)
igroup_sgi_mask = Param.UInt16(
0xFFFF, "Mask for writes to SGI bits in " "IGROUP registers"
0xFFFF, "Mask for writes to SGI bits in IGROUP registers"
)
igroup_ppi_mask = Param.UInt16(
0xFFFF, "Mask for writes to PPI bits in " "IGROUP registers"
0xFFFF, "Mask for writes to PPI bits in IGROUP registers"
)
igroup_sgi_reset = Param.UInt16(
0x0, "Reset value for SGI bits in IGROUP " "registers"
0x0, "Reset value for SGI bits in IGROUP registers"
)
igroup_ppi_reset = Param.UInt16(
0x0, "Reset value for SGI bits in IGROUP " "registers"
0x0, "Reset value for SGI bits in IGROUP registers"
)
ppi_implemented_mask = Param.UInt16(
0xFFFF,
@@ -220,16 +220,16 @@ class SCFastModelGIC(SystemC_ScModule):
"to be instantiated (0=none)",
)
its0_base = Param.Addr(
0, "Register base address for ITS0 " "(automatic if 0)."
0, "Register base address for ITS0 (automatic if 0)."
)
its1_base = Param.Addr(
0, "Register base address for ITS1 " "(automatic if 0)."
0, "Register base address for ITS1 (automatic if 0)."
)
its2_base = Param.Addr(
0, "Register base address for ITS2 " "(automatic if 0)."
0, "Register base address for ITS2 (automatic if 0)."
)
its3_base = Param.Addr(
0, "Register base address for ITS3 " "(automatic if 0)."
0, "Register base address for ITS3 (automatic if 0)."
)
gits_pidr = Param.UInt64(
0x0,
@@ -286,52 +286,52 @@ class SCFastModelGIC(SystemC_ScModule):
"2 = Virtual Processors; 3 = Physical Processors; 4 = Collections",
)
gits_baser0_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER0 register."
8, "Number of bytes required per entry for GITS_BASER0 register."
)
gits_baser1_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER1 register."
8, "Number of bytes required per entry for GITS_BASER1 register."
)
gits_baser2_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER2 register."
8, "Number of bytes required per entry for GITS_BASER2 register."
)
gits_baser3_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER3 register."
8, "Number of bytes required per entry for GITS_BASER3 register."
)
gits_baser4_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER4 register."
8, "Number of bytes required per entry for GITS_BASER4 register."
)
gits_baser5_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER5 register."
8, "Number of bytes required per entry for GITS_BASER5 register."
)
gits_baser6_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER6 register."
8, "Number of bytes required per entry for GITS_BASER6 register."
)
gits_baser7_entry_bytes = Param.Unsigned(
8, "Number of bytes required per " "entry for GITS_BASER7 register."
8, "Number of bytes required per entry for GITS_BASER7 register."
)
gits_baser0_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER0 register is RAZ/WI."
False, "Indirect field for GITS_BASER0 register is RAZ/WI."
)
gits_baser1_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER1 register is RAZ/WI."
False, "Indirect field for GITS_BASER1 register is RAZ/WI."
)
gits_baser2_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER2 register is RAZ/WI."
False, "Indirect field for GITS_BASER2 register is RAZ/WI."
)
gits_baser3_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER3 register is RAZ/WI."
False, "Indirect field for GITS_BASER3 register is RAZ/WI."
)
gits_baser4_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER4 register is RAZ/WI."
False, "Indirect field for GITS_BASER4 register is RAZ/WI."
)
gits_baser5_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER5 register is RAZ/WI."
False, "Indirect field for GITS_BASER5 register is RAZ/WI."
)
gits_baser6_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER6 register is RAZ/WI."
False, "Indirect field for GITS_BASER6 register is RAZ/WI."
)
gits_baser7_indirect_raz = Param.Bool(
False, "Indirect field for " "GITS_BASER7 register is RAZ/WI."
False, "Indirect field for GITS_BASER7 register is RAZ/WI."
)
its_baser_force_page_alignement = Param.Bool(
True,
@@ -352,25 +352,25 @@ class SCFastModelGIC(SystemC_ScModule):
"port rather than an AXI4 port).",
)
a3_affinity_supported = Param.Bool(
False, "Device supports affinity " "level 3 values that are non-zero."
False, "Device supports affinity level 3 values that are non-zero."
)
SGI_RSS_support = Param.Bool(
False, "Device has support for the Range " "Selector feature for SGI"
False, "Device has support for the Range Selector feature for SGI"
)
gicr_propbaser_read_only = Param.Bool(
False, "GICR_PROPBASER register is " "read-only."
False, "GICR_PROPBASER register is read-only."
)
gicr_propbaser_reset = Param.UInt64(
0x0, "Value of GICR_PROPBASER on " "reset."
0x0, "Value of GICR_PROPBASER on reset."
)
its_device_bits = Param.Unsigned(
16, "Number of bits supported for ITS " "device IDs."
16, "Number of bits supported for ITS device IDs."
)
its_entry_size = Param.Unsigned(
8, "Number of bytes required to store " "each entry in the ITT tables."
8, "Number of bytes required to store each entry in the ITT tables."
)
its_id_bits = Param.Unsigned(
16, "Number of interrupt bits supported by " "ITS."
16, "Number of interrupt bits supported by ITS."
)
its_collection_id_bits = Param.Unsigned(
0,
@@ -386,7 +386,7 @@ class SCFastModelGIC(SystemC_ScModule):
"the number supported in memory only. Irrelevant when HCC=0",
)
delay_ITS_accesses = Param.Bool(
True, "Delay accesses from the ITS until " "GICR_SYNCR is read."
True, "Delay accesses from the ITS until GICR_SYNCR is read."
)
local_SEIs = Param.Bool(False, "Generate SEI to signal internal issues")
local_VSEIs = Param.Bool(False, "Generate VSEI to signal internal issues")
@@ -397,10 +397,10 @@ class SCFastModelGIC(SystemC_ScModule):
"for distributed implementations",
)
ITS_hardware_collection_count = Param.Unsigned(
0, "Number of hardware " "collections held exclusively in the ITS"
0, "Number of hardware collections held exclusively in the ITS"
)
ITS_MOVALL_update_collections = Param.Bool(
False, "Whether MOVALL command " "updates the collection entires"
False, "Whether MOVALL command updates the collection entires"
)
ITS_TRANSLATE64R = Param.Bool(
False,
@@ -409,7 +409,7 @@ class SCFastModelGIC(SystemC_ScModule):
"interupt[31:0])",
)
enable_protocol_checking = Param.Bool(
False, "Enable/disable protocol " "checking at cpu interface"
False, "Enable/disable protocol checking at cpu interface"
)
fixed_routed_spis = Param.String(
"",
@@ -470,13 +470,13 @@ class SCFastModelGIC(SystemC_ScModule):
)
virtual_lpi_support = Param.Bool(
False,
"GICv4 Virtual LPIs and Direct " "injection of Virtual LPIs supported",
"GICv4 Virtual LPIs and Direct injection of Virtual LPIs supported",
)
virtual_priority_bits = Param.Unsigned(
5, "Number of implemented virtual " "priority bits"
5, "Number of implemented virtual priority bits"
)
LPI_cache_type = Param.Unsigned(
1, "Cache type for LPIs, 0:No caching, " "1:Full caching"
1, "Cache type for LPIs, 0:No caching, 1:Full caching"
)
LPI_cache_check_data = Param.Bool(
False,
@@ -490,7 +490,7 @@ class SCFastModelGIC(SystemC_ScModule):
)
DPG_ARE_only = Param.Bool(
False,
"Limit application of DPG bits to " "interrupt groups for which ARE=1",
"Limit application of DPG bits to interrupt groups for which ARE=1",
)
ARE_fixed_to_one = Param.Bool(
False,
@@ -498,7 +498,7 @@ class SCFastModelGIC(SystemC_ScModule):
"supported and GICD_CTLR.ARE_* is always one",
)
legacy_sgi_enable_rao = Param.Bool(
False, "Enables for SGI associated " "with an ARE=0 regime are RAO/WI"
False, "Enables for SGI associated with an ARE=0 regime are RAO/WI"
)
pa_size = Param.Unsigned(48, "Number of valid bits in physical address")
MSI_IIDR = Param.UInt32(0x0, "Value returned in MSI_IIDR registers.")
@@ -763,7 +763,7 @@ class SCFastModelGIC(SystemC_ScModule):
"the core fast model.",
)
SPI_MBIS = Param.Bool(
True, "Distributor supports meassage based " "signaling of SPI"
True, "Distributor supports meassage based signaling of SPI"
)
SPI_unimplemented = Param.String(
"",
@@ -772,7 +772,7 @@ class SCFastModelGIC(SystemC_ScModule):
"'35, 39-42, 73)'",
)
irm_razwi = Param.Bool(
False, "GICD_IROUTERn.InterruptRoutingMode is " "RAZ/WI"
False, "GICD_IROUTERn.InterruptRoutingMode is RAZ/WI"
)
common_LPI_configuration = Param.Unsigned(
0,
@@ -810,7 +810,7 @@ class SCFastModelGIC(SystemC_ScModule):
"transient loading state when valid=1",
)
allow_LPIEN_clear = Param.Bool(
False, "Allow RW behaviour on " "GICR_CTLR.LPIEN isntead of set once"
False, "Allow RW behaviour on GICR_CTLR.LPIEN isntead of set once"
)
GICD_legacy_reg_reserved = Param.Bool(
False,

2
src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
View File

@@ -87,7 +87,7 @@ class FastModelPL330(SystemC_ScModule):
cache_lines = Param.UInt32(1, "number of cache lines")
max_channels = Param.UInt32(8, "virtual channels")
controller_nsecure = Param.Bool(
False, "Controller non-secure at reset " "(boot_manager_ns)"
False, "Controller non-secure at reset (boot_manager_ns)"
)
irq_nsecure = Param.UInt32(0, "Interrupts non-secure at reset")
periph_nsecure = Param.Bool(False, "Peripherals non-secure at reset")

4
src/arch/isa_parser/isa_parser.py
View File

@@ -133,7 +133,7 @@ class Template(object):
"""
pcstate_decl = (
f"{self.parser.namespace}::PCState " "__parserAutoPCState;\n"
f"{self.parser.namespace}::PCState __parserAutoPCState;\n"
)
myDict["op_decl"] = operands.concatAttrStrings("op_decl")
if operands.readPC or operands.setPC:
@@ -1098,7 +1098,7 @@ del wrap
# 'def [signed] bitfield <ID> [<first>:<last>]'
# This generates a preprocessor macro in the output file.
def p_def_bitfield_0(self, t):
"def_bitfield : DEF opt_signed " "BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI"
"def_bitfield : DEF opt_signed BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI"
expr = "bits(machInst, %2d, %2d)" % (t[6], t[8])
if t[2] == "signed":
expr = "sext<%d>(%s)" % (t[6] - t[8] + 1, expr)

2
src/cpu/BaseCPU.py
View File

@@ -228,7 +228,7 @@ class BaseCPU(ClockedObject):
else:
if len(self.isa) != int(self.numThreads):
raise RuntimeError(
"Number of ISA instances doesn't " "match thread count"
"Number of ISA instances doesn't match thread count"
)
if len(self.decoder) != 0:
raise RuntimeError("Decoders should not be set up manually")

14
src/cpu/minor/BaseMinorCPU.py
View File

@@ -67,7 +67,7 @@ class MinorOpClassSet(SimObject):
cxx_class = "gem5::MinorOpClassSet"
opClasses = VectorParam.MinorOpClass(
[], "op classes to be matched." " An empty list means any class"
[], "op classes to be matched. An empty list means any class"
)
@@ -83,13 +83,13 @@ class MinorFUTiming(SimObject):
" (ext_mach_inst & mask) == match",
)
suppress = Param.Bool(
False, "if true, this inst. is not executed by" " this FU"
False, "if true, this inst. is not executed by this FU"
)
extraCommitLat = Param.Cycles(
0, "extra cycles to stall commit for" " this inst."
0, "extra cycles to stall commit for this inst."
)
extraCommitLatExpr = Param.TimingExpr(
NULL, "extra cycles as a" " run-time evaluated expression"
NULL, "extra cycles as a run-time evaluated expression"
)
extraAssumedLat = Param.Cycles(
0,
@@ -109,7 +109,7 @@ class MinorFUTiming(SimObject):
" class",
)
description = Param.String(
"", "description string of the decoding/inst." " class"
"", "description string of the decoding/inst class"
)
@@ -129,11 +129,11 @@ class MinorFU(SimObject):
opClasses = Param.MinorOpClassSet(
MinorOpClassSet(),
"type of operations" " allowed on this functional unit",
"type of operations allowed on this functional unit",
)
opLat = Param.Cycles(1, "latency in cycles")
issueLat = Param.Cycles(
1, "cycles until another instruction can be" " issued"
1, "cycles until another instruction can be issued"
)
timings = VectorParam.MinorFUTiming([], "extra decoding rules")

32
src/cpu/o3/BaseO3CPU.py
View File

@@ -79,47 +79,43 @@ class BaseO3CPU(BaseCPU):
activity = Param.Unsigned(0, "Initial count")
cacheStorePorts = Param.Unsigned(
200, "Cache Ports. " "Constrains stores only."
)
cacheLoadPorts = Param.Unsigned(
200, "Cache Ports. " "Constrains loads only."
200, "Cache Ports. Constrains stores only."
)
cacheLoadPorts = Param.Unsigned(200, "Cache Ports. Constrains loads only.")
decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
renameToFetchDelay = Param.Cycles(1, "Rename to fetch delay")
iewToFetchDelay = Param.Cycles(
1, "Issue/Execute/Writeback to fetch " "delay"
)
iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch delay")
commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
fetchWidth = Param.Unsigned(8, "Fetch width")
fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
fetchQueueSize = Param.Unsigned(
32, "Fetch queue size in micro-ops " "per-thread"
32, "Fetch queue size in micro-ops per-thread"
)
renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
iewToDecodeDelay = Param.Cycles(
1, "Issue/Execute/Writeback to decode " "delay"
1, "Issue/Execute/Writeback to decode delay"
)
commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
decodeWidth = Param.Unsigned(8, "Decode width")
iewToRenameDelay = Param.Cycles(
1, "Issue/Execute/Writeback to rename " "delay"
1, "Issue/Execute/Writeback to rename delay"
)
commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
renameWidth = Param.Unsigned(8, "Rename width")
commitToIEWDelay = Param.Cycles(
1, "Commit to " "Issue/Execute/Writeback delay"
1, "Commit to Issue/Execute/Writeback delay"
)
renameToIEWDelay = Param.Cycles(
2, "Rename to " "Issue/Execute/Writeback delay"
2, "Rename to Issue/Execute/Writeback delay"
)
issueToExecuteDelay = Param.Cycles(
1, "Issue to execute delay (internal " "to the IEW stage)"
1, "Issue to execute delay (internal to the IEW stage)"
)
dispatchWidth = Param.Unsigned(8, "Dispatch width")
issueWidth = Param.Unsigned(8, "Issue width")
@@ -127,7 +123,7 @@ class BaseO3CPU(BaseCPU):
fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
iewToCommitDelay = Param.Cycles(
1, "Issue/Execute/Writeback to commit " "delay"
1, "Issue/Execute/Writeback to commit delay"
)
renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
commitWidth = Param.Unsigned(8, "Commit width")
@@ -166,13 +162,11 @@ class BaseO3CPU(BaseCPU):
256, "Number of physical integer registers"
)
numPhysFloatRegs = Param.Unsigned(
256, "Number of physical floating point " "registers"
)
numPhysVecRegs = Param.Unsigned(
256, "Number of physical vector " "registers"
256, "Number of physical floating point registers"
)
numPhysVecRegs = Param.Unsigned(256, "Number of physical vector registers")
numPhysVecPredRegs = Param.Unsigned(
32, "Number of physical predicate " "registers"
32, "Number of physical predicate registers"
)
# most ISAs don't use condition-code regs, so default is 0
numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers")

6
src/cpu/o3/probe/ElasticTrace.py
View File

@@ -44,10 +44,10 @@ class ElasticTrace(ProbeListenerObject):
# Trace files for the following params are created in the output directory.
# User is forced to provide these when an instance of this class is created.
instFetchTraceFile = Param.String(
desc="Protobuf trace file name for " "instruction fetch tracing"
desc="Protobuf trace file name for instruction fetch tracing"
)
dataDepTraceFile = Param.String(
desc="Protobuf trace file name for " "data dependency tracing"
desc="Protobuf trace file name for data dependency tracing"
)
# The dependency window size param must be equal to or greater than the
# number of entries in the O3CPU ROB, a typical value is 3 times ROB size
@@ -66,5 +66,5 @@ class ElasticTrace(ProbeListenerObject):
)
# Whether to trace virtual addresses for memory accesses
traceVirtAddr = Param.Bool(
False, "Set to true if virtual addresses are " "to be traced."
False, "Set to true if virtual addresses are to be traced."
)

4
src/cpu/testers/memtest/MemTest.py
View File

@@ -70,7 +70,7 @@ class MemTest(ClockedObject):
1000000, "Progress report interval (in accesses)"
)
progress_check = Param.Cycles(
5000000, "Cycles before exiting " "due to lack of progress"
5000000, "Cycles before exiting due to lack of progress"
)
port = RequestPort("Port to the memory system")
@@ -79,5 +79,5 @@ class MemTest(ClockedObject):
# Add the ability to supress error responses on functional
# accesses as Ruby needs this
suppress_func_errors = Param.Bool(
False, "Suppress panic when " "functional accesses fail."
False, "Suppress panic when functional accesses fail."
)

2
src/cpu/testers/rubytest/RubyTester.py
View File

@@ -38,7 +38,7 @@ class RubyTester(ClockedObject):
num_cpus = Param.Int("number of cpus / RubyPorts")
cpuInstDataPort = VectorRequestPort(
"cpu combo ports to inst & " "data caches"
"cpu combo ports to inst & data caches"
)
cpuInstPort = VectorRequestPort("cpu ports to only inst caches")
cpuDataPort = VectorRequestPort("cpu ports to only data caches")

2
src/cpu/testers/traffic_gen/BaseTrafficGen.py
View File

@@ -82,7 +82,7 @@ class BaseTrafficGen(ClockedObject):
# progress for a long period of time. The default value is
# somewhat arbitrary and may well have to be tuned.
progress_check = Param.Latency(
"1ms", "Time before exiting " "due to lack of progress"
"1ms", "Time before exiting due to lack of progress"
)
# Generator type used for applying Stream and/or Substream IDs to requests

4
src/cpu/testers/traffic_gen/GUPSGen.py
View File

@@ -58,11 +58,11 @@ class GUPSGen(ClockedObject):
)
update_limit = Param.Int(
0, "The number of updates to issue before the" " simulation is over"
0, "The number of updates to issue before the simulation is over"
)
request_queue_size = Param.Int(
1024, "Maximum number of parallel" " outstanding requests"
1024, "Maximum number of parallel outstanding requests"
)
init_memory = Param.Bool(

6
src/cpu/trace/TraceCPU.py
View File

@@ -64,7 +64,7 @@ class TraceCPU(BaseCPU):
instTraceFile = Param.String("", "Instruction trace file")
dataTraceFile = Param.String("", "Data dependency trace file")
sizeStoreBuffer = Param.Unsigned(
16, "Number of entries in the store " "buffer"
16, "Number of entries in the store buffer"
)
sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer")
sizeROB = Param.Unsigned(40, "Number of entries in the re-order buffer")
@@ -74,13 +74,13 @@ class TraceCPU(BaseCPU):
# changed when frequency is scaled. A default value of 1.0 means the same
# frequency as was used for generating the traces.
freqMultiplier = Param.Float(
1.0, "Multiplier scale the Trace CPU " "frequency up or down"
1.0, "Multiplier scale the Trace CPU frequency up or down"
)
# Enable exiting when any one Trace CPU completes execution which is set to
# false by default
enableEarlyExit = Param.Bool(
False, "Exit when any one Trace CPU " "completes execution"
False, "Exit when any one Trace CPU completes execution"
)
# If progress msg interval is set to a non-zero value, it is treated as

2
src/dev/amdgpu/AMDGPU.py
View File

@@ -73,7 +73,7 @@ class AMDGPUDevice(PciDevice):
rom_binary = Param.String("ROM binary dumped from hardware")
trace_file = Param.String("MMIO trace collected on hardware")
checkpoint_before_mmios = Param.Bool(
False, "Take a checkpoint before the" " device begins sending MMIOs"
False, "Take a checkpoint before the device begins sending MMIOs"
)
# Specific to Vega10: Vega10 has two SDMA engines these do not have any

12
src/dev/arm/RealView.py
View File

@@ -117,7 +117,7 @@ class AmbaDmaDevice(DmaDevice):
pio_addr = Param.Addr("Address for AMBA responder interface")
pio_latency = Param.Latency(
"10ns",
"Time between action and write/read" "result by AMBA DMA Device",
"Time between action and write/readresult by AMBA DMA Device",
)
interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
amba_id = Param.UInt32("ID of AMBA device for kernel detection")
@@ -634,17 +634,17 @@ class HDLcd(AmbaDmaDevice):
cxx_header = "dev/arm/hdlcd.hh"
cxx_class = "gem5::HDLcd"
vnc = Param.VncInput(
Parent.any, "Vnc server for remote frame buffer " "display"
Parent.any, "Vnc server for remote frame buffer display"
)
amba_id = 0x00141000
workaround_swap_rb = Param.Bool(
False, "Workaround incorrect color " "selector order in some kernels"
False, "Workaround incorrect color selector order in some kernels"
)
workaround_dma_line_count = Param.Bool(
True, "Workaround incorrect " "DMA line count (off by 1)"
True, "Workaround incorrect DMA line count (off by 1)"
)
enable_capture = Param.Bool(
True, "capture frame to " "system.framebuffer.{extension}"
True, "capture frame to system.framebuffer.{extension}"
)
frame_format = Param.ImageFormat(
"Auto", "image format of the captured frame"
@@ -655,7 +655,7 @@ class HDLcd(AmbaDmaDevice):
pxl_clk = Param.ClockDomain("Pixel clock source")
pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
virt_refresh_rate = Param.Frequency(
"20Hz", "Frame refresh rate " "in KVM mode"
"20Hz", "Frame refresh rate in KVM mode"
)
_status = "ok"

4
src/dev/arm/SMMUv3.py
View File

@@ -48,13 +48,13 @@ class SMMUv3DeviceInterface(ClockedObject):
device_port = ResponsePort("Device port")
slave = DeprecatedParam(device_port, "`slave` is now called `device_port`")
ats_mem_side_port = RequestPort(
"ATS mem side port," "sends requests and receives responses"
"ATS mem side port,sends requests and receives responses"
)
ats_master = DeprecatedParam(
ats_mem_side_port, "`ats_master` is now called `ats_mem_side_port`"
)
ats_dev_side_port = ResponsePort(
"ATS dev_side_port," "sends responses and receives requests"
"ATS dev_side_port,sends responses and receives requests"
)
ats_slave = DeprecatedParam(
ats_dev_side_port, "`ats_slave` is now called `ats_dev_side_port`"

2
src/dev/net/Ethernet.py
View File

@@ -107,7 +107,7 @@ class EtherSwitch(SimObject):
dump = Param.EtherDump(NULL, "dump object")
fabric_speed = Param.NetworkBandwidth(
"10Gbps", "switch fabric speed in " "bits per second"
"10Gbps", "switch fabric speed in bits per second"
)
interface = VectorEtherInt("Ethernet Interface")
output_buffer_size = Param.MemorySize(

2
src/dev/pci/PciHost.py
View File

@@ -57,7 +57,7 @@ class GenericPciHost(PciHost):
conf_base = Param.Addr("Config space base address")
conf_size = Param.Addr("Config space base address")
conf_device_bits = Param.UInt8(
8, "Number of bits used to as an " "offset a devices address space"
8, "Number of bits used to as an offset a devices address space"
)
pci_pio_base = Param.Addr(0, "Base address for PCI IO accesses")

2
src/dev/serial/Uart.py
View File

@@ -61,7 +61,7 @@ class SimpleUart(Uart):
byte_order = Param.ByteOrder("little", "Device byte order")
pio_size = Param.Addr(0x4, "Size of address range")
end_on_eot = Param.Bool(
False, "End the simulation when a EOT is " "received on the UART"
False, "End the simulation when a EOT is received on the UART"
)

42
src/gpu-compute/GPU.py
View File

@@ -115,7 +115,7 @@ class Wavefront(SimObject):
wf_size = Param.Int(64, "Wavefront size (in work items)")
max_ib_size = Param.Int(
13,
"Maximum size (in number of insts) of the " "instruction buffer (IB).",
"Maximum size (in number of insts) of the instruction buffer (IB).",
)
@@ -134,32 +134,32 @@ class ComputeUnit(ClockedObject):
num_SIMDs = Param.Int(4, "number of SIMD units per CU")
num_scalar_cores = Param.Int(1, "number of Scalar cores per CU")
num_scalar_mem_pipes = Param.Int(
1, "number of Scalar memory pipelines " "per CU"
1, "number of Scalar memory pipelines per CU"
)
simd_width = Param.Int(16, "width (number of lanes) per SIMD unit")
operand_network_length = Param.Int(
1, "number of pipe stages of operand " "network"
1, "number of pipe stages of operand network"
)
spbypass_pipe_length = Param.Int(
4, "vector ALU Single Precision bypass " "latency"
4, "vector ALU Single Precision bypass latency"
)
dpbypass_pipe_length = Param.Int(
4, "vector ALU Double Precision bypass " "latency"
4, "vector ALU Double Precision bypass latency"
)
scalar_pipe_length = Param.Int(1, "number of pipe stages per scalar ALU")
issue_period = Param.Int(4, "number of cycles per issue period")
vrf_gm_bus_latency = Param.Int(
1, "number of cycles per use of VRF to " "GM bus"
1, "number of cycles per use of VRF to GM bus"
)
srf_scm_bus_latency = Param.Int(
1, "number of cycles per use of SRF " "to Scalar Mem bus"
1, "number of cycles per use of SRF to Scalar Mem bus"
)
vrf_lm_bus_latency = Param.Int(
1, "number of cycles per use of VRF to " "LM bus"
1, "number of cycles per use of VRF to LM bus"
)
num_global_mem_pipes = Param.Int(1, "number of global memory pipes per CU")
@@ -194,10 +194,10 @@ class ComputeUnit(ClockedObject):
system = Param.System(Parent.any, "system object")
cu_id = Param.Int("CU id")
vrf_to_coalescer_bus_width = Param.Int(
64, "VRF->Coalescer data bus " "width in bytes"
64, "VRF->Coalescer data bus width in bytes"
)
coalescer_to_vrf_bus_width = Param.Int(
64, "Coalescer->VRF data bus " "width in bytes"
64, "Coalescer->VRF data bus width in bytes"
)
memory_port = VectorRequestPort("Port to the memory system")
@@ -211,7 +211,7 @@ class ComputeUnit(ClockedObject):
perLaneTLB = Param.Bool(False, "enable per-lane TLB")
prefetch_depth = Param.Int(
0,
"Number of prefetches triggered at a time" "(0 turns off prefetching)",
"Number of prefetches triggered at a time(0 turns off prefetching)",
)
prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)")
prefetch_prev_type = Param.PrefetchType(
@@ -225,24 +225,24 @@ class ComputeUnit(ClockedObject):
functionalTLB = Param.Bool(False, "Assume TLB causes no delay")
localMemBarrier = Param.Bool(
False, "Assume Barriers do not wait on " "kernel end"
False, "Assume Barriers do not wait on kernel end"
)
countPages = Param.Bool(
False,
"Generate per-CU file of all pages " "touched and how many times",
"Generate per-CU file of all pages touched and how many times",
)
scalar_mem_queue_size = Param.Int(
32, "Number of entries in scalar " "memory pipeline's queues"
32, "Number of entries in scalar memory pipeline's queues"
)
global_mem_queue_size = Param.Int(
256, "Number of entries in the global " "memory pipeline's queues"
256, "Number of entries in the global memory pipeline's queues"
)
local_mem_queue_size = Param.Int(
256, "Number of entries in the local " "memory pipeline's queues"
256, "Number of entries in the local memory pipeline's queues"
)
max_wave_requests = Param.Int(
64, "number of pending vector memory " "requests per wavefront"
64, "number of pending vector memory requests per wavefront"
)
max_cu_tokens = Param.Int(
4,
@@ -254,18 +254,18 @@ class ComputeUnit(ClockedObject):
localDataStore = Param.LdsState("the LDS for this CU")
vector_register_file = VectorParam.VectorRegisterFile(
"Vector register " "file"
"Vector register file"
)
scalar_register_file = VectorParam.ScalarRegisterFile(
"Scalar register " "file"
"Scalar register file"
)
out_of_order_data_delivery = Param.Bool(
False, "enable OoO data delivery" " in the GM pipeline"
False, "enable OoO data delivery in the GM pipeline"
)
register_manager = Param.RegisterManager("Register Manager")
fetch_depth = Param.Int(
2, "number of i-cache lines that may be " "buffered in the fetch unit."
2, "number of i-cache lines that may be buffered in the fetch unit."
)

2
src/gpu-compute/LdsState.py
View File

@@ -41,7 +41,7 @@ class LdsState(ClockedObject):
size = Param.Int(65536, "the size of the LDS")
range = Param.AddrRange("64kB", "address space of the LDS")
bankConflictPenalty = Param.Int(
1, "penalty per LDS bank conflict when " "accessing data"
1, "penalty per LDS bank conflict when accessing data"
)
banks = Param.Int(32, "Number of LDS banks")
cuPort = ResponsePort("port that goes to the compute unit")

4
src/learning_gem5/part2/HelloObject.py
View File

@@ -36,7 +36,7 @@ class HelloObject(SimObject):
time_to_wait = Param.Latency("Time before firing the event")
number_of_fires = Param.Int(
1, "Number of times to fire the event before " "goodbye"
1, "Number of times to fire the event before goodbye"
)
goodbye_object = Param.GoodbyeObject("A goodbye object")
@@ -51,5 +51,5 @@ class GoodbyeObject(SimObject):
"1kB", "Size of buffer to fill with goodbye"
)
write_bandwidth = Param.MemoryBandwidth(
"100MB/s", "Bandwidth to fill " "the buffer"
"100MB/s", "Bandwidth to fill the buffer"
)

4
src/mem/AddrMapper.py
View File

@@ -50,13 +50,13 @@ class AddrMapper(SimObject):
# one port in each direction
mem_side_port = RequestPort(
"This port sends requests and " "receives responses"
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and " "sends responses"
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called `cpu_side_port`"

4
src/mem/Bridge.py
View File

@@ -46,13 +46,13 @@ class Bridge(ClockedObject):
cxx_class = "gem5::Bridge"
mem_side_port = RequestPort(
"This port sends requests and " "receives responses"
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and " "sends responses"
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called `cpu_side_port`"

16
src/mem/CommMonitor.py
View File

@@ -49,13 +49,13 @@ class CommMonitor(SimObject):
# one port in each direction
mem_side_port = RequestPort(
"This port sends requests and " "receives responses"
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and " "sends responses"
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called `cpu_side_port`"
@@ -70,10 +70,10 @@ class CommMonitor(SimObject):
# histogram of burst length of packets (not using sample period)
burst_length_bins = Param.Unsigned(
"20", "# bins in burst length " "histograms"
"20", "# bins in burst length histograms"
)
disable_burst_length_hists = Param.Bool(
False, "Disable burst length " "histograms"
False, "Disable burst length histograms"
)
# bandwidth per sample period
@@ -95,18 +95,18 @@ class CommMonitor(SimObject):
# outstanding requests (that did not yet get a response) per
# sample period
outstanding_bins = Param.Unsigned(
"20", "# bins in outstanding " "requests histograms"
"20", "# bins in outstanding requests histograms"
)
disable_outstanding_hists = Param.Bool(
False, "Disable outstanding " "requests histograms"
False, "Disable outstanding requests histograms"
)
# transactions (requests) observed per sample period
transaction_bins = Param.Unsigned(
"20", "# bins in transaction " "count histograms"
"20", "# bins in transaction count histograms"
)
disable_transaction_hists = Param.Bool(
False, "Disable transaction count " "histograms"
False, "Disable transaction count histograms"
)
# address distributions (heatmaps) with associated address masks

4
src/mem/DRAMInterface.py
View File

@@ -57,7 +57,7 @@ class DRAMInterface(MemInterface):
# enforce a limit on the number of accesses per row
max_accesses_per_row = Param.Unsigned(
16, "Max accesses per row before " "closing"
16, "Max accesses per row before closing"
)
# default to 0 bank groups per rank, indicating bank group architecture
@@ -139,7 +139,7 @@ class DRAMInterface(MemInterface):
# write-to-read, same rank turnaround penalty for same bank group
tWTR_L = Param.Latency(
Self.tWTR,
"Write to read, same rank switching " "time, same bank group",
"Write to read, same rank switching time, same bank group",
)
# minimum precharge to precharge delay time

4
src/mem/DRAMsim3.py
View File

@@ -44,11 +44,11 @@ class DRAMsim3(AbstractMemory):
# A single port for now
port = ResponsePort(
"port for receiving requests from" "the CPU or other requestor"
"port for receiving requests fromthe CPU or other requestor"
)
configFile = Param.String(
"ext/dramsim3/DRAMsim3/configs/" "DDR4_8Gb_x8_2400.ini",
"ext/dramsim3/DRAMsim3/configs/DDR4_8Gb_x8_2400.ini",
"The configuration file to use with DRAMSim3",
)
filePath = Param.String(

2
src/mem/ExternalSlave.py
View File

@@ -45,7 +45,7 @@ class ExternalSlave(SimObject):
port = SlavePort("Slave port")
addr_ranges = VectorParam.AddrRange(
[], "Addresses served by" " this port's external agent"
[], "Addresses served by this port's external agent"
)
port_type = Param.String(

8
src/mem/MemChecker.py
View File

@@ -51,16 +51,16 @@ class MemCheckerMonitor(SimObject):
# one port in each direction
mem_side_port = RequestPort(
"This port sends requests and receives " "responses"
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called " "`mem_side_port`"
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and sends " "responses"
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called " "`cpu_side_port`"
cpu_side_port, "`slave` is now called `cpu_side_port`"
)
warn_only = Param.Bool(False, "Warn about violations only")
memchecker = Param.MemChecker("Instance shared with other monitors")

6
src/mem/MemCtrl.py
View File

@@ -63,7 +63,7 @@ class MemCtrl(QoSMemCtrl):
# Interface to memory media
dram = Param.MemInterface(
"Memory interface, can be a DRAM" "or an NVM interface "
"Memory interface, can be a DRAMor an NVM interface "
)
# read and write buffer depths are set in the interface
@@ -79,12 +79,12 @@ class MemCtrl(QoSMemCtrl):
# minimum write bursts to schedule before switching back to reads
min_writes_per_switch = Param.Unsigned(
16, "Minimum write bursts before " "switching to reads"
16, "Minimum write bursts before switching to reads"
)
# minimum read bursts to schedule before switching back to writes
min_reads_per_switch = Param.Unsigned(
16, "Minimum read bursts before " "switching to writes"
16, "Minimum read bursts before switching to writes"
)
# scheduler, address map and page policy

4
src/mem/MemDelay.py
View File

@@ -44,13 +44,13 @@ class MemDelay(ClockedObject):
abstract = True
mem_side_port = RequestPort(
"This port sends requests and " "receives responses"
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and " "sends responses"
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called `cpu_side_port`"

6
src/mem/MemInterface.py
View File

@@ -73,11 +73,11 @@ class MemInterface(AbstractMemory):
device_size = Param.MemorySize("Size of memory device")
# the physical organisation of the memory
device_bus_width = Param.Unsigned(
"data bus width in bits for each " "memory device/chip"
"data bus width in bits for each memory device/chip"
)
burst_length = Param.Unsigned("Burst lenght (BL) in beats")
device_rowbuffer_size = Param.MemorySize(
"Page (row buffer) size per " "device/chip"
"Page (row buffer) size per device/chip"
)
devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
ranks_per_channel = Param.Unsigned("Number of ranks per channel")
@@ -96,7 +96,7 @@ class MemInterface(AbstractMemory):
# Read/Write requests with data size larger than one full burst are broken
# down into multiple requests in the controller
tBURST = Param.Latency(
"Burst duration " "(typically burst length / 2 cycles)"
"Burst duration (typically burst length / 2 cycles)"
)
# write-to-read, same rank turnaround penalty

4
src/mem/PortTerminator.py
View File

@@ -35,8 +35,8 @@ class PortTerminator(SimObject):
cxx_class = "gem5::PortTerminator"
req_ports = VectorRequestPort(
"Vector port for connecting terminating " "response ports."
"Vector port for connecting terminating response ports."
)
resp_ports = VectorResponsePort(
"Vector port for terminating " "request ports."
"Vector port for terminating request ports."
)

6
src/mem/SerialLink.py
View File

@@ -50,13 +50,13 @@ class SerialLink(ClockedObject):
cxx_class = "gem5::SerialLink"
mem_side_port = RequestPort(
"This port sends requests and " "receives responses"
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and " "sends responses"
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called `cpu_side_port`"
@@ -71,7 +71,7 @@ class SerialLink(ClockedObject):
# link belongs to and the number of lanes:
num_lanes = Param.Unsigned(
1,
"Number of parallel lanes inside the serial" "link. (aka. lane width)",
"Number of parallel lanes inside the seriallink. (aka. lane width)",
)
link_speed = Param.UInt64(
1,

10
src/mem/XBar.py
View File

@@ -51,13 +51,13 @@ class BaseXBar(ClockedObject):
cxx_class = "gem5::BaseXBar"
cpu_side_ports = VectorResponsePort(
"Vector port for connecting " "mem side ports"
"Vector port for connecting mem side ports"
)
slave = DeprecatedParam(
cpu_side_ports, "`slave` is now called `cpu_side_ports`"
)
mem_side_ports = VectorRequestPort(
"Vector port for connecting " "cpu side ports"
"Vector port for connecting cpu side ports"
)
master = DeprecatedParam(
mem_side_ports, "`master` is now called `mem_side_ports`"
@@ -98,7 +98,7 @@ class BaseXBar(ClockedObject):
# a two-level hierarchical lookup. This is useful e.g. for the PCI
# xbar configuration.
use_default_range = Param.Bool(
False, "Perform address mapping for " "the default port"
False, "Perform address mapping for the default port"
)
@@ -130,12 +130,12 @@ class CoherentXBar(BaseXBar):
# already committed to responding, by establishing if the crossbar
# is the point of coherency or not.
point_of_coherency = Param.Bool(
False, "Consider this crossbar the " "point of coherency"
False, "Consider this crossbar the point of coherency"
)
# Specify whether this crossbar is the point of unification.
point_of_unification = Param.Bool(
False, "Consider this crossbar the " "point of unification"
False, "Consider this crossbar the point of unification"
)
system = Param.System(Parent.any, "System that the crossbar belongs to.")

6
src/mem/cache/Cache.py vendored
View File

@@ -61,10 +61,10 @@ class WriteAllocator(SimObject):
# allow whole-line write coalescing, and eventually switches to a
# write-no-allocate policy.
coalesce_limit = Param.Unsigned(
2, "Consecutive lines written before " "delaying for coalescing"
2, "Consecutive lines written before delaying for coalescing"
)
no_allocate_limit = Param.Unsigned(
12, "Consecutive lines written before" " skipping allocation"
12, "Consecutive lines written before skipping allocation"
)
delay_threshold = Param.Unsigned(
@@ -129,7 +129,7 @@ class BaseCache(ClockedObject):
# co-allocatable with another existing entry of the same superblock,
# so try move the block to co-allocate it
move_contractions = Param.Bool(
True, "Try to co-allocate blocks that " "contract"
True, "Try to co-allocate blocks that contract"
)
sequential_access = Param.Bool(

2
src/mem/cache/compressors/Compressors.py vendored
View File

@@ -232,7 +232,7 @@ class FrequentValuesCompressor(BaseCacheCompressor):
)
check_saturation = Param.Bool(
False,
"Whether the counters should be " "manipulated in case of saturation.",
"Whether the counters should be manipulated in case of saturation.",
)
vft_assoc = Param.Int(16, "Associativity of the VFT.")

2
src/mem/cache/tags/Tags.py vendored
View File

@@ -139,7 +139,7 @@ class FALRU(BaseTags):
cxx_class = "gem5::FALRU"
min_tracked_cache_size = Param.MemorySize(
"128KiB", "Minimum cache size" " for which we track statistics"
"128KiB", "Minimum cache size for which we track statistics"
)
# This tag uses its own embedded indexing

2
src/mem/probes/StackDistProbe.py
View File

@@ -44,7 +44,7 @@ class StackDistProbe(BaseMemProbe):
cxx_class = "gem5::StackDistProbe"
system = Param.System(
Parent.any, "System to use when determining system cache " "line size"
Parent.any, "System to use when determining system cache line size"
)
line_size = Param.Unsigned(

2
src/mem/ruby/slicc_interface/Controller.py
View File

@@ -49,7 +49,7 @@ class RubyController(ClockedObject):
version = Param.Int("")
addr_ranges = VectorParam.AddrRange(
[AllMemory], "Address range this " "controller responds to"
[AllMemory], "Address range this controller responds to"
)
cluster_id = Param.UInt32(0, "Id of this controller's cluster")

2
src/mem/ruby/system/GPUCoalescer.py
View File

@@ -44,7 +44,7 @@ class RubyGPUCoalescer(RubyPort):
40 * 64, "max requests (incl. prefetches) outstanding"
)
max_coalesces_per_cycle = Param.Int(
1, "max instructions that can be " "coalesced in a single cycle"
1, "max instructions that can be coalesced in a single cycle"
)
icache = Param.RubyCache("")

2
src/mem/slicc/symbols/StateMachine.py
View File

@@ -184,7 +184,7 @@ class StateMachine(Symbol):
if type_ident == "%s_TBE" % self.ident:
if self.TBEType != None:
self.error(
"Multiple Transaction Buffer types in a " "single machine."
"Multiple Transaction Buffer types in a single machine."
)
self.TBEType = type

2
src/python/gem5/components/memory/dramsim_3.py
View File

@@ -53,7 +53,7 @@ def config_ds3(mem_type: str, num_chnls: int) -> Tuple[str, str]:
)
elif os.path.isfile(input_file):
raise Exception(
"The configuration file '" + input_file + "' cannot " " be found."
"The configuration file '" + input_file + "' cannot be found."
)
output_file = "/tmp/" + mem_type + "_chnls" + str(num_chnls) + ".ini"

4
src/python/m5/SimObject.py
View File

@@ -478,7 +478,7 @@ def cxxMethod(*args, **kwargs):
args, varargs, keywords, defaults = inspect.getargspec(func)
if varargs or keywords:
raise ValueError(
"Wrapped methods must not contain variable " "arguments"
"Wrapped methods must not contain variable arguments"
)
# Create tuples of (argument, default)
@@ -571,7 +571,7 @@ class SimObjectCliWrapper(object):
setattr(sim_object, key, val)
else:
raise SimObjectCliWrapperException(
"tried to set or unsettable" "object parameter: " + key
"tried to set or unsettableobject parameter: " + key
)
else:
raise SimObjectCliWrapperException(

2
src/python/m5/params.py
View File

@@ -1457,7 +1457,7 @@ class MetaEnum(MetaParamValue):
cls.map[val] = idx
else:
raise TypeError(
"Enum-derived class must define " "attribute 'map' or 'vals'"
"Enum-derived class must define attribute 'map' or 'vals'"
)
if cls.is_class:

4
src/sim/System.py
View File

@@ -77,7 +77,7 @@ class System(SimObject):
# mmap). By enabling this flag, we accommodate cases where a large
# (but sparse) memory is simulated.
mmap_using_noreserve = Param.Bool(
False, "mmap the backing store " "without reserving swap"
False, "mmap the backing store without reserving swap"
)
# The memory ranges are to be populated when creating the system
@@ -89,7 +89,7 @@ class System(SimObject):
# The ranges backed by a shadowed ROM
shadow_rom_ranges = VectorParam.AddrRange(
[], "Ranges backed by a " "shadowed ROM"
[], "Ranges backed by a shadowed ROM"
)
shared_backstore = Param.String(

4
src/systemc/tests/verify.py
View File

@@ -148,7 +148,7 @@ class RunPhase(TestPhaseBase):
"--timeout",
type=int,
metavar="SECONDS",
help="Time limit for each run in seconds, " "0 to disable.",
help="Time limit for each run in seconds, 0 to disable.",
default=60,
)
parser.add_argument(
@@ -604,7 +604,7 @@ filter_opts = parser.add_mutually_exclusive_group()
filter_opts.add_argument(
"--filter",
default="True",
help="Python expression which filters tests based " "on their properties",
help="Python expression which filters tests based on their properties",
)
filter_opts.add_argument(
"--filter-file",

4
tests/configs/gpu-randomtest-ruby.py
View File

@@ -57,7 +57,7 @@ parser.add_argument(
help="Number of GPU Command Processors (CP)",
)
parser.add_argument(
"--simds-per-cu", type=int, default=4, help="SIMD units" "per CU"
"--simds-per-cu", type=int, default=4, help="SIMD unitsper CU"
)
parser.add_argument(
"--wf-size", type=int, default=64, help="Wavefront size(in workitems)"
@@ -66,7 +66,7 @@ parser.add_argument(
"--wfs-per-simd",
type=int,
default=10,
help="Number of " "WF slots per SIMD",
help="Number of WF slots per SIMD",
)
# Add the ruby specific and protocol specific options

12
tests/configs/gpu-ruby.py
View File

@@ -79,13 +79,13 @@ parser.add_argument(
help="Number of GPU Command Processors (CP)",
)
parser.add_argument(
"--simds-per-cu", type=int, default=4, help="SIMD units" "per CU"
"--simds-per-cu", type=int, default=4, help="SIMD unitsper CU"
)
parser.add_argument(
"--cu-per-sqc",
type=int,
default=4,
help="number of CUs" "sharing an SQC (icache, and thus icache TLB)",
help="number of CUssharing an SQC (icache, and thus icache TLB)",
)
parser.add_argument(
"--wf-size", type=int, default=64, help="Wavefront size(in workitems)"
@@ -94,7 +94,7 @@ parser.add_argument(
"--wfs-per-simd",
type=int,
default=8,
help="Number of " "WF slots per SIMD",
help="Number of WF slots per SIMD",
)
parser.add_argument(
"--sp-bypass-path-length",
@@ -194,13 +194,11 @@ parser.add_argument(
action="store_true",
help="Count Page Accesses and output in per-CU output files",
)
parser.add_argument(
"--TLB-prefetch", type=int, help="prefetch depth for" "TLBs"
)
parser.add_argument("--TLB-prefetch", type=int, help="prefetch depth forTLBs")
parser.add_argument(
"--pf-type",
type=str,
help="type of prefetch: " "PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
)
parser.add_argument("--pf-stride", type=int, help="set prefetch stride")
parser.add_argument(

4
tests/gem5/fixture.py
View File

@@ -170,7 +170,7 @@ class SConsFixture(UniqueFixture):
)
else:
log.test_log.message(
"Building the following targets." " This may take a while."
"Building the following targets. This may take a while."
)
log.test_log.message("%s" % (", ".join(self.targets)))
log.test_log.message(
@@ -391,7 +391,7 @@ class DownloadedArchive(DownloadedProgram):
except (urllib.error.URLError, socket.timeout):
# Problem checking the server, use the old files.
log.test_log.debug(
"Could not contact server. " "Binaries may be old."
"Could not contact server. Binaries may be old."
)
return
# If the server version is more recent, download it

2
util/cpt_upgraders/isa-is-simobject.py
View File

@@ -94,7 +94,7 @@ def upgrader(cpt):
else:
if cpt.items(sec):
raise ValueError(
"Unexpected populated ISA section in old " "checkpoint"
"Unexpected populated ISA section in old checkpoint"
)
for (key, value) in options:

2
util/gerrit-bot/extract_gitcookies.py
View File

@@ -62,7 +62,7 @@ if __name__ == "__main__":
)
parser.add_argument(
"input",
help=("Path to a .gitcookies file or a file with " "a similar format"),
help=("Path to a .gitcookies file or a file with a similar format"),
)
parser.add_argument("output", help="Path to the output file")
args = parser.parse_args()

6
util/maint/list_changes.py
View File

@@ -179,14 +179,14 @@ def _main():
"-u",
type=str,
default="origin/master",
help="Upstream branch for comparison. " "Default: %(default)s",
help="Upstream branch for comparison. Default: %(default)s",
)
parser.add_argument(
"--feature",
"-f",
type=str,
default="HEAD",
help="Feature branch for comparison. " "Default: %(default)s",
help="Feature branch for comparison. Default: %(default)s",
)
parser.add_argument(
"--show-unknown",
@@ -199,7 +199,7 @@ def _main():
parser.add_argument(
"--deep-search",
action="store_true",
help="Use a deep search to find incorrectly " "rebased changes",
help="Use a deep search to find incorrectly rebased changes",
)
parser.add_argument(
"paths",

4
util/maint/show_changes_by_file.py
View File

@@ -95,14 +95,14 @@ def _main():
"-u",
type=str,
default="origin/master",
help="Upstream branch for comparison. " "Default: %(default)s",
help="Upstream branch for comparison. Default: %(default)s",
)
parser.add_argument(
"--feature",
"-f",
type=str,
default="HEAD",
help="Feature branch for comparison. " "Default: %(default)s",
help="Feature branch for comparison. Default: %(default)s",
)
parser.add_argument(
"paths",

2
util/plot_dram/dram_sweep_plot.py
View File

@@ -90,7 +90,7 @@ def main():
for line in simout:
match = re.match(
"DRAM sweep with " "burst: (\d+), banks: (\d+), max stride: (\d+)",
"DRAM sweep with burst: (\d+), banks: (\d+), max stride: (\d+)",
line,
)
if match: