eac06ad681
An example case,
```python
mem_side_port = RequestPort(
"This port sends requests and " "receives responses"
)
```
This is the residue of running the python formatter.
This is done by finding all tokens matching the regex `"\s"(?![.;"])`
and manually replacing them by empty strings.
Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66111
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
137 lines
5.7 KiB
Python
137 lines
5.7 KiB
Python
# Copyright (c) 2012, 2016, 2018, 2019 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.ClockedObject import ClockedObject
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# Types of Stream Generators.
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# Those are orthogonal to the other generators in the TrafficGen
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# and are meant to initialize the stream and substream IDs for
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# every memory request, regardless of how the packet has been
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# generated (Random, Linear, Trace etc)
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class StreamGenType(ScopedEnum):
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vals = ["none", "fixed", "random"]
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# The traffic generator is a requestor module that generates stimuli for
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# the memory system, based on a collection of simple behaviours that
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# are either probabilistic or based on traces. It can be used stand
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# alone for creating test cases for interconnect and memory
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# controllers, or function as a black-box replacement for system
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# components that are not yet modelled in detail, e.g. a video engine
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# or baseband subsystem in an SoC.
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class BaseTrafficGen(ClockedObject):
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type = "BaseTrafficGen"
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abstract = True
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cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
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cxx_class = "gem5::BaseTrafficGen"
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# Port used for sending requests and receiving responses
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port = RequestPort("This port sends requests and receives responses")
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# System used to determine the mode of the memory system
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system = Param.System(Parent.any, "System this generator is part of")
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# Should requests respond to back-pressure or not, if true, the
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# rate of the traffic generator will be slowed down if requests
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# are not immediately accepted
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elastic_req = Param.Bool(
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False, "Slow down requests in case of backpressure"
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)
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# Maximum number of requests waiting for response. Set to 0 for an
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# unlimited number of outstanding requests.
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max_outstanding_reqs = Param.Int(
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0, "Maximum number of outstanding requests"
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)
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# Let the user know if we have waited for a retry and not made any
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# progress for a long period of time. The default value is
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# somewhat arbitrary and may well have to be tuned.
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progress_check = Param.Latency(
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"1ms", "Time before exiting due to lack of progress"
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)
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# Generator type used for applying Stream and/or Substream IDs to requests
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stream_gen = Param.StreamGenType(
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"none", "Generator for adding Stream and/or Substream ID's to requests"
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)
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# Sources for Stream/Substream IDs to apply to requests
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sids = VectorParam.Unsigned([], "StreamIDs to use")
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ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
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# These additional parameters allow TrafficGen to be used with scripts
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# that expect a BaseCPU
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cpu_id = Param.Int(-1, "CPU identifier")
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socket_id = Param.Unsigned(0, "Physical Socket identifier")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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@classmethod
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def memory_mode(cls):
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return "timing"
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@classmethod
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def require_caches(cls):
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return False
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def createThreads(self):
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pass
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def createInterruptController(self):
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pass
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def connectCachedPorts(self, in_ports):
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if hasattr(self, "_cached_ports") and (len(self._cached_ports) > 0):
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for p in self._cached_ports:
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exec("self.%s = in_ports" % p)
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else:
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self.port = in_ports
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def connectAllPorts(self, cached_in, uncached_in, uncached_out):
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self.connectCachedPorts(cached_in)
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def connectBus(self, bus):
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self.connectAllPorts(
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bus.cpu_side_ports, bus.cpu_side_ports, bus.mem_side_ports
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)
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def addPrivateSplitL1Caches(self, ic, dc, iwc=None, dwc=None):
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self.dcache = dc
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self.port = dc.cpu_side
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self._cached_ports = ["dcache.mem_side"]
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self._uncached_ports = []
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