Gabe Black c0d380b4d7 arch: Simplify the VecElemOperand class. ...

Oddly, makeDecl would conditionally declare the operand, but only
because makeRead would also declare it. Instead, make makeRead work like
normal, and get rid of the custom makeDecl.

Change-Id: I26c6f01f971778ad5075f8d3f49d9816f371f5b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49722
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-03-02 23:41:31 +00:00

..

__init__.py

arch: Move the ISA parser into a package.

2020-10-12 04:28:18 +00:00

isa_parser.py

arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array.

2022-03-01 01:36:07 +00:00

operand_list.py

arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).

2022-03-01 01:36:07 +00:00

operand_types.py

arch: Simplify the VecElemOperand class.

2022-03-02 23:41:31 +00:00

util.py

arch: Pull the (Sub)OperandList classes into their own file.

2020-10-13 04:57:23 +00:00