arch: Pull the (Sub)OperandList classes into their own file.
Another step in breaking down the isa parser into more manageable parts. Change-Id: I0c5e70fe481bd17c0069b768129731e99a93ed0d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35816 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
@@ -45,6 +45,7 @@ import traceback
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from types import *
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from m5.util.grammar import Grammar
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from .operand_list import *
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from .operand_types import *
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from .util import *
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@@ -340,270 +341,6 @@ def makeList(arg):
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else:
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return [ arg ]
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class OperandList(object):
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'''Find all the operands in the given code block. Returns an operand
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descriptor list (instance of class OperandList).'''
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def __init__(self, parser, code):
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self.items = []
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self.bases = {}
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# delete strings and comments so we don't match on operands inside
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for regEx in (stringRE, commentRE):
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code = regEx.sub('', code)
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# search for operands
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next_pos = 0
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while 1:
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match = parser.operandsRE().search(code, next_pos)
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if not match:
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# no more matches: we're done
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break
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op = match.groups()
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# regexp groups are operand full name, base, and extension
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(op_full, op_base, op_ext) = op
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# If is a elem operand, define or update the corresponding
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# vector operand
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isElem = False
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if op_base in parser.elemToVector:
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isElem = True
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elem_op = (op_base, op_ext)
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op_base = parser.elemToVector[op_base]
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op_ext = '' # use the default one
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# if the token following the operand is an assignment, this is
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# a destination (LHS), else it's a source (RHS)
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is_dest = (assignRE.match(code, match.end()) != None)
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is_src = not is_dest
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# see if we've already seen this one
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op_desc = self.find_base(op_base)
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if op_desc:
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if op_ext and op_ext != '' and op_desc.ext != op_ext:
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error ('Inconsistent extensions for operand %s: %s - %s' \
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% (op_base, op_desc.ext, op_ext))
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op_desc.is_src = op_desc.is_src or is_src
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op_desc.is_dest = op_desc.is_dest or is_dest
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if isElem:
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(elem_base, elem_ext) = elem_op
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found = False
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for ae in op_desc.active_elems:
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(ae_base, ae_ext) = ae
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if ae_base == elem_base:
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if ae_ext != elem_ext:
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error('Inconsistent extensions for elem'
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' operand %s' % elem_base)
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else:
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found = True
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if not found:
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op_desc.active_elems.append(elem_op)
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else:
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# new operand: create new descriptor
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op_desc = parser.operandNameMap[op_base](parser,
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op_full, op_ext, is_src, is_dest)
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# if operand is a vector elem, add the corresponding vector
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# operand if not already done
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if isElem:
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op_desc.elemExt = elem_op[1]
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op_desc.active_elems = [elem_op]
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self.append(op_desc)
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# start next search after end of current match
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next_pos = match.end()
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self.sort()
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# enumerate source & dest register operands... used in building
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# constructor later
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self.numSrcRegs = 0
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self.numDestRegs = 0
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self.numFPDestRegs = 0
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self.numIntDestRegs = 0
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self.numVecDestRegs = 0
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self.numVecPredDestRegs = 0
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self.numCCDestRegs = 0
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self.numMiscDestRegs = 0
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self.memOperand = None
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# Flags to keep track if one or more operands are to be read/written
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# conditionally.
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self.predRead = False
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self.predWrite = False
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for op_desc in self.items:
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if op_desc.isReg():
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if op_desc.is_src:
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op_desc.src_reg_idx = self.numSrcRegs
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self.numSrcRegs += 1
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if op_desc.is_dest:
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op_desc.dest_reg_idx = self.numDestRegs
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self.numDestRegs += 1
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if op_desc.isFloatReg():
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self.numFPDestRegs += 1
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elif op_desc.isIntReg():
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self.numIntDestRegs += 1
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elif op_desc.isVecReg():
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self.numVecDestRegs += 1
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elif op_desc.isVecPredReg():
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self.numVecPredDestRegs += 1
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elif op_desc.isCCReg():
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self.numCCDestRegs += 1
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elif op_desc.isControlReg():
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self.numMiscDestRegs += 1
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elif op_desc.isMem():
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if self.memOperand:
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error("Code block has more than one memory operand.")
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self.memOperand = op_desc
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# Check if this operand has read/write predication. If true, then
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# the microop will dynamically index source/dest registers.
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self.predRead = self.predRead or op_desc.hasReadPred()
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self.predWrite = self.predWrite or op_desc.hasWritePred()
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if parser.maxInstSrcRegs < self.numSrcRegs:
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parser.maxInstSrcRegs = self.numSrcRegs
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if parser.maxInstDestRegs < self.numDestRegs:
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parser.maxInstDestRegs = self.numDestRegs
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if parser.maxMiscDestRegs < self.numMiscDestRegs:
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parser.maxMiscDestRegs = self.numMiscDestRegs
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# now make a final pass to finalize op_desc fields that may depend
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# on the register enumeration
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for op_desc in self.items:
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op_desc.finalize(self.predRead, self.predWrite)
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def __len__(self):
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return len(self.items)
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def __getitem__(self, index):
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return self.items[index]
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def append(self, op_desc):
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self.items.append(op_desc)
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self.bases[op_desc.base_name] = op_desc
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def find_base(self, base_name):
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# like self.bases[base_name], but returns None if not found
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# (rather than raising exception)
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return self.bases.get(base_name)
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# internal helper function for concat[Some]Attr{Strings|Lists}
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def __internalConcatAttrs(self, attr_name, filter, result):
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for op_desc in self.items:
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if filter(op_desc):
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result += getattr(op_desc, attr_name)
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return result
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# return a single string that is the concatenation of the (string)
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# values of the specified attribute for all operands
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def concatAttrStrings(self, attr_name):
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return self.__internalConcatAttrs(attr_name, lambda x: 1, '')
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# like concatAttrStrings, but only include the values for the operands
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# for which the provided filter function returns true
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def concatSomeAttrStrings(self, filter, attr_name):
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return self.__internalConcatAttrs(attr_name, filter, '')
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# return a single list that is the concatenation of the (list)
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# values of the specified attribute for all operands
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def concatAttrLists(self, attr_name):
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return self.__internalConcatAttrs(attr_name, lambda x: 1, [])
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# like concatAttrLists, but only include the values for the operands
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# for which the provided filter function returns true
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def concatSomeAttrLists(self, filter, attr_name):
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return self.__internalConcatAttrs(attr_name, filter, [])
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def sort(self):
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self.items.sort(key=lambda a: a.sort_pri)
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class SubOperandList(OperandList):
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'''Find all the operands in the given code block. Returns an operand
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descriptor list (instance of class OperandList).'''
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def __init__(self, parser, code, requestor_list):
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self.items = []
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self.bases = {}
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# delete strings and comments so we don't match on operands inside
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for regEx in (stringRE, commentRE):
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code = regEx.sub('', code)
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# search for operands
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next_pos = 0
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while 1:
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match = parser.operandsRE().search(code, next_pos)
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if not match:
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# no more matches: we're done
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break
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op = match.groups()
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# regexp groups are operand full name, base, and extension
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(op_full, op_base, op_ext) = op
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# If is a elem operand, define or update the corresponding
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# vector operand
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if op_base in parser.elemToVector:
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elem_op = op_base
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op_base = parser.elemToVector[elem_op]
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# find this op in the requestor list
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op_desc = requestor_list.find_base(op_base)
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if not op_desc:
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error('Found operand %s which is not in the requestor list!'
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% op_base)
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else:
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# See if we've already found this operand
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op_desc = self.find_base(op_base)
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if not op_desc:
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# if not, add a reference to it to this sub list
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self.append(requestor_list.bases[op_base])
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# start next search after end of current match
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next_pos = match.end()
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self.sort()
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self.memOperand = None
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# Whether the whole PC needs to be read so parts of it can be accessed
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self.readPC = False
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# Whether the whole PC needs to be written after parts of it were
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# changed
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self.setPC = False
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# Whether this instruction manipulates the whole PC or parts of it.
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# Mixing the two is a bad idea and flagged as an error.
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self.pcPart = None
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# Flags to keep track if one or more operands are to be read/written
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# conditionally.
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self.predRead = False
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self.predWrite = False
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for op_desc in self.items:
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if op_desc.isPCPart():
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self.readPC = True
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if op_desc.is_dest:
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self.setPC = True
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if op_desc.isPCState():
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if self.pcPart is not None:
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if self.pcPart and not op_desc.isPCPart() or \
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not self.pcPart and op_desc.isPCPart():
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error("Mixed whole and partial PC state operands.")
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self.pcPart = op_desc.isPCPart()
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if op_desc.isMem():
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if self.memOperand:
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error("Code block has more than one memory operand.")
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self.memOperand = op_desc
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# Check if this operand has read/write predication. If true, then
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# the microop will dynamically index source/dest registers.
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self.predRead = self.predRead or op_desc.hasReadPred()
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self.predWrite = self.predWrite or op_desc.hasWritePred()
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# Regular expression object to match C++ strings
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stringRE = re.compile(r'"([^"\\]|\\.)*"')
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# Regular expression object to match C++ comments
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# (used in findOperands())
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commentRE = re.compile(r'(^)?[^\S\n]*/(?:\*(.*?)\*/[^\S\n]*|/[^\n]*)($)?',
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re.DOTALL | re.MULTILINE)
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# Regular expression object to match assignment statements (used in
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# findOperands()). If the code immediately following the first
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# appearance of the operand matches this regex, then the operand
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# appears to be on the LHS of an assignment, and is thus a
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# destination. basically we're looking for an '=' that's not '=='.
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# The heinous tangle before that handles the case where the operand
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# has an array subscript.
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assignRE = re.compile(r'(\[[^\]]+\])?\s*=(?!=)', re.MULTILINE)
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def makeFlagConstructor(flag_list):
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if len(flag_list) == 0:
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return ''
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288
src/arch/isa_parser/operand_list.py
Executable file
288
src/arch/isa_parser/operand_list.py
Executable file
@@ -0,0 +1,288 @@
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# Copyright (c) 2014, 2016, 2018-2019 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2003-2005 The Regents of The University of Michigan
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# Copyright (c) 2013,2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
|
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# redistributions in binary form must reproduce the above copyright
|
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
|
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from .util import assignRE, commentRE, stringRE
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from .util import error
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class OperandList(object):
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'''Find all the operands in the given code block. Returns an operand
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descriptor list (instance of class OperandList).'''
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def __init__(self, parser, code):
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self.items = []
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self.bases = {}
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# delete strings and comments so we don't match on operands inside
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for regEx in (stringRE, commentRE):
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code = regEx.sub('', code)
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# search for operands
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next_pos = 0
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while 1:
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match = parser.operandsRE().search(code, next_pos)
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if not match:
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# no more matches: we're done
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break
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op = match.groups()
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# regexp groups are operand full name, base, and extension
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(op_full, op_base, op_ext) = op
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# If is a elem operand, define or update the corresponding
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# vector operand
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isElem = False
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if op_base in parser.elemToVector:
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isElem = True
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elem_op = (op_base, op_ext)
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op_base = parser.elemToVector[op_base]
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op_ext = '' # use the default one
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# if the token following the operand is an assignment, this is
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# a destination (LHS), else it's a source (RHS)
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is_dest = (assignRE.match(code, match.end()) != None)
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is_src = not is_dest
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# see if we've already seen this one
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op_desc = self.find_base(op_base)
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if op_desc:
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if op_ext and op_ext != '' and op_desc.ext != op_ext:
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error ('Inconsistent extensions for operand %s: %s - %s' \
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% (op_base, op_desc.ext, op_ext))
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op_desc.is_src = op_desc.is_src or is_src
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op_desc.is_dest = op_desc.is_dest or is_dest
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if isElem:
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(elem_base, elem_ext) = elem_op
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found = False
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for ae in op_desc.active_elems:
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(ae_base, ae_ext) = ae
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if ae_base == elem_base:
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if ae_ext != elem_ext:
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error('Inconsistent extensions for elem'
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' operand %s' % elem_base)
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else:
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found = True
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if not found:
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op_desc.active_elems.append(elem_op)
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else:
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# new operand: create new descriptor
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op_desc = parser.operandNameMap[op_base](parser,
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op_full, op_ext, is_src, is_dest)
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# if operand is a vector elem, add the corresponding vector
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# operand if not already done
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if isElem:
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op_desc.elemExt = elem_op[1]
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op_desc.active_elems = [elem_op]
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self.append(op_desc)
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# start next search after end of current match
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next_pos = match.end()
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self.sort()
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# enumerate source & dest register operands... used in building
|
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# constructor later
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self.numSrcRegs = 0
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self.numDestRegs = 0
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self.numFPDestRegs = 0
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self.numIntDestRegs = 0
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self.numVecDestRegs = 0
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self.numVecPredDestRegs = 0
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self.numCCDestRegs = 0
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self.numMiscDestRegs = 0
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self.memOperand = None
|
||||
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# Flags to keep track if one or more operands are to be read/written
|
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# conditionally.
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self.predRead = False
|
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self.predWrite = False
|
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for op_desc in self.items:
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if op_desc.isReg():
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if op_desc.is_src:
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op_desc.src_reg_idx = self.numSrcRegs
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self.numSrcRegs += 1
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if op_desc.is_dest:
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op_desc.dest_reg_idx = self.numDestRegs
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self.numDestRegs += 1
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if op_desc.isFloatReg():
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self.numFPDestRegs += 1
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elif op_desc.isIntReg():
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self.numIntDestRegs += 1
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elif op_desc.isVecReg():
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self.numVecDestRegs += 1
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elif op_desc.isVecPredReg():
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self.numVecPredDestRegs += 1
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elif op_desc.isCCReg():
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self.numCCDestRegs += 1
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elif op_desc.isControlReg():
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self.numMiscDestRegs += 1
|
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elif op_desc.isMem():
|
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if self.memOperand:
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error("Code block has more than one memory operand.")
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self.memOperand = op_desc
|
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|
||||
# Check if this operand has read/write predication. If true, then
|
||||
# the microop will dynamically index source/dest registers.
|
||||
self.predRead = self.predRead or op_desc.hasReadPred()
|
||||
self.predWrite = self.predWrite or op_desc.hasWritePred()
|
||||
|
||||
if parser.maxInstSrcRegs < self.numSrcRegs:
|
||||
parser.maxInstSrcRegs = self.numSrcRegs
|
||||
if parser.maxInstDestRegs < self.numDestRegs:
|
||||
parser.maxInstDestRegs = self.numDestRegs
|
||||
if parser.maxMiscDestRegs < self.numMiscDestRegs:
|
||||
parser.maxMiscDestRegs = self.numMiscDestRegs
|
||||
|
||||
# now make a final pass to finalize op_desc fields that may depend
|
||||
# on the register enumeration
|
||||
for op_desc in self.items:
|
||||
op_desc.finalize(self.predRead, self.predWrite)
|
||||
|
||||
def __len__(self):
|
||||
return len(self.items)
|
||||
|
||||
def __getitem__(self, index):
|
||||
return self.items[index]
|
||||
|
||||
def append(self, op_desc):
|
||||
self.items.append(op_desc)
|
||||
self.bases[op_desc.base_name] = op_desc
|
||||
|
||||
def find_base(self, base_name):
|
||||
# like self.bases[base_name], but returns None if not found
|
||||
# (rather than raising exception)
|
||||
return self.bases.get(base_name)
|
||||
|
||||
# internal helper function for concat[Some]Attr{Strings|Lists}
|
||||
def __internalConcatAttrs(self, attr_name, filter, result):
|
||||
for op_desc in self.items:
|
||||
if filter(op_desc):
|
||||
result += getattr(op_desc, attr_name)
|
||||
return result
|
||||
|
||||
# return a single string that is the concatenation of the (string)
|
||||
# values of the specified attribute for all operands
|
||||
def concatAttrStrings(self, attr_name):
|
||||
return self.__internalConcatAttrs(attr_name, lambda x: 1, '')
|
||||
|
||||
# like concatAttrStrings, but only include the values for the operands
|
||||
# for which the provided filter function returns true
|
||||
def concatSomeAttrStrings(self, filter, attr_name):
|
||||
return self.__internalConcatAttrs(attr_name, filter, '')
|
||||
|
||||
# return a single list that is the concatenation of the (list)
|
||||
# values of the specified attribute for all operands
|
||||
def concatAttrLists(self, attr_name):
|
||||
return self.__internalConcatAttrs(attr_name, lambda x: 1, [])
|
||||
|
||||
# like concatAttrLists, but only include the values for the operands
|
||||
# for which the provided filter function returns true
|
||||
def concatSomeAttrLists(self, filter, attr_name):
|
||||
return self.__internalConcatAttrs(attr_name, filter, [])
|
||||
|
||||
def sort(self):
|
||||
self.items.sort(key=lambda a: a.sort_pri)
|
||||
|
||||
class SubOperandList(OperandList):
|
||||
'''Find all the operands in the given code block. Returns an operand
|
||||
descriptor list (instance of class OperandList).'''
|
||||
def __init__(self, parser, code, requestor_list):
|
||||
self.items = []
|
||||
self.bases = {}
|
||||
# delete strings and comments so we don't match on operands inside
|
||||
for regEx in (stringRE, commentRE):
|
||||
code = regEx.sub('', code)
|
||||
# search for operands
|
||||
next_pos = 0
|
||||
while 1:
|
||||
match = parser.operandsRE().search(code, next_pos)
|
||||
if not match:
|
||||
# no more matches: we're done
|
||||
break
|
||||
op = match.groups()
|
||||
# regexp groups are operand full name, base, and extension
|
||||
(op_full, op_base, op_ext) = op
|
||||
# If is a elem operand, define or update the corresponding
|
||||
# vector operand
|
||||
if op_base in parser.elemToVector:
|
||||
elem_op = op_base
|
||||
op_base = parser.elemToVector[elem_op]
|
||||
# find this op in the requestor list
|
||||
op_desc = requestor_list.find_base(op_base)
|
||||
if not op_desc:
|
||||
error('Found operand %s which is not in the requestor list!'
|
||||
% op_base)
|
||||
else:
|
||||
# See if we've already found this operand
|
||||
op_desc = self.find_base(op_base)
|
||||
if not op_desc:
|
||||
# if not, add a reference to it to this sub list
|
||||
self.append(requestor_list.bases[op_base])
|
||||
|
||||
# start next search after end of current match
|
||||
next_pos = match.end()
|
||||
self.sort()
|
||||
self.memOperand = None
|
||||
# Whether the whole PC needs to be read so parts of it can be accessed
|
||||
self.readPC = False
|
||||
# Whether the whole PC needs to be written after parts of it were
|
||||
# changed
|
||||
self.setPC = False
|
||||
# Whether this instruction manipulates the whole PC or parts of it.
|
||||
# Mixing the two is a bad idea and flagged as an error.
|
||||
self.pcPart = None
|
||||
|
||||
# Flags to keep track if one or more operands are to be read/written
|
||||
# conditionally.
|
||||
self.predRead = False
|
||||
self.predWrite = False
|
||||
|
||||
for op_desc in self.items:
|
||||
if op_desc.isPCPart():
|
||||
self.readPC = True
|
||||
if op_desc.is_dest:
|
||||
self.setPC = True
|
||||
|
||||
if op_desc.isPCState():
|
||||
if self.pcPart is not None:
|
||||
if self.pcPart and not op_desc.isPCPart() or \
|
||||
not self.pcPart and op_desc.isPCPart():
|
||||
error("Mixed whole and partial PC state operands.")
|
||||
self.pcPart = op_desc.isPCPart()
|
||||
|
||||
if op_desc.isMem():
|
||||
if self.memOperand:
|
||||
error("Code block has more than one memory operand.")
|
||||
self.memOperand = op_desc
|
||||
|
||||
# Check if this operand has read/write predication. If true, then
|
||||
# the microop will dynamically index source/dest registers.
|
||||
self.predRead = self.predRead or op_desc.hasReadPred()
|
||||
self.predWrite = self.predWrite or op_desc.hasWritePred()
|
||||
@@ -50,6 +50,23 @@ import re
|
||||
def indent(s):
|
||||
return re.sub(r'(?m)^(?!#)', ' ', s)
|
||||
|
||||
# Regular expression object to match C++ strings
|
||||
stringRE = re.compile(r'"([^"\\]|\\.)*"')
|
||||
|
||||
# Regular expression object to match C++ comments
|
||||
# (used in findOperands())
|
||||
commentRE = re.compile(r'(^)?[^\S\n]*/(?:\*(.*?)\*/[^\S\n]*|/[^\n]*)($)?',
|
||||
re.DOTALL | re.MULTILINE)
|
||||
|
||||
# Regular expression object to match assignment statements (used in
|
||||
# findOperands()). If the code immediately following the first
|
||||
# appearance of the operand matches this regex, then the operand
|
||||
# appears to be on the LHS of an assignment, and is thus a
|
||||
# destination. basically we're looking for an '=' that's not '=='.
|
||||
# The heinous tangle before that handles the case where the operand
|
||||
# has an array subscript.
|
||||
assignRE = re.compile(r'(\[[^\]]+\])?\s*=(?!=)', re.MULTILINE)
|
||||
|
||||
#
|
||||
# Munge a somewhat arbitrarily formatted piece of Python code
|
||||
# (e.g. from a format 'let' block) into something whose indentation
|
||||
|
||||
Reference in New Issue
Block a user