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misc: Use python f-strings for string formatting

Browse Source 
This patch has been generated by applying flynt to the
gem5 repo (ext has been excluded)

JIRA: https://gem5.atlassian.net/browse/GEM5-831

Change-Id: I0935db6223d5426b99515959bde78e374cbadb04
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Giacomo Travaglini
2023-03-15 13:34:46 +00:00
parent 07fca546e6
commit e73655d038
242 changed files with 814 additions and 1002 deletions
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6
configs/common/CacheConfig.py
View File

@@ -60,15 +60,15 @@ def _get_hwp(hwp_option):
def _get_cache_opts(level, options):
opts = {}
size_attr = "{}_size".format(level)
size_attr = f"{level}_size"
if hasattr(options, size_attr):
opts["size"] = getattr(options, size_attr)
assoc_attr = "{}_assoc".format(level)
assoc_attr = f"{level}_assoc"
if hasattr(options, assoc_attr):
opts["assoc"] = getattr(options, assoc_attr)
prefetcher_attr = "{}_hwp_type".format(level)
prefetcher_attr = f"{level}_hwp_type"
if hasattr(options, prefetcher_attr):
opts["prefetcher"] = _get_hwp(getattr(options, prefetcher_attr))

10
configs/common/FileSystemConfig.py
View File

@@ -51,7 +51,7 @@ from shutil import rmtree, copyfile
def hex_mask(terms):
dec_mask = reduce(operator.or_, [2**i for i in terms], 0)
return "%08x" % dec_mask
return f"{dec_mask:08x}"
def file_append(path, contents):
@@ -252,13 +252,13 @@ def _redirect_paths(options):
# Redirect filesystem syscalls from src to the first matching dests
redirect_paths = [
RedirectPath(
app_path="/proc", host_paths=["%s/fs/proc" % m5.options.outdir]
app_path="/proc", host_paths=[f"{m5.options.outdir}/fs/proc"]
),
RedirectPath(
app_path="/sys", host_paths=["%s/fs/sys" % m5.options.outdir]
app_path="/sys", host_paths=[f"{m5.options.outdir}/fs/sys"]
),
RedirectPath(
app_path="/tmp", host_paths=["%s/fs/tmp" % m5.options.outdir]
app_path="/tmp", host_paths=[f"{m5.options.outdir}/fs/tmp"]
),
]
@@ -275,7 +275,7 @@ def _redirect_paths(options):
if chroot:
redirect_paths.append(
RedirectPath(
app_path="/", host_paths=["%s" % os.path.expanduser(chroot)]
app_path="/", host_paths=[f"{os.path.expanduser(chroot)}"]
)
)

4
configs/common/GPUTLBConfig.py
View File

@@ -204,8 +204,8 @@ def config_tlb_hierarchy(
# add the different TLB levels to the system
# Modify here if you want to make the TLB hierarchy a child of
# the shader.
exec("system.%s = TLB_array" % system_TLB_name)
exec("system.%s = Coalescer_array" % system_Coalescer_name)
exec(f"system.{system_TLB_name} = TLB_array")
exec(f"system.{system_Coalescer_name} = Coalescer_array")
# ===========================================================
# Specify the TLB hierarchy (i.e., port connections)

12
configs/common/ObjectList.py
View File

@@ -65,22 +65,18 @@ class ObjectList(object):
sub_cls = self._sub_classes[real_name]
return sub_cls
except KeyError:
print(
"{} is not a valid sub-class of {}.".format(
name, self.base_cls
)
)
print(f"{name} is not a valid sub-class of {self.base_cls}.")
raise
def print(self):
"""Print a list of available sub-classes and aliases."""
print("Available {} classes:".format(self.base_cls))
print(f"Available {self.base_cls} classes:")
doc_wrapper = TextWrapper(
initial_indent="\t\t", subsequent_indent="\t\t"
)
for name, cls in list(self._sub_classes.items()):
print("\t{}".format(name))
print(f"\t{name}")
# Try to extract the class documentation from the class help
# string.
@@ -92,7 +88,7 @@ class ObjectList(object):
if self._aliases:
print("\Aliases:")
for alias, target in list(self._aliases.items()):
print("\t{} => {}".format(alias, target))
print(f"\t{alias} => {target}")
def get_names(self):
"""Return a list of valid sub-class names and aliases."""

3
configs/common/Options.py
View File

@@ -834,8 +834,7 @@ def addFSOptions(parser):
action="store",
type=str,
dest="benchmark",
help="Specify the benchmark to run. Available benchmarks: %s"
% DefinedBenchmarks,
help=f"Specify the benchmark to run. Available benchmarks: {DefinedBenchmarks}",
)
# Metafile options

18
configs/common/Simulation.py
View File

@@ -71,7 +71,7 @@ def setCPUClass(options):
TmpClass, test_mem_mode = getCPUClass(options.cpu_type)
CPUClass = None
if TmpClass.require_caches() and not options.caches and not options.ruby:
fatal("%s must be used with caches" % options.cpu_type)
fatal(f"{options.cpu_type} must be used with caches")
if options.checkpoint_restore != None:
if options.restore_with_cpu != options.cpu_type:
@@ -144,7 +144,7 @@ def findCptDir(options, cptdir, testsys):
fatal("Unable to find simpoint")
inst += int(testsys.cpu[0].workload[0].simpoint)
checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst))
checkpoint_dir = joinpath(cptdir, f"cpt.{options.bench}.{inst}")
if not exists(checkpoint_dir):
fatal("Unable to find checkpoint directory %s", checkpoint_dir)
@@ -204,7 +204,7 @@ def findCptDir(options, cptdir, testsys):
fatal("Checkpoint %d not found", cpt_num)
cpt_starttick = int(cpts[cpt_num - 1])
checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])
checkpoint_dir = joinpath(cptdir, f"cpt.{cpts[cpt_num - 1]}")
return cpt_starttick, checkpoint_dir
@@ -220,7 +220,7 @@ def scriptCheckpoints(options, maxtick, cptdir):
print("Creating checkpoint at inst:%d" % (checkpoint_inst))
exit_event = m5.simulate()
exit_cause = exit_event.getCause()
print("exit cause = %s" % exit_cause)
print(f"exit cause = {exit_cause}")
# skip checkpoint instructions should they exist
while exit_cause == "checkpoint":
@@ -549,10 +549,10 @@ def run(options, root, testsys, cpu_class):
if options.repeat_switch:
switch_class = getCPUClass(options.cpu_type)[0]
if switch_class.require_caches() and not options.caches:
print("%s: Must be used with caches" % str(switch_class))
print(f"{str(switch_class)}: Must be used with caches")
sys.exit(1)
if not switch_class.support_take_over():
print("%s: CPU switching not supported" % str(switch_class))
print(f"{str(switch_class)}: CPU switching not supported")
sys.exit(1)
repeat_switch_cpus = [
@@ -740,9 +740,9 @@ def run(options, root, testsys, cpu_class):
)
exit_event = m5.simulate()
else:
print("Switch at curTick count:%s" % str(10000))
print(f"Switch at curTick count:{str(10000)}")
exit_event = m5.simulate(10000)
print("Switched CPUS @ tick %s" % (m5.curTick()))
print(f"Switched CPUS @ tick {m5.curTick()}")
m5.switchCpus(testsys, switch_cpu_list)
@@ -757,7 +757,7 @@ def run(options, root, testsys, cpu_class):
exit_event = m5.simulate()
else:
exit_event = m5.simulate(options.standard_switch)
print("Switching CPUS @ tick %s" % (m5.curTick()))
print(f"Switching CPUS @ tick {m5.curTick()}")
print(
"Simulation ends instruction count:%d"
% (testsys.switch_cpus_1[0].max_insts_any_thread)

4
configs/common/SysPaths.py
View File

@@ -73,9 +73,7 @@ class PathSearchFunc(object):
return next(p for p in paths if os.path.exists(p))
except StopIteration:
raise IOError(
"Can't find file '{}' on {}.".format(
filepath, self.environment_variable
)
f"Can't find file '{filepath}' on {self.environment_variable}."
)

39
configs/common/cpu2000.py
View File

@@ -83,7 +83,7 @@ class Benchmark(object):
self.args = []
if not hasattr(self.__class__, "output"):
self.output = "%s.out" % self.name
self.output = f"{self.name}.out"
if not hasattr(self.__class__, "simpoint"):
self.simpoint = None
@@ -92,13 +92,12 @@ class Benchmark(object):
func = getattr(self.__class__, input_set)
except AttributeError:
raise AttributeError(
"The benchmark %s does not have the %s input set"
% (self.name, input_set)
f"The benchmark {self.name} does not have the {input_set} input set"
)
executable = joinpath(spec_dist, "binaries", isa, os, self.binary)
if not isfile(executable):
raise AttributeError("%s not found" % executable)
raise AttributeError(f"{executable} not found")
self.executable = executable
# root of tree for input & output data files
@@ -112,7 +111,7 @@ class Benchmark(object):
self.input_set = input_set
if not isdir(inputs_dir):
raise AttributeError("%s not found" % inputs_dir)
raise AttributeError(f"{inputs_dir} not found")
self.inputs_dir = [inputs_dir]
if isdir(all_dir):
@@ -121,12 +120,12 @@ class Benchmark(object):
self.outputs_dir = outputs_dir
if not hasattr(self.__class__, "stdin"):
self.stdin = joinpath(inputs_dir, "%s.in" % self.name)
self.stdin = joinpath(inputs_dir, f"{self.name}.in")
if not isfile(self.stdin):
self.stdin = None
if not hasattr(self.__class__, "stdout"):
self.stdout = joinpath(outputs_dir, "%s.out" % self.name)
self.stdout = joinpath(outputs_dir, f"{self.name}.out")
if not isfile(self.stdout):
self.stdout = None
@@ -387,9 +386,9 @@ class mesa(Benchmark):
"-frames",
frames,
"-meshfile",
"%s.in" % self.name,
f"{self.name}.in",
"-ppmfile",
"%s.ppm" % self.name,
f"{self.name}.ppm",
]
def test(self, isa, os):
@@ -876,34 +875,34 @@ class vortex(Benchmark):
elif isa == "sparc" or isa == "sparc32":
self.endian = "bendian"
else:
raise AttributeError("unknown ISA %s" % isa)
raise AttributeError(f"unknown ISA {isa}")
super(vortex, self).__init__(isa, os, input_set)
def test(self, isa, os):
self.args = ["%s.raw" % self.endian]
self.args = [f"{self.endian}.raw"]
self.output = "vortex.out"
def train(self, isa, os):
self.args = ["%s.raw" % self.endian]
self.args = [f"{self.endian}.raw"]
self.output = "vortex.out"
def smred(self, isa, os):
self.args = ["%s.raw" % self.endian]
self.args = [f"{self.endian}.raw"]
self.output = "vortex.out"
def mdred(self, isa, os):
self.args = ["%s.raw" % self.endian]
self.args = [f"{self.endian}.raw"]
self.output = "vortex.out"
def lgred(self, isa, os):
self.args = ["%s.raw" % self.endian]
self.args = [f"{self.endian}.raw"]
self.output = "vortex.out"
class vortex1(vortex):
def ref(self, isa, os):
self.args = ["%s1.raw" % self.endian]
self.args = [f"{self.endian}1.raw"]
self.output = "vortex1.out"
self.simpoint = 271 * 100e6
@@ -911,14 +910,14 @@ class vortex1(vortex):
class vortex2(vortex):
def ref(self, isa, os):
self.simpoint = 1024 * 100e6
self.args = ["%s2.raw" % self.endian]
self.args = [f"{self.endian}2.raw"]
self.output = "vortex2.out"
class vortex3(vortex):
def ref(self, isa, os):
self.simpoint = 564 * 100e6
self.args = ["%s3.raw" % self.endian]
self.args = [f"{self.endian}3.raw"]
self.output = "vortex3.out"
@@ -1031,8 +1030,8 @@ if __name__ == "__main__":
for bench in all:
for input_set in "ref", "test", "train":
print("class: %s" % bench.__name__)
print(f"class: {bench.__name__}")
x = bench("x86", "linux", input_set)
print("%s: %s" % (x, input_set))
print(f"{x}: {input_set}")
pprint(x.makeProcessArgs())
print()

6
configs/deprecated/example/fs.py
View File

@@ -347,8 +347,8 @@ if args.benchmark:
try:
bm = Benchmarks[args.benchmark]
except KeyError:
print("Error benchmark %s has not been defined." % args.benchmark)
print("Valid benchmarks are: %s" % DefinedBenchmarks)
print(f"Error benchmark {args.benchmark} has not been defined.")
print(f"Valid benchmarks are: {DefinedBenchmarks}")
sys.exit(1)
else:
if args.dual:
@@ -433,7 +433,7 @@ if buildEnv["USE_ARM_ISA"] and not args.bare_metal and not args.dtb_filename:
if hasattr(root, sysname):
sys = getattr(root, sysname)
sys.workload.dtb_filename = os.path.join(
m5.options.outdir, "%s.dtb" % sysname
m5.options.outdir, f"{sysname}.dtb"
)
sys.generateDtb(sys.workload.dtb_filename)

3
configs/deprecated/example/se.py
View File

@@ -159,8 +159,7 @@ if args.bench:
multiprocesses.append(workload.makeProcess())
except:
print(
"Unable to find workload for %s: %s"
% (get_runtime_isa().name(), app),
f"Unable to find workload for {get_runtime_isa().name()}: {app}",
file=sys.stderr,
)
sys.exit(1)

18
configs/example/apu_se.py
View File

@@ -683,7 +683,7 @@ def find_path(base_list, rel_path, test):
full_path = os.path.join(base, rel_path)
if test(full_path):
return full_path
fatal("%s not found in %s" % (rel_path, base_list))
fatal(f"{rel_path} not found in {base_list}")
def find_file(base_list, rel_path):
@@ -717,7 +717,7 @@ else:
"/usr/lib/x86_64-linux-gnu",
]
),
"HOME=%s" % os.getenv("HOME", "/"),
f"HOME={os.getenv('HOME', '/')}",
# Disable the VM fault handler signal creation for dGPUs also
# forces the use of DefaultSignals instead of driver-controlled
# InteruptSignals throughout the runtime. DefaultSignals poll
@@ -922,14 +922,10 @@ else:
redirect_paths = [
RedirectPath(
app_path="/proc", host_paths=["%s/fs/proc" % m5.options.outdir]
),
RedirectPath(
app_path="/sys", host_paths=["%s/fs/sys" % m5.options.outdir]
),
RedirectPath(
app_path="/tmp", host_paths=["%s/fs/tmp" % m5.options.outdir]
app_path="/proc", host_paths=[f"{m5.options.outdir}/fs/proc"]
),
RedirectPath(app_path="/sys", host_paths=[f"{m5.options.outdir}/fs/sys"]),
RedirectPath(app_path="/tmp", host_paths=[f"{m5.options.outdir}/fs/tmp"]),
]
system.redirect_paths = redirect_paths
@@ -981,7 +977,7 @@ exit_event = m5.simulate(maxtick)
if args.fast_forward:
if exit_event.getCause() == "a thread reached the max instruction count":
m5.switchCpus(system, switch_cpu_list)
print("Switched CPUS @ tick %s" % (m5.curTick()))
print(f"Switched CPUS @ tick {m5.curTick()}")
m5.stats.reset()
exit_event = m5.simulate(maxtick - m5.curTick())
elif args.fast_forward_pseudo_op:
@@ -992,7 +988,7 @@ elif args.fast_forward_pseudo_op:
print("Dumping stats...")
m5.stats.dump()
m5.switchCpus(system, switch_cpu_list)
print("Switched CPUS @ tick %s" % (m5.curTick()))
print(f"Switched CPUS @ tick {m5.curTick()}")
m5.stats.reset()
# This lets us switch back and forth without keeping a counter
switch_cpu_list = [(x[1], x[0]) for x in switch_cpu_list]

4
configs/example/arm/baremetal.py
View File

@@ -77,7 +77,7 @@ def create(args):
"""Create and configure the system object."""
if args.readfile and not os.path.isfile(args.readfile):
print("Error: Bootscript %s does not exist" % args.readfile)
print(f"Error: Bootscript {args.readfile} does not exist")
sys.exit(1)
object_file = args.kernel if args.kernel else ""
@@ -149,7 +149,7 @@ def create(args):
def run(args):
cptdir = m5.options.outdir
if args.checkpoint:
print("Checkpoint directory: %s" % cptdir)
print(f"Checkpoint directory: {cptdir}")
while True:
event = m5.simulate()

6
configs/example/arm/fs_bigLITTLE.py
View File

@@ -331,10 +331,10 @@ def build(options):
"lpj=19988480",
"norandmaps",
"loglevel=8",
"mem=%s" % options.mem_size,
"root=%s" % options.root,
f"mem={options.mem_size}",
f"root={options.root}",
"rw",
"init=%s" % options.kernel_init,
f"init={options.kernel_init}",
"vmalloc=768MB",
]

2
configs/example/arm/fs_power.py
View File

@@ -79,7 +79,7 @@ class L2PowerOn(MathExprPowerModel):
# Example to report l2 Cache overallAccesses
# The estimated power is converted to Watt and will vary based
# on the size of the cache
self.dyn = "{}.overallAccesses * 0.000018000".format(l2_path)
self.dyn = f"{l2_path}.overallAccesses * 0.000018000"
self.st = "(voltage * 3)/10"

12
configs/example/arm/ruby_fs.py
View File

@@ -100,7 +100,7 @@ def create(args):
"""Create and configure the system object."""
if args.script and not os.path.isfile(args.script):
print("Error: Bootscript %s does not exist" % args.script)
print(f"Error: Bootscript {args.script} does not exist")
sys.exit(1)
cpu_class = cpu_types[args.cpu]
@@ -171,11 +171,11 @@ def create(args):
# memory layout.
"norandmaps",
# Tell Linux where to find the root disk image.
"root=%s" % args.root_device,
f"root={args.root_device}",
# Mount the root disk read-write by default.
"rw",
# Tell Linux about the amount of physical memory present.
"mem=%s" % args.mem_size,
f"mem={args.mem_size}",
]
system.workload.command_line = " ".join(kernel_cmd)
@@ -185,7 +185,7 @@ def create(args):
def run(args):
cptdir = m5.options.outdir
if args.checkpoint:
print("Checkpoint directory: %s" % cptdir)
print(f"Checkpoint directory: {cptdir}")
while True:
event = m5.simulate()
@@ -221,9 +221,7 @@ def main():
"--root-device",
type=str,
default=default_root_device,
help="OS device name for root partition (default: {})".format(
default_root_device
),
help=f"OS device name for root partition (default: {default_root_device})",
)
parser.add_argument(
"--script", type=str, default="", help="Linux bootscript"

12
configs/example/arm/starter_fs.py
View File

@@ -88,7 +88,7 @@ def create(args):
"""Create and configure the system object."""
if args.script and not os.path.isfile(args.script):
print("Error: Bootscript %s does not exist" % args.script)
print(f"Error: Bootscript {args.script} does not exist")
sys.exit(1)
cpu_class = cpu_types[args.cpu][0]
@@ -163,11 +163,11 @@ def create(args):
# memory layout.
"norandmaps",
# Tell Linux where to find the root disk image.
"root=%s" % args.root_device,
f"root={args.root_device}",
# Mount the root disk read-write by default.
"rw",
# Tell Linux about the amount of physical memory present.
"mem=%s" % args.mem_size,
f"mem={args.mem_size}",
]
system.workload.command_line = " ".join(kernel_cmd)
@@ -177,7 +177,7 @@ def create(args):
def run(args):
cptdir = m5.options.outdir
if args.checkpoint:
print("Checkpoint directory: %s" % cptdir)
print(f"Checkpoint directory: {cptdir}")
while True:
event = m5.simulate()
@@ -219,9 +219,7 @@ def main():
"--root-device",
type=str,
default=default_root_device,
help="OS device name for root partition (default: {})".format(
default_root_device
),
help=f"OS device name for root partition (default: {default_root_device})",
)
parser.add_argument(
"--script", type=str, default="", help="Linux bootscript"

8
configs/example/gem5_library/x86-gapbs-benchmarks.py
View File

@@ -195,9 +195,9 @@ if args.synthetic == "1":
)
exit(-1)
command = "./{} -g {}\n".format(args.benchmark, args.size)
command = f"./{args.benchmark} -g {args.size}\n"
else:
command = "./{} -sf ../{}".format(args.benchmark, args.size)
command = f"./{args.benchmark} -sf ../{args.size}"
board.set_kernel_disk_workload(
# The x86 linux kernel will be automatically downloaded to the
@@ -262,7 +262,9 @@ print("Done with the simulation")
print()
print("Performance statistics:")
print("Simulated time in ROI: %.2fs" % ((end_tick - start_tick) / 1e12))
print(
f"Simulated time in ROI: {(end_tick - start_tick) / 1000000000000.0:.2f}s"
)
print(
"Ran a total of", simulator.get_current_tick() / 1e12, "simulated seconds"
)

2
configs/example/gem5_library/x86-npb-benchmarks.py
View File

@@ -195,7 +195,7 @@ board = X86Board(
# properly.
command = (
"/home/gem5/NPB3.3-OMP/bin/{}.{}.x;".format(args.benchmark, args.size)
f"/home/gem5/NPB3.3-OMP/bin/{args.benchmark}.{args.size}.x;"
+ "sleep 5;"
+ "m5 exit;"
)

5
configs/example/gem5_library/x86-parsec-benchmarks.py
View File

@@ -177,10 +177,7 @@ board = X86Board(
command = (
"cd /home/gem5/parsec-benchmark;".format(args.benchmark)
+ "source env.sh;"
+ "parsecmgmt -a run -p {} -c gcc-hooks -i {} \
-n {};".format(
args.benchmark, args.size, "2"
)
+ f"parsecmgmt -a run -p {args.benchmark} -c gcc-hooks -i {args.size} -n 2;"
+ "sleep 5;"
+ "m5 exit;"
)

4
configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
View File

@@ -179,7 +179,7 @@ if not os.path.exists(args.image):
print(
"https://gem5art.readthedocs.io/en/latest/tutorials/spec-tutorial.html"
)
fatal("The disk-image is not found at {}".format(args.image))
fatal(f"The disk-image is not found at {args.image}")
# Setting up all the fixed system parameters here
# Caches: MESI Two Level Cache Hierarchy
@@ -252,7 +252,7 @@ except FileExistsError:
# The runscript.sh file places `m5 exit` before and after the following command
# Therefore, we only pass this command without m5 exit.
command = "{} {} {}".format(args.benchmark, args.size, output_dir)
command = f"{args.benchmark} {args.size} {output_dir}"
board.set_kernel_disk_workload(
# The x86 linux kernel will be automatically downloaded to the

4
configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
View File

@@ -193,7 +193,7 @@ if not os.path.exists(args.image):
print(
"https://gem5art.readthedocs.io/en/latest/tutorials/spec-tutorial.html"
)
fatal("The disk-image is not found at {}".format(args.image))
fatal(f"The disk-image is not found at {args.image}")
# Setting up all the fixed system parameters here
# Caches: MESI Two Level Cache Hierarchy
@@ -266,7 +266,7 @@ except FileExistsError:
# The runscript.sh file places `m5 exit` before and after the following command
# Therefore, we only pass this command without m5 exit.
command = "{} {} {}".format(args.benchmark, args.size, output_dir)
command = f"{args.benchmark} {args.size} {output_dir}"
# For enabling CustomResource, we pass an additional parameter to mount the
# correct partition.

8
configs/example/gpufs/DisjointNetwork.py
View File

@@ -48,7 +48,7 @@ class DisjointSimple(SimpleNetwork):
def connectCPU(self, opts, controllers):
# Setup parameters for makeTopology call for CPU network
topo_module = import_module("topologies.%s" % opts.cpu_topology)
topo_module = import_module(f"topologies.{opts.cpu_topology}")
topo_class = getattr(topo_module, opts.cpu_topology)
_topo = topo_class(controllers)
_topo.makeTopology(opts, self, SimpleIntLink, SimpleExtLink, Switch)
@@ -58,7 +58,7 @@ class DisjointSimple(SimpleNetwork):
def connectGPU(self, opts, controllers):
# Setup parameters for makeTopology call for GPU network
topo_module = import_module("topologies.%s" % opts.gpu_topology)
topo_module = import_module(f"topologies.{opts.gpu_topology}")
topo_class = getattr(topo_module, opts.gpu_topology)
_topo = topo_class(controllers)
_topo.makeTopology(opts, self, SimpleIntLink, SimpleExtLink, Switch)
@@ -84,7 +84,7 @@ class DisjointGarnet(GarnetNetwork):
def connectCPU(self, opts, controllers):
# Setup parameters for makeTopology call for CPU network
topo_module = import_module("topologies.%s" % opts.cpu_topology)
topo_module = import_module(f"topologies.{opts.cpu_topology}")
topo_class = getattr(topo_module, opts.cpu_topology)
_topo = topo_class(controllers)
_topo.makeTopology(
@@ -96,7 +96,7 @@ class DisjointGarnet(GarnetNetwork):
def connectGPU(self, opts, controllers):
# Setup parameters for makeTopology call
topo_module = import_module("topologies.%s" % opts.gpu_topology)
topo_module = import_module(f"topologies.{opts.gpu_topology}")
topo_class = getattr(topo_module, opts.gpu_topology)
_topo = topo_class(controllers)
_topo.makeTopology(

10
configs/example/gpufs/hip_cookbook.py
View File

@@ -99,18 +99,16 @@ if __name__ == "__m5_main__":
# Create temp script to run application
if args.app is None:
print("No application given. Use %s -a <app>" % sys.argv[0])
print(f"No application given. Use {sys.argv[0]} -a <app>")
sys.exit(1)
elif args.kernel is None:
print("No kernel path given. Use %s --kernel <vmlinux>" % sys.argv[0])
print(f"No kernel path given. Use {sys.argv[0]} --kernel <vmlinux>")
sys.exit(1)
elif args.disk_image is None:
print("No disk path given. Use %s --disk-image <linux>" % sys.argv[0])
print(f"No disk path given. Use {sys.argv[0]} --disk-image <linux>")
sys.exit(1)
elif args.gpu_mmio_trace is None:
print(
"No MMIO trace path. Use %s --gpu-mmio-trace <path>" % sys.argv[0]
)
print(f"No MMIO trace path. Use {sys.argv[0]} --gpu-mmio-trace <path>")
sys.exit(1)
_, tempRunscript = tempfile.mkstemp()

10
configs/example/gpufs/hip_rodinia.py
View File

@@ -107,18 +107,16 @@ if __name__ == "__m5_main__":
# Create temp script to run application
if args.app is None:
print("No application given. Use %s -a <app>" % sys.argv[0])
print(f"No application given. Use {sys.argv[0]} -a <app>")
sys.exit(1)
elif args.kernel is None:
print("No kernel path given. Use %s --kernel <vmlinux>" % sys.argv[0])
print(f"No kernel path given. Use {sys.argv[0]} --kernel <vmlinux>")
sys.exit(1)
elif args.disk_image is None:
print("No disk path given. Use %s --disk-image <linux>" % sys.argv[0])
print(f"No disk path given. Use {sys.argv[0]} --disk-image <linux>")
sys.exit(1)
elif args.gpu_mmio_trace is None:
print(
"No MMIO trace path. Use %s --gpu-mmio-trace <path>" % sys.argv[0]
)
print(f"No MMIO trace path. Use {sys.argv[0]} --gpu-mmio-trace <path>")
sys.exit(1)
_, tempRunscript = tempfile.mkstemp()

10
configs/example/gpufs/hip_samples.py
View File

@@ -97,18 +97,16 @@ if __name__ == "__m5_main__":
# Create temp script to run application
if args.app is None:
print("No application given. Use %s -a <app>" % sys.argv[0])
print(f"No application given. Use {sys.argv[0]} -a <app>")
sys.exit(1)
elif args.kernel is None:
print("No kernel path given. Use %s --kernel <vmlinux>" % sys.argv[0])
print(f"No kernel path given. Use {sys.argv[0]} --kernel <vmlinux>")
sys.exit(1)
elif args.disk_image is None:
print("No disk path given. Use %s --disk-image <linux>" % sys.argv[0])
print(f"No disk path given. Use {sys.argv[0]} --disk-image <linux>")
sys.exit(1)
elif args.gpu_mmio_trace is None:
print(
"No MMIO trace path. Use %s --gpu-mmio-trace <path>" % sys.argv[0]
)
print(f"No MMIO trace path. Use {sys.argv[0]} --gpu-mmio-trace <path>")
sys.exit(1)
_, tempRunscript = tempfile.mkstemp()

2
configs/example/gpufs/runfs.py
View File

@@ -184,7 +184,7 @@ def runGpuFSSystem(args):
break
else:
print(
"Unknown exit event: %s. Continuing..." % exit_event.getCause()
f"Unknown exit event: {exit_event.getCause()}. Continuing..."
)
print(

10
configs/example/gpufs/vega10_kvm.py
View File

@@ -82,18 +82,16 @@ if __name__ == "__m5_main__":
# Create temp script to run application
if args.app is None:
print("No application given. Use %s -a <app>" % sys.argv[0])
print(f"No application given. Use {sys.argv[0]} -a <app>")
sys.exit(1)
elif args.kernel is None:
print("No kernel path given. Use %s --kernel <vmlinux>" % sys.argv[0])
print(f"No kernel path given. Use {sys.argv[0]} --kernel <vmlinux>")
sys.exit(1)
elif args.disk_image is None:
print("No disk path given. Use %s --disk-image <linux>" % sys.argv[0])
print(f"No disk path given. Use {sys.argv[0]} --disk-image <linux>")
sys.exit(1)
elif args.gpu_mmio_trace is None:
print(
"No MMIO trace path. Use %s --gpu-mmio-trace <path>" % sys.argv[0]
)
print(f"No MMIO trace path. Use {sys.argv[0]} --gpu-mmio-trace <path>")
sys.exit(1)
elif not os.path.isfile(args.app):
print("Could not find applcation", args.app)

72
configs/example/hsaTopology.py
View File

@@ -118,11 +118,11 @@ def createVegaTopology(options):
# Populate CPU node properties
node_prop = (
"cpu_cores_count %s\n" % options.num_cpus
f"cpu_cores_count {options.num_cpus}\n"
+ "simd_count 0\n"
+ "mem_banks_count 1\n"
+ "caches_count 0\n"
+ "io_links_count %s\n" % io_links
+ f"io_links_count {io_links}\n"
+ "cpu_core_id_base 0\n"
+ "simd_id_base 0\n"
+ "max_waves_per_simd 0\n"
@@ -200,8 +200,8 @@ def createVegaTopology(options):
"cpu_cores_count 0\n"
+ "simd_count 256\n"
+ "mem_banks_count 1\n"
+ "caches_count %s\n" % caches
+ "io_links_count %s\n" % io_links
+ f"caches_count {caches}\n"
+ f"io_links_count {io_links}\n"
+ "cpu_core_id_base 0\n"
+ "simd_id_base 2147487744\n"
+ "max_waves_per_simd 10\n"
@@ -212,11 +212,11 @@ def createVegaTopology(options):
+ "simd_arrays_per_engine 1\n"
+ "cu_per_simd_array 16\n"
+ "simd_per_cu 4\n"
+ "max_slots_scratch_cu %s\n" % cu_scratch
+ f"max_slots_scratch_cu {cu_scratch}\n"
+ "vendor_id 4098\n"
+ "device_id 26720\n"
+ "location_id 1024\n"
+ "drm_render_minor %s\n" % drm_num
+ f"drm_render_minor {drm_num}\n"
+ "hive_id 0\n"
+ "num_sdma_engines 2\n"
+ "num_sdma_xgmi_engines 0\n"
@@ -313,11 +313,11 @@ def createFijiTopology(options):
# Populate CPU node properties
node_prop = (
"cpu_cores_count %s\n" % options.num_cpus
f"cpu_cores_count {options.num_cpus}\n"
+ "simd_count 0\n"
+ "mem_banks_count 1\n"
+ "caches_count 0\n"
+ "io_links_count %s\n" % io_links
+ f"io_links_count {io_links}\n"
+ "cpu_core_id_base 0\n"
+ "simd_id_base 0\n"
+ "max_waves_per_simd 0\n"
@@ -392,33 +392,30 @@ def createFijiTopology(options):
# Populate GPU node properties
node_prop = (
"cpu_cores_count 0\n"
+ "simd_count %s\n"
% (options.num_compute_units * options.simds_per_cu)
+ f"simd_count {options.num_compute_units * options.simds_per_cu}\n"
+ "mem_banks_count 1\n"
+ "caches_count %s\n" % caches
+ "io_links_count %s\n" % io_links
+ f"caches_count {caches}\n"
+ f"io_links_count {io_links}\n"
+ "cpu_core_id_base 0\n"
+ "simd_id_base 2147487744\n"
+ "max_waves_per_simd %s\n" % options.wfs_per_simd
+ "lds_size_in_kb %s\n" % int(options.lds_size / 1024)
+ f"max_waves_per_simd {options.wfs_per_simd}\n"
+ f"lds_size_in_kb {int(options.lds_size / 1024)}\n"
+ "gds_size_in_kb 0\n"
+ "wave_front_size %s\n" % options.wf_size
+ f"wave_front_size {options.wf_size}\n"
+ "array_count 4\n"
+ "simd_arrays_per_engine %s\n" % options.sa_per_complex
+ "cu_per_simd_array %s\n" % options.cu_per_sa
+ "simd_per_cu %s\n" % options.simds_per_cu
+ f"simd_arrays_per_engine {options.sa_per_complex}\n"
+ f"cu_per_simd_array {options.cu_per_sa}\n"
+ f"simd_per_cu {options.simds_per_cu}\n"
+ "max_slots_scratch_cu 32\n"
+ "vendor_id 4098\n"
+ "device_id 29440\n"
+ "location_id 512\n"
+ "drm_render_minor %s\n" % drm_num
+ "max_engine_clk_fcompute %s\n"
% int(toFrequency(options.gpu_clock) / 1e6)
+ f"drm_render_minor {drm_num}\n"
+ f"max_engine_clk_fcompute {int(toFrequency(options.gpu_clock) / 1000000.0)}\n"
+ "local_mem_size 4294967296\n"
+ "fw_version 730\n"
+ "capability 4736\n"
+ "max_engine_clk_ccompute %s\n"
% int(toFrequency(options.CPUClock) / 1e6)
+ f"max_engine_clk_ccompute {int(toFrequency(options.CPUClock) / 1000000.0)}\n"
)
file_append((node_dir, "properties"), node_prop)
@@ -484,34 +481,31 @@ def createCarrizoTopology(options):
# populate global node properties
# NOTE: SIMD count triggers a valid GPU agent creation
node_prop = (
"cpu_cores_count %s\n" % options.num_cpus
+ "simd_count %s\n"
% (options.num_compute_units * options.simds_per_cu)
+ "mem_banks_count %s\n" % mem_banks_cnt
f"cpu_cores_count {options.num_cpus}\n"
+ f"simd_count {options.num_compute_units * options.simds_per_cu}\n"
+ f"mem_banks_count {mem_banks_cnt}\n"
+ "caches_count 0\n"
+ "io_links_count 0\n"
+ "cpu_core_id_base 16\n"
+ "simd_id_base 2147483648\n"
+ "max_waves_per_simd %s\n" % options.wfs_per_simd
+ "lds_size_in_kb %s\n" % int(options.lds_size / 1024)
+ f"max_waves_per_simd {options.wfs_per_simd}\n"
+ f"lds_size_in_kb {int(options.lds_size / 1024)}\n"
+ "gds_size_in_kb 0\n"
+ "wave_front_size %s\n" % options.wf_size
+ f"wave_front_size {options.wf_size}\n"
+ "array_count 1\n"
+ "simd_arrays_per_engine %s\n" % options.sa_per_complex
+ "cu_per_simd_array %s\n" % options.cu_per_sa
+ "simd_per_cu %s\n" % options.simds_per_cu
+ f"simd_arrays_per_engine {options.sa_per_complex}\n"
+ f"cu_per_simd_array {options.cu_per_sa}\n"
+ f"simd_per_cu {options.simds_per_cu}\n"
+ "max_slots_scratch_cu 32\n"
+ "vendor_id 4098\n"
+ "device_id %s\n" % device_id
+ f"device_id {device_id}\n"
+ "location_id 8\n"
+ "drm_render_minor %s\n" % drm_num
+ "max_engine_clk_fcompute %s\n"
% int(toFrequency(options.gpu_clock) / 1e6)
+ f"drm_render_minor {drm_num}\n"
+ f"max_engine_clk_fcompute {int(toFrequency(options.gpu_clock) / 1000000.0)}\n"
+ "local_mem_size 0\n"
+ "fw_version 699\n"
+ "capability 4738\n"
+ "max_engine_clk_ccompute %s\n"
% int(toFrequency(options.CPUClock) / 1e6)
+ f"max_engine_clk_ccompute {int(toFrequency(options.CPUClock) / 1000000.0)}\n"
)
file_append((node_dir, "properties"), node_prop)

4
configs/example/lupv/run_lupv.py
View File

@@ -113,6 +113,4 @@ print("Beginning simulation!")
exit_event = m5.simulate(args.max_ticks)
print(
"Exiting @ tick {} because {}.".format(m5.curTick(), exit_event.getCause())
)
print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}.")

2
configs/example/memcheck.py
View File

@@ -330,7 +330,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
make_cache_level(cachespec, cache_proto, len(cachespec), None)
# Connect the lowest level crossbar to the memory
last_subsys = getattr(system, "l%dsubsys0" % len(cachespec))
last_subsys = getattr(system, f"l{len(cachespec)}subsys0")
last_subsys.xbar.mem_side_ports = system.physmem.port
last_subsys.xbar.point_of_coherency = True

5
configs/example/memtest.py
View File

@@ -211,8 +211,7 @@ else:
if numtesters(cachespec, testerspec) > block_size:
print(
"Error: Limited to %s testers because of false sharing"
% (block_size)
f"Error: Limited to {block_size} testers because of false sharing"
)
sys.exit(1)
@@ -351,7 +350,7 @@ make_cache_level(cachespec, cache_proto, len(cachespec), None)
# Connect the lowest level crossbar to the last-level cache and memory
# controller
last_subsys = getattr(system, "l%dsubsys0" % len(cachespec))
last_subsys = getattr(system, f"l{len(cachespec)}subsys0")
last_subsys.xbar.point_of_coherency = True
if args.noncoherent_cache:
system.llc = NoncoherentCache(

10
configs/example/read_config.py
View File

@@ -68,8 +68,7 @@ sim_object_classes_by_name = {
def no_parser(cls, flags, param):
raise Exception(
"Can't parse string: %s for parameter"
" class: %s" % (str(param), cls.__name__)
f"Can't parse string: {str(param)} for parameter class: {cls.__name__}"
)
@@ -114,7 +113,7 @@ def memory_bandwidth_parser(cls, flags, param):
value = 1.0 / float(param)
# Convert to byte/s
value = ticks.fromSeconds(value)
return cls("%fB/s" % value)
return cls(f"{value:f}B/s")
# These parameters have trickier parsing from .ini files than might be
@@ -201,8 +200,7 @@ class ConfigManager(object):
if object_type not in sim_object_classes_by_name:
raise Exception(
"No SimObject type %s is available to"
" build: %s" % (object_type, object_name)
f"No SimObject type {object_type} is available to build: {object_name}"
)
object_class = sim_object_classes_by_name[object_type]
@@ -479,7 +477,7 @@ class ConfigIniFile(ConfigFile):
if object_name == "root":
return child_name
else:
return "%s.%s" % (object_name, child_name)
return f"{object_name}.{child_name}"
return [(name, make_path(name)) for name in child_names]

2
configs/example/riscv/fs_linux.py
View File

@@ -91,7 +91,7 @@ from common import Options
def generateMemNode(state, mem_range):
node = FdtNode("memory@%x" % int(mem_range.start))
node = FdtNode(f"memory@{int(mem_range.start):x}")
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(
FdtPropertyWords(

2
configs/example/sst/riscv_fs.py
View File

@@ -35,7 +35,7 @@ import argparse
def generateMemNode(state, mem_range):
node = FdtNode("memory@%x" % int(mem_range.start))
node = FdtNode(f"memory@{int(mem_range.start):x}")
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(
FdtPropertyWords(

8
configs/learning_gem5/part1/caches.py
View File

@@ -75,7 +75,7 @@ class L1ICache(L1Cache):
size = "16kB"
SimpleOpts.add_option(
"--l1i_size", help="L1 instruction cache size. Default: %s" % size
"--l1i_size", help=f"L1 instruction cache size. Default: {size}"
)
def __init__(self, opts=None):
@@ -96,7 +96,7 @@ class L1DCache(L1Cache):
size = "64kB"
SimpleOpts.add_option(
"--l1d_size", help="L1 data cache size. Default: %s" % size
"--l1d_size", help=f"L1 data cache size. Default: {size}"
)
def __init__(self, opts=None):
@@ -122,9 +122,7 @@ class L2Cache(Cache):
mshrs = 20
tgts_per_mshr = 12
SimpleOpts.add_option(
"--l2_size", help="L2 cache size. Default: %s" % size
)
SimpleOpts.add_option("--l2_size", help=f"L2 cache size. Default: {size}")
def __init__(self, opts=None):
super(L2Cache, self).__init__()

4
configs/learning_gem5/part3/ruby_test.py
View File

@@ -78,6 +78,4 @@ m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print(
"Exiting @ tick {} because {}".format(m5.curTick(), exit_event.getCause())
)
print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")

4
configs/learning_gem5/part3/simple_ruby.py
View File

@@ -110,6 +110,4 @@ m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print(
"Exiting @ tick {} because {}".format(m5.curTick(), exit_event.getCause())
)
print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")

2
configs/ruby/CHI.py
View File

@@ -280,6 +280,6 @@ def create_system(
elif options.topology in ["Crossbar", "Pt2Pt"]:
topology = create_topology(network_cntrls, options)
else:
m5.fatal("%s not supported!" % options.topology)
m5.fatal(f"{options.topology} not supported!")
return (cpu_sequencers, mem_cntrls, topology)

2
configs/ruby/CHI_config.py
View File

@@ -428,7 +428,7 @@ class CPUSequencerWrapper:
cpu.icache_port = self.inst_seq.in_ports
for p in cpu._cached_ports:
if str(p) != "icache_port":
exec("cpu.%s = self.data_seq.in_ports" % p)
exec(f"cpu.{p} = self.data_seq.in_ports")
cpu.connectUncachedPorts(
self.data_seq.in_ports, self.data_seq.interrupt_out_port
)

12
configs/ruby/Ruby.py
View File

@@ -120,8 +120,8 @@ def define_options(parser):
)
protocol = buildEnv["PROTOCOL"]
exec("from . import %s" % protocol)
eval("%s.define_options(parser)" % protocol)
exec(f"from . import {protocol}")
eval(f"{protocol}.define_options(parser)")
Network.define_options(parser)
@@ -207,8 +207,8 @@ def create_topology(controllers, options):
found in configs/topologies/BaseTopology.py
This is a wrapper for the legacy topologies.
"""
exec("import topologies.%s as Topo" % options.topology)
topology = eval("Topo.%s(controllers)" % options.topology)
exec(f"import topologies.{options.topology} as Topo")
topology = eval(f"Topo.{options.topology}(controllers)")
return topology
@@ -242,7 +242,7 @@ def create_system(
cpus = system.cpu
protocol = buildEnv["PROTOCOL"]
exec("from . import %s" % protocol)
exec(f"from . import {protocol}")
try:
(cpu_sequencers, dir_cntrls, topology) = eval(
"%s.create_system(options, full_system, system, dma_ports,\
@@ -250,7 +250,7 @@ def create_system(
% protocol
)
except:
print("Error: could not create sytem for ruby protocol %s" % protocol)
print(f"Error: could not create sytem for ruby protocol {protocol}")
raise
# Create the network topology

12
configs/topologies/CustomMesh.py
View File

@@ -325,9 +325,7 @@ class CustomMesh(SimpleTopology):
rni_io_params = check_same(type(n).NoC_Params, rni_io_params)
else:
fatal(
"topologies.CustomMesh: {} not supported".format(
n.__class__.__name__
)
f"topologies.CustomMesh: {n.__class__.__name__} not supported"
)
# Create all mesh routers
@@ -420,11 +418,11 @@ class CustomMesh(SimpleTopology):
if pair_debug:
print(c.path())
for r in c.addr_ranges:
print("%s" % r)
print(f"{r}")
for p in c._pairing:
print("\t" + p.path())
for r in p.addr_ranges:
print("\t%s" % r)
print(f"\t{r}")
# all must be paired
for c in all_cache:
@@ -516,8 +514,8 @@ class CustomMesh(SimpleTopology):
assert len(c._pairing) == pairing_check
print(c.path())
for r in c.addr_ranges:
print("%s" % r)
print(f"{r}")
for p in c._pairing:
print("\t" + p.path())
for r in p.addr_ranges:
print("\t%s" % r)
print(f"\t{r}")

2
site_scons/gem5_scons/builders/switching_headers.py
View File

@@ -61,7 +61,7 @@ def SwitchingHeaders(env):
os.path.realpath(dp), os.path.realpath(env["BUILDDIR"])
)
with open(path, "w") as hdr:
print('#include "%s/%s/%s"' % (dp, subdir, fp), file=hdr)
print(f'#include "{dp}/{subdir}/{fp}"', file=hdr)
switching_header_action = MakeAction(
build_switching_header, Transform("GENERATE")

10
site_scons/gem5_scons/configure.py
View File

@@ -46,7 +46,7 @@ import SCons.Util
def CheckCxxFlag(context, flag, autoadd=True):
context.Message("Checking for compiler %s support... " % flag)
context.Message(f"Checking for compiler {flag} support... ")
last_cxxflags = context.env["CXXFLAGS"]
context.env.Append(CXXFLAGS=[flag])
pre_werror = context.env["CXXFLAGS"]
@@ -60,7 +60,7 @@ def CheckCxxFlag(context, flag, autoadd=True):
def CheckLinkFlag(context, flag, autoadd=True, set_for_shared=True):
context.Message("Checking for linker %s support... " % flag)
context.Message(f"Checking for linker {flag} support... ")
last_linkflags = context.env["LINKFLAGS"]
context.env.Append(LINKFLAGS=[flag])
pre_werror = context.env["LINKFLAGS"]
@@ -78,7 +78,7 @@ def CheckLinkFlag(context, flag, autoadd=True, set_for_shared=True):
# Add a custom Check function to test for structure members.
def CheckMember(context, include, decl, member, include_quotes="<>"):
context.Message("Checking for member %s in %s..." % (member, decl))
context.Message(f"Checking for member {member} in {decl}...")
text = """
#include %(header)s
int main(){
@@ -128,8 +128,8 @@ def CheckPkgConfig(context, pkgs, *args):
assert pkgs
for pkg in pkgs:
context.Message("Checking for pkg-config package %s... " % pkg)
ret = context.TryAction("pkg-config %s" % pkg)[0]
context.Message(f"Checking for pkg-config package {pkg}... ")
ret = context.TryAction(f"pkg-config {pkg}")[0]
if not ret:
context.Result(ret)
continue

2
site_scons/site_tools/git.py
View File

@@ -63,7 +63,7 @@ def install_style_hooks(env):
).strip("\n")
)
except Exception as e:
print("Warning: Failed to find git repo directory: %s" % e)
print(f"Warning: Failed to find git repo directory: {e}")
return
git_hooks = gitdir.Dir("hooks")

2
src/arch/arm/ArmSystem.py
View File

@@ -262,7 +262,7 @@ class ArmSystem(System):
# root instead of appended.
def generateMemNode(mem_range):
node = FdtNode("memory@%x" % int(mem_range.start))
node = FdtNode(f"memory@{int(mem_range.start):x}")
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(
FdtPropertyWords(

4
src/arch/arm/fastmodel/FastModel.py
View File

@@ -39,11 +39,11 @@ def AMBA_INITIATOR_ROLE(width):
def SC_REQUEST_PORT_ROLE(port_type):
return "SC REQUEST PORT for %s" % port_type
return f"SC REQUEST PORT for {port_type}"
def SC_RESPONSE_PORT_ROLE(port_type):
return "SC RESPONSE PORT for %s" % port_type
return f"SC RESPONSE PORT for {port_type}"
class AmbaTargetSocket(Port):

12
src/arch/arm/fastmodel/arm_fast_model.py
View File

@@ -64,13 +64,13 @@ def check_armlmd_license(timeout):
for server in servers:
if os.path.exists(server):
logging.debug("License file %s exists." % server)
logging.debug(f"License file {server} exists.")
break
tuple = server.split("@")
if len(tuple) != 2:
# Probably not a server, and we know the file doesn't exist.
logging.debug('License file "%s" does not exist.' % server)
logging.debug(f'License file "{server}" does not exist.')
continue
try:
@@ -80,17 +80,15 @@ def check_armlmd_license(timeout):
(tuple[1], int(tuple[0])), timeout=timeout
)
s.close()
logging.debug("License server %s is reachable." % server)
logging.debug(f"License server {server} is reachable.")
break
except Exception as e:
logging.debug(
"Cannot connect to license server %s (%s: %s)."
% (server, type(e).__name__, e)
f"Cannot connect to license server {server} ({type(e).__name__}: {e})."
)
else:
raise ConnectionError(
"Cannot connect to any of the license servers (%s)."
% ", ".join(servers)
f"Cannot connect to any of the license servers ({', '.join(servers)})."
)

81
src/arch/isa_parser/isa_parser.py
View File

@@ -206,13 +206,11 @@ class Format(object):
label = "def format " + id
self.user_code = compile(fixPythonIndentation(code), label, "exec")
param_list = ", ".join(params)
f = (
"""def defInst(_code, _context, %s):
f = f"""def defInst(_code, _context, {param_list}):
my_locals = vars().copy()
exec(_code, _context, my_locals)
return my_locals\n"""
% param_list
)
return my_locals
"""
c = compile(f, label + " wrapper", "exec")
exec(c, globals())
self.func = defInst
@@ -230,7 +228,7 @@ class Format(object):
except Exception as exc:
if debug:
raise
error(lineno, 'error defining "%s": %s.' % (name, exc))
error(lineno, f'error defining "{name}": {exc}.')
for k in list(vars.keys()):
if k not in (
"header_output",
@@ -250,7 +248,7 @@ class NoFormat(object):
def defineInst(self, parser, name, args, lineno):
error(
lineno, 'instruction definition "%s" with no active format!' % name
lineno, f'instruction definition "{name}" with no active format!'
)
@@ -606,7 +604,7 @@ class ISAParser(Grammar):
if section == "header":
file = "decoder.hh"
else:
file = "%s.cc" % section
file = f"{section}.cc"
filename = self.suffixize(file, section)
try:
return self.files[filename]
@@ -652,7 +650,7 @@ class ISAParser(Grammar):
)
fn = "decoder-g.hh.inc"
assert fn in self.files
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
fn = "decoder-ns.hh.inc"
assert fn in self.files
@@ -663,26 +661,25 @@ class ISAParser(Grammar):
)
f.write("} // namespace gem5")
f.write(
"\n#endif // __ARCH_%s_GENERATED_DECODER_HH__\n"
% self.isa_name.upper()
f"\n#endif // __ARCH_{self.isa_name.upper()}_GENERATED_DECODER_HH__\n"
)
# decoder method - cannot be split
file = "decoder.cc"
with self.open(file) as f:
fn = "base/compiler.hh"
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
fn = "decoder-g.cc.inc"
assert fn in self.files
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
fn = "decoder.hh"
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
fn = "decode-method.cc.inc"
# is guaranteed to have been written for parse to complete
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
extn = re.compile("(\.[^\.]+)$")
@@ -697,10 +694,10 @@ class ISAParser(Grammar):
with self.open(file) as f:
fn = "decoder-g.cc.inc"
assert fn in self.files
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
fn = "decoder.hh"
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
fn = "decoder-ns.cc.inc"
assert fn in self.files
@@ -708,7 +705,7 @@ class ISAParser(Grammar):
print("namespace %s {" % self.namespace, file=f)
if splits > 1:
print("#define __SPLIT %u" % i, file=f)
print('#include "%s"' % fn, file=f)
print(f'#include "{fn}"', file=f)
print("} // namespace %s" % self.namespace, file=f)
print("} // namespace gem5", file=f)
@@ -721,7 +718,7 @@ class ISAParser(Grammar):
with self.open(file) as f:
fn = "exec-g.cc.inc"
assert fn in self.files
f.write('#include "%s"\n' % fn)
f.write(f'#include "{fn}"\n')
f.write('#include "cpu/exec_context.hh"\n')
f.write('#include "decoder.hh"\n')
@@ -731,7 +728,7 @@ class ISAParser(Grammar):
print("namespace %s {" % self.namespace, file=f)
if splits > 1:
print("#define __SPLIT %u" % i, file=f)
print('#include "%s"' % fn, file=f)
print(f'#include "{fn}"', file=f)
print("} // namespace %s" % self.namespace, file=f)
print("} // namespace gem5", file=f)
@@ -847,7 +844,7 @@ class ISAParser(Grammar):
try:
t.value = int(t.value, 0)
except ValueError:
error(t.lexer.lineno, 'Integer value "%s" too large' % t.value)
error(t.lexer.lineno, f'Integer value "{t.value}" too large')
t.value = 0
return t
@@ -902,7 +899,7 @@ class ISAParser(Grammar):
# Error handler
def t_error(self, t):
error(t.lexer.lineno, "illegal character '%s'" % t.value[0])
error(t.lexer.lineno, f"illegal character '{t.value[0]}'")
t.skip(1)
#####################################################################
@@ -1060,7 +1057,7 @@ del wrap
traceback.print_exc(file=sys.stdout)
if debug:
raise
error(t.lineno(1), "In global let block: %s" % exc)
error(t.lineno(1), f"In global let block: {exc}")
GenCode(
self,
header_output=self.exportContext["header_output"],
@@ -1078,7 +1075,7 @@ del wrap
except Exception as exc:
if debug:
raise
error(t.lineno(1), "In def operand_types: %s" % exc)
error(t.lineno(1), f"In def operand_types: {exc}")
# Define the mapping from operand names to operand classes and
# other traits. Stored in operandNameMap.
@@ -1094,7 +1091,7 @@ del wrap
except Exception as exc:
if debug:
raise
error(t.lineno(1), "In def operands: %s" % exc)
error(t.lineno(1), f"In def operands: {exc}")
self.buildOperandNameMap(user_dict, t.lexer.lineno)
# A bitfield definition looks like:
@@ -1105,7 +1102,7 @@ del wrap
expr = "bits(machInst, %2d, %2d)" % (t[6], t[8])
if t[2] == "signed":
expr = "sext<%d>(%s)" % (t[6] - t[8] + 1, expr)
hash_define = "#undef %s\n#define %s\t%s\n" % (t[4], t[4], expr)
hash_define = f"#undef {t[4]}\n#define {t[4]}\t{expr}\n"
GenCode(self, header_output=hash_define).emit()
# alternate form for single bit: 'def [signed] bitfield <ID> [<bit>]'
@@ -1114,7 +1111,7 @@ del wrap
expr = "bits(machInst, %2d, %2d)" % (t[6], t[6])
if t[2] == "signed":
expr = "sext<%d>(%s)" % (1, expr)
hash_define = "#undef %s\n#define %s\t%s\n" % (t[4], t[4], expr)
hash_define = f"#undef {t[4]}\n#define {t[4]}\t{expr}\n"
GenCode(self, header_output=hash_define).emit()
# alternate form for structure member: 'def bitfield <ID> <ID>'
@@ -1124,8 +1121,8 @@ del wrap
error(
t.lineno(1), "error: structure bitfields are always unsigned."
)
expr = "machInst.%s" % t[5]
hash_define = "#undef %s\n#define %s\t%s\n" % (t[4], t[4], expr)
expr = f"machInst.{t[5]}"
hash_define = f"#undef {t[4]}\n#define {t[4]}\t{expr}\n"
GenCode(self, header_output=hash_define).emit()
def p_id_with_dot_0(self, t):
@@ -1147,7 +1144,7 @@ del wrap
def p_def_template(self, t):
"def_template : DEF TEMPLATE ID CODELIT SEMI"
if t[3] in self.templateMap:
print("warning: template %s already defined" % t[3])
print(f"warning: template {t[3]} already defined")
self.templateMap[t[3]] = Template(self, t[4])
# An instruction format definition looks like
@@ -1326,9 +1323,9 @@ StaticInstPtr
"push_format_id : ID"
try:
self.formatStack.push(self.formatMap[t[1]])
t[0] = ("", "// format %s" % t[1])
t[0] = ("", f"// format {t[1]}")
except KeyError:
error(t.lineno(1), 'instruction format "%s" not defined.' % t[1])
error(t.lineno(1), f'instruction format "{t[1]}" not defined.')
# Nested decode block: if the value of the current field matches
# the specified constant(s), do a nested decode on some other field.
@@ -1339,7 +1336,7 @@ StaticInstPtr
# just wrap the decoding code from the block as a case in the
# outer switch statement.
codeObj.wrap_decode_block(
"\n%s\n" % "".join(case_list), "GEM5_UNREACHABLE;\n"
f"\n{''.join(case_list)}\n", "GEM5_UNREACHABLE;\n"
)
codeObj.has_decode_default = case_list == ["default:"]
t[0] = codeObj
@@ -1349,7 +1346,7 @@ StaticInstPtr
"decode_stmt : case_list COLON inst SEMI"
case_list = t[1]
codeObj = t[3]
codeObj.wrap_decode_block("\n%s" % "".join(case_list), "break;\n")
codeObj.wrap_decode_block(f"\n{''.join(case_list)}", "break;\n")
codeObj.has_decode_default = case_list == ["default:"]
t[0] = codeObj
@@ -1368,7 +1365,7 @@ StaticInstPtr
return "case %#x: " % lit
def prep_str_lit_case_label(self, lit):
return "case %s: " % lit
return f"case {lit}: "
def p_case_list_1(self, t):
"case_list : INTLIT"
@@ -1399,7 +1396,7 @@ StaticInstPtr
args = ",".join(list(map(str, t[3])))
args = re.sub("(?m)^", "//", args)
args = re.sub("^//", "", args)
comment = "\n// %s::%s(%s)\n" % (currentFormat.id, t[1], args)
comment = f"\n// {currentFormat.id}::{t[1]}({args})\n"
codeObj.prepend_all(comment)
t[0] = codeObj
@@ -1410,10 +1407,10 @@ StaticInstPtr
try:
format = self.formatMap[t[1]]
except KeyError:
error(t.lineno(1), 'instruction format "%s" not defined.' % t[1])
error(t.lineno(1), f'instruction format "{t[1]}" not defined.')
codeObj = format.defineInst(self, t[3], t[5], t.lexer.lineno)
comment = "\n// %s::%s(%s)\n" % (t[1], t[3], t[5])
comment = f"\n// {t[1]}::{t[3]}({t[5]})\n"
codeObj.prepend_all(comment)
t[0] = codeObj
@@ -1503,7 +1500,7 @@ StaticInstPtr
# t.value)
def p_error(self, t):
if t:
error(t.lexer.lineno, "syntax error at '%s'" % t.value)
error(t.lexer.lineno, f"syntax error at '{t.value}'")
else:
error("unknown syntax error")
@@ -1523,7 +1520,7 @@ StaticInstPtr
# make sure we haven't already defined this one
if id in self.formatMap:
error(lineno, "format %s redefined." % id)
error(lineno, f"format {id} redefined.")
# create new object and store in global map
self.formatMap[id] = Format(id, params, code)
@@ -1641,7 +1638,7 @@ StaticInstPtr
try:
contents = open(filename).read()
except IOError:
error('Error including file "%s"' % filename)
error(f'Error including file "{filename}"')
self.fileNameStack.push(LineTracker(filename))
@@ -1691,7 +1688,7 @@ StaticInstPtr
self._parse_isa_desc(*args, **kwargs)
except ISAParserError as e:
print(backtrace(self.fileNameStack))
print("At %s:" % e.lineno)
print(f"At {e.lineno}:")
print(e)
sys.exit(1)

3
src/arch/isa_parser/operand_list.py
View File

@@ -205,8 +205,7 @@ class SubOperandList(OperandList):
op_desc = requestor_list.find_base(op_base)
if not op_desc:
error(
"Found operand %s which is not in the requestor list!"
% op_base
f"Found operand {op_base} which is not in the requestor list!"
)
else:
# See if we've already found this operand

22
src/arch/isa_parser/operand_types.py
View File

@@ -286,16 +286,16 @@ class VecRegOperand(RegOperand):
else:
ext = dflt_elem_ext
ctype = self.parser.operandTypeMap[ext]
return "\n\t%s %s = 0;" % (ctype, elem_name)
return f"\n\t{ctype} {elem_name} = 0;"
def makeDecl(self):
if not self.is_dest and self.is_src:
c_decl = "\t/* Vars for %s*/" % (self.base_name)
c_decl = f"\t/* Vars for {self.base_name}*/"
if hasattr(self, "active_elems"):
if self.active_elems:
for elem in self.active_elems:
c_decl += self.makeDeclElem(elem)
return c_decl + "\t/* End vars for %s */\n" % (self.base_name)
return c_decl + f"\t/* End vars for {self.base_name} */\n"
else:
return ""
@@ -308,12 +308,7 @@ class VecRegOperand(RegOperand):
else:
ext = dflt_elem_ext
ctype = self.parser.operandTypeMap[ext]
c_read = "\t\t%s& %s = %s[%s];\n" % (
ctype,
elem_name,
self.base_name,
elem_spec,
)
c_read = f"\t\t{ctype}& {elem_name} = {self.base_name}[{elem_spec}];\n"
return c_read
def makeReadW(self):
@@ -346,7 +341,7 @@ class VecRegOperand(RegOperand):
else:
ext = dflt_elem_ext
ctype = self.parser.operandTypeMap[ext]
c_read = "\t\t%s = %s[%s];\n" % (elem_name, name, elem_spec)
c_read = f"\t\t{elem_name} = {name}[{elem_spec}];\n"
return c_read
def makeRead(self):
@@ -610,10 +605,7 @@ class PCStateOperand(Operand):
def makeWrite(self):
if self.reg_spec:
# A component of the PC state.
return "__parserAutoPCState.%s(%s);\n" % (
self.reg_spec,
self.base_name,
)
return f"__parserAutoPCState.{self.reg_spec}({self.base_name});\n"
else:
# The whole PC state itself.
return f"xc->pcState({self.base_name});\n"
@@ -624,7 +616,7 @@ class PCStateOperand(Operand):
ctype = self.ctype
# Note that initializations in the declarations are solely
# to avoid 'uninitialized variable' errors from the compiler.
return "%s %s = 0;\n" % (ctype, self.base_name)
return f"{ctype} {self.base_name} = 0;\n"
def isPCState(self):
return 1

34
src/arch/micro_asm.py
View File

@@ -56,9 +56,9 @@ class MicroContainer:
self.microops.append(microop)
def __str__(self):
string = "%s:\n" % self.name
string = f"{self.name}:\n"
for microop in self.microops:
string += " %s\n" % microop
string += f" {microop}\n"
return string
@@ -72,7 +72,7 @@ class RomMacroop:
self.target = target
def __str__(self):
return "%s: %s\n" % (self.name, self.target)
return f"{self.name}: {self.target}\n"
class Rom(MicroContainer):
@@ -130,29 +130,26 @@ class Directive(Statement):
def print_error(message):
print()
print("*** %s" % message)
print(f"*** {message}")
print()
def handle_statement(parser, container, statement):
if statement.is_microop:
if statement.mnemonic not in parser.microops.keys():
raise Exception(
"Unrecognized mnemonic: {}".format(statement.mnemonic)
)
raise Exception(f"Unrecognized mnemonic: {statement.mnemonic}")
parser.symbols[
"__microopClassFromInsideTheAssembler"
] = parser.microops[statement.mnemonic]
try:
microop = eval(
"__microopClassFromInsideTheAssembler(%s)" % statement.params,
f"__microopClassFromInsideTheAssembler({statement.params})",
{},
parser.symbols,
)
except:
print_error(
"Error creating microop object with mnemonic %s."
% statement.mnemonic
f"Error creating microop object with mnemonic {statement.mnemonic}."
)
raise
try:
@@ -166,16 +163,13 @@ def handle_statement(parser, container, statement):
raise
elif statement.is_directive:
if statement.name not in container.directives.keys():
raise Exception(
"Unrecognized directive: {}".format(statement.name)
)
raise Exception(f"Unrecognized directive: {statement.name}")
parser.symbols[
"__directiveFunctionFromInsideTheAssembler"
] = container.directives[statement.name]
try:
eval(
"__directiveFunctionFromInsideTheAssembler(%s)"
% statement.params,
f"__directiveFunctionFromInsideTheAssembler({statement.params})",
{},
parser.symbols,
)
@@ -184,9 +178,7 @@ def handle_statement(parser, container, statement):
print(container.directives)
raise
else:
raise Exception(
"Didn't recognize the type of statement {}".format(statement)
)
raise Exception(f"Didn't recognize the type of statement {statement}")
##########################################################################
@@ -207,7 +199,7 @@ def error(lineno, string, print_traceback=False):
line_str = "%d:" % lineno
else:
line_str = ""
sys.exit("%s %s" % (line_str, string))
sys.exit(f"{line_str} {string}")
reserved = ("DEF", "MACROOP", "ROM", "EXTERN")
@@ -358,7 +350,7 @@ t_ANY_ignore = " \t\x0c"
def t_ANY_error(t):
error(t.lineno, "illegal character '%s'" % t.value[0])
error(t.lineno, f"illegal character '{t.value[0]}'")
t.skip(1)
@@ -570,7 +562,7 @@ def p_directive_1(t):
# *token*, not a grammar symbol (hence the need to use t.value)
def p_error(t):
if t:
error(t.lineno, "syntax error at '%s'" % t.value)
error(t.lineno, f"syntax error at '{t.value}'")
else:
error(0, "unknown syntax error", True)

4
src/arch/micro_asm_test.py
View File

@@ -39,10 +39,10 @@ class Bah_Tweaked(object):
class Hoop(object):
def __init__(self, first_param, second_param):
self.mnemonic = "hoop_%s_%s" % (first_param, second_param)
self.mnemonic = f"hoop_{first_param}_{second_param}"
def __str__(self):
return "%s" % self.mnemonic
return f"{self.mnemonic}"
class Dah(object):

3
src/arch/x86/bios/IntelMP.py
View File

@@ -81,8 +81,7 @@ class X86IntelMPConfigTable(SimObject):
self.ext_entries.append(entry)
else:
panic(
"Don't know what type of Intel MP entry %s is."
% entry.__class__.__name__
f"Don't know what type of Intel MP entry {entry.__class__.__name__} is."
)

2
src/arch/x86/isa/insts/__init__.py
View File

@@ -46,5 +46,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/__init__.py
View File

@@ -56,5 +56,5 @@ microcode = """
# Microcode for general purpose instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/arithmetic/__init__.py
View File

@@ -41,5 +41,5 @@ categories = [
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/compare_and_test/__init__.py
View File

@@ -44,5 +44,5 @@ categories = [
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/control_transfer/__init__.py
View File

@@ -44,5 +44,5 @@ categories = [
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/data_conversion/__init__.py
View File

@@ -44,5 +44,5 @@ categories = [
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/data_transfer/__init__.py
View File

@@ -37,5 +37,5 @@ categories = ["conditional_move", "move", "stack_operations", "xchg"]
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/flags/__init__.py
View File

@@ -37,5 +37,5 @@ categories = ["load_and_store", "push_and_pop", "set_and_clear"]
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/input_output/__init__.py
View File

@@ -37,5 +37,5 @@ categories = ["general_io", "string_io"]
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/rotate_and_shift/__init__.py
View File

@@ -37,5 +37,5 @@ categories = ["rotate", "shift"]
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/general_purpose/string/__init__.py
View File

@@ -43,5 +43,5 @@ categories = [
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/__init__.py
View File

@@ -46,5 +46,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/arithmetic/__init__.py
View File

@@ -50,5 +50,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/compare/__init__.py
View File

@@ -43,5 +43,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/data_conversion/__init__.py
View File

@@ -45,5 +45,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/data_reordering/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/data_transfer/__init__.py
View File

@@ -44,5 +44,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/floating_point/logical/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# SSE instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/__init__.py
View File

@@ -48,5 +48,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/arithmetic/__init__.py
View File

@@ -47,5 +47,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/compare/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/data_conversion/__init__.py
View File

@@ -43,5 +43,5 @@ microcode = """
# 128 bit multimedia and scientific conversion instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/data_reordering/__init__.py
View File

@@ -44,5 +44,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/data_transfer/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 128 bit multimedia and scientific data transfer instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/logical/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd128/integer/shift/__init__.py
View File

@@ -43,5 +43,5 @@ microcode = """
# 128 bit multimedia and scientific instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/floating_point/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/floating_point/arithmetic/__init__.py
View File

@@ -46,5 +46,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/floating_point/compare/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/__init__.py
View File

@@ -49,5 +49,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/arithmetic/__init__.py
View File

@@ -46,5 +46,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/compare/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/data_reordering/__init__.py
View File

@@ -44,5 +44,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/data_transfer/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/logical/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/simd64/integer/shift/__init__.py
View File

@@ -43,5 +43,5 @@ microcode = """
# 64 bit multimedia instructions
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/system/__init__.py
View File

@@ -47,5 +47,5 @@ categories = [
microcode = ""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/__init__.py
View File

@@ -48,5 +48,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/arithmetic/__init__.py
View File

@@ -48,5 +48,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/compare_and_test/__init__.py
View File

@@ -45,5 +45,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/control/__init__.py
View File

@@ -46,5 +46,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/data_transfer_and_conversion/__init__.py
View File

@@ -46,5 +46,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/load_constants/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

2
src/arch/x86/isa/insts/x87/stack_management/__init__.py
View File

@@ -39,5 +39,5 @@ microcode = """
# X86 microcode
"""
for category in categories:
exec("from . import %s as cat" % category)
exec(f"from . import {category} as cat")
microcode += cat.microcode

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