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misc: Replace M5_UNREACHABLE with GEM5_UNREACHABLE.

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Change-Id: Id4cbdb8ae58c1077411e01579ac3a2d72b3b7465
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45238
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-05-08 20:44:51 -07:00
parent e92f64b0b7
commit c480558532
11 changed files with 70 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

82
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -108,7 +108,7 @@ namespace Aarch64
case 0x3:
return new SubXImmCc(machInst, rdzr, rnsp, imm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x4:
@@ -152,7 +152,7 @@ namespace Aarch64
case 0x3:
return new AndXImmCc(machInst, rdzr, rn, imm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x5:
@@ -171,7 +171,7 @@ namespace Aarch64
case 0x3:
return new Movk(machInst, rdzr, imm16, hw * 16);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x6:
@@ -187,7 +187,7 @@ namespace Aarch64
case 0x3:
return new Unknown64(machInst);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x7:
{
@@ -520,7 +520,7 @@ namespace Aarch64
}
break;
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
} else if (bits(machInst, 25) == 0x1) {
uint8_t opc = bits(machInst, 24, 21);
@@ -720,7 +720,7 @@ namespace Aarch64
else
return new LDADDLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x1:
switch(size_ar){
@@ -781,7 +781,7 @@ namespace Aarch64
case 0xf:
return new LDCLRLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x2:
switch(size_ar){
@@ -842,7 +842,7 @@ namespace Aarch64
case 0xf:
return new LDEORLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x3:
switch(size_ar){
@@ -903,7 +903,7 @@ namespace Aarch64
case 0xf:
return new LDSETLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x4:
switch(size_ar){
@@ -964,7 +964,7 @@ namespace Aarch64
case 0xf:
return new LDSMAXLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x5:
switch(size_ar){
@@ -1025,7 +1025,7 @@ namespace Aarch64
case 0xf:
return new LDSMINLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x6:
switch(size_ar){
@@ -1086,7 +1086,7 @@ namespace Aarch64
case 0xf:
return new LDUMAXLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x7:
switch(size_ar){
@@ -1147,7 +1147,7 @@ namespace Aarch64
case 0xf:
return new LDUMINLA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
default:
return new Unknown64(machInst);
@@ -1190,7 +1190,7 @@ namespace Aarch64
case 0x3:
return new STXRX64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x1:
switch (size) {
@@ -1203,7 +1203,7 @@ namespace Aarch64
case 0x3:
return new STLXRX64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x2:
switch (size) {
@@ -1216,7 +1216,7 @@ namespace Aarch64
case 0x3:
return new STXPX64(machInst, rs, rt, rt2, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x3:
@@ -1230,7 +1230,7 @@ namespace Aarch64
case 0x3:
return new STLXPX64(machInst, rs, rt, rt2, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x4:
@@ -1244,7 +1244,7 @@ namespace Aarch64
case 0x3:
return new LDXRX64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x5:
switch (size) {
@@ -1257,7 +1257,7 @@ namespace Aarch64
case 0x3:
return new LDAXRX64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x6:
switch (size) {
@@ -1270,7 +1270,7 @@ namespace Aarch64
case 0x3:
return new LDXPX64(machInst, rt, rt2, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x7:
switch (size) {
@@ -1283,7 +1283,7 @@ namespace Aarch64
case 0x3:
return new LDAXPX64(machInst, rt, rt2, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x9:
switch (size) {
@@ -1296,7 +1296,7 @@ namespace Aarch64
case 0x3:
return new STLRX64(machInst, rt, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0xa:
switch (size) {
@@ -1309,7 +1309,7 @@ namespace Aarch64
case 0x3:
return new CAS64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0xb:
switch (size) {
@@ -1322,7 +1322,7 @@ namespace Aarch64
case 0x3:
return new CASL64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0xd:
switch (size) {
@@ -1335,7 +1335,7 @@ namespace Aarch64
case 0x3:
return new LDARX64(machInst, rt, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0xe:
switch (size) {
@@ -1348,7 +1348,7 @@ namespace Aarch64
case 0x3:
return new CASA64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0xf:
switch (size) {
@@ -1361,7 +1361,7 @@ namespace Aarch64
case 0x3:
return new CASAL64(machInst, rt, rnsp, rs);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
default:
return new Unknown64(machInst);
@@ -1543,7 +1543,7 @@ namespace Aarch64
case 0x3:
return new LDAPRX64(machInst, rt, rnsp);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
} else {
return decodeAtomicArithOp(machInst);
@@ -1575,7 +1575,7 @@ namespace Aarch64
return new LDRAB_PRE(machInst, rt,
makeSP(rn), imm10);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x2:
@@ -1902,12 +1902,12 @@ namespace Aarch64
}
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
return new FailUnimplemented("Unhandled Case1", machInst);
}
@@ -1955,7 +1955,7 @@ namespace Aarch64
case 0x7:
return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x1:
@@ -1983,7 +1983,7 @@ namespace Aarch64
case 0x3:
return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
} else {
if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4)
@@ -2008,7 +2008,7 @@ namespace Aarch64
case 0x3:
return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
}
@@ -2036,7 +2036,7 @@ namespace Aarch64
case 0x3:
return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x1:
@@ -2091,7 +2091,7 @@ namespace Aarch64
case 0x3:
return new Csneg64(machInst, rdzr, rn, rm, cond);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x3:
@@ -2247,7 +2247,7 @@ namespace Aarch64
}
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x3:
@@ -2289,7 +2289,7 @@ namespace Aarch64
}
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
return new FailUnimplemented("Unhandled Case2", machInst);
}
@@ -2835,7 +2835,7 @@ namespace Aarch64
return new Unknown64(machInst);
}
}
M5_UNREACHABLE;
GEM5_UNREACHABLE;
case 0x1:
{
if (bits(machInst, 31) ||
@@ -2941,10 +2941,10 @@ namespace Aarch64
return new Unknown64(machInst);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
}};

12
src/arch/arm/isa/formats/data.isa
View File

@@ -605,7 +605,7 @@ def format Thumb32DataProcReg() {{
return new MovRegRegCc(machInst, rd,
INTREG_ZERO, rn, rm, ROR);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
} else if (bits(op2, 3) == 0) {
return new Unknown(machInst);
@@ -921,7 +921,7 @@ def format Thumb16ShiftAddSubMoveCmp() {{
return new SubImmCc(machInst, rd, rn, imm3, true);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x4:
if (machInst.itstateMask) {
@@ -944,7 +944,7 @@ def format Thumb16ShiftAddSubMoveCmp() {{
return new SubImmCc(machInst, rd8, rd8, imm8, true);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''
@@ -1049,7 +1049,7 @@ def format Thumb16DataProcessing() {{
return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''
@@ -1080,7 +1080,7 @@ def format Thumb16SpecDataAndBx() {{
COND_UC);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''
@@ -1198,7 +1198,7 @@ def format Thumb16Misc() {{
case 0x3:
return new Uxtb(machInst, rd, 0, rm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x1:

10
src/arch/arm/isa/formats/fp.isa
View File

@@ -483,7 +483,7 @@ let {{
return new VbifD<uint64_t>(machInst, vd, vn, vm);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
} else {
switch (size) {
@@ -526,7 +526,7 @@ let {{
machInst, vd, vn, vm);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
}
@@ -702,7 +702,7 @@ let {{
case 0x3:
return new Unknown(machInst);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
} else {
switch (size) {
@@ -715,7 +715,7 @@ let {{
case 0x3:
return new SHA1SU0(machInst, vd, vn, vm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
}
@@ -2093,7 +2093,7 @@ let {{
return new VLdmStm(machInst, rn, vd, single,
true, true, true, offset);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
case 0x2:

4
src/arch/arm/isa/formats/mem.isa
View File

@@ -608,7 +608,7 @@ def format Thumb32StoreSingle() {{
case 7:
return new %(imm_puw)s(machInst, RT, RN, true, imm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''
@@ -1074,7 +1074,7 @@ def format Thumb16MemReg() {{
case 0x7:
return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''

14
src/arch/arm/isa/formats/mult.isa
View File

@@ -86,7 +86,7 @@ def format ArmMultAndMultAcc() {{
return new Smlal(machInst, ra, rd, rn, rm);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''
@@ -113,7 +113,7 @@ def format ArmHalfWordMultAndMultAcc() {{
case 0x3:
return new SmlattCc(machInst, rd, rn, rm, ra);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x1:
if (op) {
@@ -140,7 +140,7 @@ def format ArmHalfWordMultAndMultAcc() {{
case 0x3:
return new Smlaltt(machInst, ra, rd, rn, rm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x3:
switch (bits(machInst, 6, 5)) {
@@ -153,10 +153,10 @@ def format ArmHalfWordMultAndMultAcc() {{
case 0x3:
return new Smultt(machInst, rd, rn, rm);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''
@@ -209,7 +209,7 @@ def format Thumb32MulMulAccAndAbsDiff() {{
return new SmlattCc(machInst, rd, rn, rm, ra);
}
}
M5_UNREACHABLE;
GEM5_UNREACHABLE;
case 0x2:
if (ra == 0xf) {
if (bits(machInst, 4)) {
@@ -281,7 +281,7 @@ def format Thumb32MulMulAccAndAbsDiff() {{
return new Usada8(machInst, rd, rn, rm, ra);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
}
'''

8
src/arch/arm/isa/formats/neon64.isa
View File

@@ -184,7 +184,7 @@ namespace Aarch64
return new OrnDX<uint64_t>(machInst, vd, vn, vm);
}
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x04:
if (size == 0x3)
@@ -2242,7 +2242,7 @@ namespace Aarch64
case 0x3:
return new Unknown64(machInst);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x1a:
if (size < 0x2)
@@ -2322,7 +2322,7 @@ namespace Aarch64
case 0x3:
return new Unknown64(machInst);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x34:
switch (size) {
@@ -2335,7 +2335,7 @@ namespace Aarch64
case 0x3:
return new Unknown64(machInst);
default:
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
case 0x36:
if (size != 0x1) {

2
src/arch/arm/regs/misc.cc
View File

@@ -2870,7 +2870,7 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
// S3_<op1>_11_<Cm>_<op2>
return MISCREG_IMPDEF_UNIMPL;
}
M5_UNREACHABLE;
GEM5_UNREACHABLE;
case 12:
switch (op1) {
case 0:

2
src/arch/isa_parser/isa_parser.py
View File

@@ -1257,7 +1257,7 @@ StaticInstPtr
# just wrap the decoding code from the block as a case in the
# outer switch statement.
codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
'M5_UNREACHABLE;\n')
'GEM5_UNREACHABLE;\n')
codeObj.has_decode_default = (case_list == ['default:'])
t[0] = codeObj

2
src/base/cprintf.cc
View File

@@ -238,7 +238,7 @@ Print::processFlag()
break;
case '%':
M5_UNREACHABLE;
GEM5_UNREACHABLE;
break;
default:

2
src/dev/arm/gic_v3_distributor.cc
View File

@@ -1155,7 +1155,7 @@ Gicv3Distributor::getIntGroup(int int_id) const
}
}
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
void

2
src/dev/arm/gic_v3_redistributor.cc
View File

@@ -988,7 +988,7 @@ Gicv3Redistributor::getIntGroup(int int_id) const
}
}
M5_UNREACHABLE;
GEM5_UNREACHABLE;
}
void