arch: Get rid of global maximums for numbers of source/dest/misc regs.

Change-Id: I6881572daedf0f0e9ff6aee4f174671d02ef743d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/SConscript

@@ -185,8 +185,6 @@ def ISADesc(desc, decoder_splits=1, exec_splits=1):
     add_gen('exec-g.cc.inc')
     add_gen('exec-ns.cc.inc')
 
-    add_gen('max_inst_regs.hh')
-
 
     # These generated files are also top level sources.
     def source_gen(name):

src/arch/arm/registers.hh

@@ -42,22 +42,14 @@
 #define __ARCH_ARM_REGISTERS_HH__
 
 #include "arch/arm/ccregs.hh"
-#include "arch/arm/generated/max_inst_regs.hh"
 #include "arch/arm/intregs.hh"
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 
-namespace ArmISA {
-
-
-// For a predicated instruction, we need all the
-// destination registers to also be sources
-const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
-    ArmISAInst::MaxInstSrcRegs;
-using ArmISAInst::MaxInstDestRegs;
-using ArmISAInst::MaxMiscDestRegs;
+namespace ArmISA
+{
 
 // Number of VecElem per Vector Register considering only pre-SVE
 // Advanced SIMD registers.

src/arch/isa_parser/isa_parser.py

@@ -526,8 +526,6 @@ class ISAParser(Grammar):
         symbols = ('makeList', 're')
         self.exportContext = dict([(s, eval(s)) for s in symbols])
 
-        self.maxInstSrcRegs = 0
-        self.maxInstDestRegs = 0
         self.maxMiscDestRegs = 0
 
     def operandsRE(self):
@@ -677,13 +675,6 @@ class ISAParser(Grammar):
                 print('#include "%s"' % fn, file=f)
                 print('}', file=f)
 
-        # max_inst_regs.hh
-        self.update('max_inst_regs.hh',
-                    '''namespace %(namespace)s {
-    const int MaxInstSrcRegs = %(maxInstSrcRegs)d;
-    const int MaxInstDestRegs = %(maxInstDestRegs)d;
-    const int MaxMiscDestRegs = %(maxMiscDestRegs)d;\n}\n''' % self)
-
     scaremonger_template ='''// DO NOT EDIT
 // This file was automatically generated from an ISA description:
 //   %(filename)s

src/arch/isa_parser/operand_list.py

@@ -133,11 +133,6 @@ class OperandList(object):
         self.predRead = any(i.hasReadPred() for i in self.items)
         self.predWrite = any(i.hasWritePred() for i in self.items)
 
-        parser.maxInstSrcRegs = max(parser.maxInstSrcRegs, self.numSrcRegs)
-        parser.maxInstDestRegs = max(parser.maxInstDestRegs, self.numDestRegs)
-        parser.maxMiscDestRegs = max(parser.maxMiscDestRegs,
-                                     self.numMiscDestRegs)
-
         # now make a final pass to finalize op_desc fields that may depend
         # on the register enumeration
         for op_desc in self.items:

src/arch/mips/registers.hh

@@ -32,7 +32,6 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/mips/generated/max_inst_regs.hh"
 #include "base/logging.hh"
 #include "base/types.hh"
 
@@ -41,10 +40,6 @@ class ThreadContext;
 namespace MipsISA
 {
 
-using MipsISAInst::MaxInstSrcRegs;
-using MipsISAInst::MaxInstDestRegs;
-using MipsISAInst::MaxMiscDestRegs;
-
 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
 const int NumIntSpecialRegs = 9;

src/arch/power/registers.hh

@@ -31,18 +31,11 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/power/generated/max_inst_regs.hh"
 #include "arch/power/miscregs.hh"
 #include "base/types.hh"
 
-namespace PowerISA {
-
-using PowerISAInst::MaxInstSrcRegs;
-using PowerISAInst::MaxInstDestRegs;
-
-// Power writes a misc register outside of the isa parser, so it can't
-// be detected by it. Manually add it here.
-const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
+namespace PowerISA
+{
 
 // Not applicable to Power
 using VecElem = ::DummyVecElem;

src/arch/riscv/registers.hh

@@ -52,15 +52,11 @@
 #include "arch/generic/types.hh"
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/riscv/generated/max_inst_regs.hh"
 #include "base/bitunion.hh"
 #include "base/types.hh"
 
-namespace RiscvISA {
-
-using RiscvISAInst::MaxInstSrcRegs;
-using RiscvISAInst::MaxInstDestRegs;
-const int MaxMiscDestRegs = 2;
+namespace RiscvISA
+{
 
 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;

src/arch/sparc/registers.hh

@@ -31,7 +31,6 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/sparc/generated/max_inst_regs.hh"
 #include "arch/sparc/miscregs.hh"
 #include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"
@@ -39,10 +38,6 @@
 namespace SparcISA
 {
 
-using SparcISAInst::MaxInstSrcRegs;
-using SparcISAInst::MaxInstDestRegs;
-using SparcISAInst::MaxMiscDestRegs;
-
 // Not applicable to SPARC
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/x86/registers.hh

@@ -41,7 +41,6 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/x86/generated/max_inst_regs.hh"
 #include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/ccr.hh"
 #include "arch/x86/regs/misc.hh"
@@ -49,9 +48,7 @@
 
 namespace X86ISA
 {
-using X86ISAInst::MaxInstSrcRegs;
-using X86ISAInst::MaxInstDestRegs;
-using X86ISAInst::MaxMiscDestRegs;
+
 const int NumMiscRegs = NUM_MISCREGS;
 
 const int NumIntArchRegs = NUM_INTREGS;