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arch: Split up src/dest register ID creation.

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This will allow us to selectively change the RegID of an operand to, for
instance, convert it to InvalidRegClass just as a source so it never
actually gets read.

Change-Id: I9f8117cbb2088f8150080f815cdb5cb84bd7218e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49747
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-22 21:32:11 -07:00
parent 2af227c32a
commit 886154b958
1 changed files with 10 additions and 4 deletions
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14
src/arch/isa_parser/operand_types.py
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@@ -143,6 +143,12 @@ class Operand(object):
def regId(self):
return f'RegId({self.reg_class}, {self.reg_spec})'
def srcRegId(self):
return self.regId()
def destRegId(self):
return self.regId()
def __init__(self, parser, full_name, ext, is_src, is_dest):
self.parser = parser
self.full_name = full_name
@@ -238,13 +244,13 @@ class RegOperand(Operand):
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % self.regId()
c_src = self.src_reg_constructor % self.srcRegId()
if self.hasReadPred():
c_src = '\n\tif (%s) {%s\n\t}' % \
(self.read_predicate, c_src)
if self.is_dest:
c_dest = self.dst_reg_constructor % self.regId()
c_dest = self.dst_reg_constructor % self.destRegId()
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
if self.hasWritePred():
c_dest = '\n\tif (%s) {%s\n\t}' % \
@@ -499,10 +505,10 @@ class ControlRegOperand(Operand):
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % self.regId()
c_src = self.src_reg_constructor % self.srcRegId()
if self.is_dest:
c_dest = self.dst_reg_constructor % self.regId()
c_dest = self.dst_reg_constructor % self.destRegId()
return c_src + c_dest