derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

misc: Use python 3's argumentless super().

Browse Source 
When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-28 16:16:07 -07:00
parent e4cff7b5ca
commit ba5f68db3d
142 changed files with 301 additions and 370 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/SConscript
View File

@@ -94,7 +94,7 @@ class PySource(SourceFile):
def __init__(self, package, source, tags=None, add_tags=None):
'''specify the python package, the source file, and any tags'''
super(PySource, self).__init__(source, tags, add_tags)
super().__init__(source, tags, add_tags)
basename = os.path.basename(self.filename)
modname, ext = os.path.splitext(basename)
@@ -145,7 +145,7 @@ class SimObject(PySource):
def __init__(self, source, tags=None, add_tags=None):
'''Specify the source file and any tags (automatically in
the m5.objects package)'''
super(SimObject, self).__init__('m5.objects', source, tags, add_tags)
super().__init__('m5.objects', source, tags, add_tags)
if self.fixed:
raise AttributeError("Too late to call SimObject now.")
@@ -226,7 +226,7 @@ class TopLevelMeta(type):
def __init__(cls, name, bases, d):
TopLevelMeta.all.append(cls)
super(TopLevelMeta, cls).__init__(name, bases, d)
super().__init__(name, bases, d)
cls.all = []
class TopLevelBase(object, metaclass=TopLevelMeta):
@@ -235,7 +235,7 @@ class TopLevelBase(object, metaclass=TopLevelMeta):
def __init__(self, target, *srcs_and_filts):
'''Specify the target name and any sources. Sources that are
not SourceFiles are evalued with Source().'''
super(TopLevelBase, self).__init__()
super().__init__()
self.all.append(self)
self.target = target
@@ -325,7 +325,7 @@ class Gem5(Executable):
env.Depends(date_obj, objs)
objs.append(date_obj)
return super(Gem5, self).declare(env, objs)
return super().declare(env, objs)
class GTest(Executable):
@@ -334,7 +334,7 @@ class GTest(Executable):
def __init__(self, *srcs_and_filts, **kwargs):
if not kwargs.pop('skip_lib', False):
srcs_and_filts = srcs_and_filts + (with_tag('gtest lib'),)
super(GTest, self).__init__(*srcs_and_filts)
super().__init__(*srcs_and_filts)
@classmethod
def declare_all(cls, env):
@@ -345,10 +345,10 @@ class GTest(Executable):
env.Append(CPPFLAGS=env['GTEST_CPPFLAGS'])
env['GTEST_OUT_DIR'] = \
Dir(env['BUILDDIR']).Dir('unittests.${ENV_LABEL}')
return super(GTest, cls).declare_all(env)
return super().declare_all(env)
def declare(self, env):
binary, stripped = super(GTest, self).declare(env)
binary, stripped = super().declare(env)
out_dir = env['GTEST_OUT_DIR']
xml_file = out_dir.Dir(str(self.dir)).File(self.target + '.xml')
@@ -520,7 +520,7 @@ SimObject.fixed = True
class SimpleModuleLoader(importlib.abc.Loader):
'''A simple wrapper which delegates setting up a module to a function.'''
def __init__(self, executor):
super(SimpleModuleLoader, self).__init__()
super().__init__()
self.executor = executor
def create_module(self, spec):
return None
@@ -530,7 +530,7 @@ class SimpleModuleLoader(importlib.abc.Loader):
class M5MetaPathFinder(importlib.abc.MetaPathFinder):
def __init__(self, modules):
super(M5MetaPathFinder, self).__init__()
super().__init__()
self.modules = modules
self.installed = set()

14
src/arch/arm/fastmodel/FastModel.py
View File

@@ -47,7 +47,7 @@ class AmbaTargetSocket(Port):
peer_role = AMBA_TARGET_ROLE(width)
Port.compat(my_role, peer_role)
super(AmbaTargetSocket, self).__init__(my_role, desc)
super().__init__(my_role, desc)
class VectorAmbaTargetSocket(VectorPort):
def __init__(self, width, desc):
@@ -55,7 +55,7 @@ class VectorAmbaTargetSocket(VectorPort):
peer_role = AMBA_TARGET_ROLE(width)
Port.compat(my_role, peer_role)
super(VectorAmbaTargetSocket, self).__init__(my_role, desc)
super().__init__(my_role, desc)
class AmbaInitiatorSocket(Port):
def __init__(self, width, desc):
@@ -63,8 +63,7 @@ class AmbaInitiatorSocket(Port):
peer_role = AMBA_INITIATOR_ROLE(width)
Port.compat(my_role, peer_role)
super(AmbaInitiatorSocket, self).__init__(
my_role, desc, is_source=True)
super().__init__(my_role, desc, is_source=True)
class VectorAmbaInitiatorSocket(VectorPort):
def __init__(self, width, desc):
@@ -72,8 +71,7 @@ class VectorAmbaInitiatorSocket(VectorPort):
peer_role = AMBA_INITIATOR_ROLE(width)
Port.compat(my_role, peer_role)
super(VectorAmbaInitiatorSocket, self).__init__(
my_role, desc, is_source=True)
super().__init__(my_role, desc, is_source=True)
class ScRequestPort(Port):
def __init__(self, desc, port_type):
@@ -81,7 +79,7 @@ class ScRequestPort(Port):
peer_role = SC_RESPONSE_PORT_ROLE(port_type)
Port.compat(my_role, peer_role)
super(ScRequestPort, self).__init__(my_role, desc)
super().__init__(my_role, desc)
class ScResponsePort(Port):
def __init__(self, desc, port_type):
@@ -89,7 +87,7 @@ class ScResponsePort(Port):
peer_role = SC_REQUEST_PORT_ROLE(port_type)
Port.compat(my_role, peer_role)
super(ScResponsePort, self).__init__(my_role, desc)
super().__init__(my_role, desc)
class AmbaToTlmBridge64(SystemC_ScModule):
type = 'AmbaToTlmBridge64'

9
src/arch/arm/fastmodel/GIC/FastModelGIC.py
View File

@@ -50,18 +50,15 @@ Port.compat(GICV3_COMMS_TARGET_ROLE, GICV3_COMMS_INITIATOR_ROLE)
class Gicv3CommsTargetSocket(Port):
def __init__(self, desc):
super(Gicv3CommsTargetSocket, self).__init__(
GICV3_COMMS_INITIATOR_ROLE, desc)
super().__init__(GICV3_COMMS_INITIATOR_ROLE, desc)
class Gicv3CommsInitiatorSocket(Port):
def __init__(self, desc):
super(Gicv3CommsInitiatorSocket, self).__init__(
GICV3_COMMS_TARGET_ROLE, desc, is_source=True)
super().__init__(GICV3_COMMS_TARGET_ROLE, desc, is_source=True)
class VectorGicv3CommsInitiatorSocket(VectorPort):
def __init__(self, desc):
super(VectorGicv3CommsInitiatorSocket, self).__init__(
GICV3_COMMS_TARGET_ROLE, desc, is_source=True)
super().__init__(GICV3_COMMS_TARGET_ROLE, desc, is_source=True)
class SCFastModelGIC(SystemC_ScModule):

12
src/arch/arm/fastmodel/SConscript
View File

@@ -149,8 +149,7 @@ class ProjectFileParser(Grammar):
class StringParam(Param):
def __init__(self, name, value):
super(ProjectFileParser.StringParam, self).__init__(
is_object=False)
super().__init__(is_object=False)
self.name = name
self.value = value
@@ -160,8 +159,7 @@ class ProjectFileParser(Grammar):
class ObjectParam(Param):
def __init__(self, type_name, name, params):
super(ProjectFileParser.ObjectParam, self).__init__(
is_object=True)
super().__init__(is_object=True)
self.type_name = type_name
self.name = name
self.params = params
@@ -362,13 +360,13 @@ class ArmFastModelBin(Executable):
sources = list(filter(not_component, components_and_sources))
self.components = components
super(ArmFastModelBin, self).__init__(target, *sources)
super().__init__(target, *sources)
@classmethod
def declare_all(cls, env):
env = env.Clone()
env.Prepend(LIBS=env['STATIC_LIB'][0])
super(ArmFastModelBin, cls).declare_all(env)
super().declare_all(env)
def declare(self, env):
env = env.Clone()
@@ -383,7 +381,7 @@ class ArmFastModelBin(Executable):
for component in self.components:
component.prepare_env(env)
binary = super(ArmFastModelBin, self).declare(env, objs)[0]
binary = super().declare(env, objs)[0]
# We need a copy of the simulation engine lib alongside the executable
# so that the license check works properly.

2
src/arch/arm/isa/arminstobjparams.isa
View File

@@ -29,7 +29,7 @@ let {{
class ArmInstObjParams(InstObjParams):
def __init__(self, *args, **kwargs):
super(ArmInstObjParams, self).__init__(*args, **kwargs)
super().__init__(*args, **kwargs)
self.padSrcRegIdx(self.operands.numDestRegs)
}};

8
src/arch/arm/isa/insts/amo64.isa
View File

@@ -65,7 +65,7 @@ let {{
def __init__(self, mnem, Name, size=4, user=False, flavor="normal",
unsign=True, top = False, paired=False, ret_op=True):
super(AtomicInst64, self).__init__()
super().__init__()
self.name= mnem
self.Name = Name
@@ -166,7 +166,7 @@ let {{
execBase = 'AmoOp'
def __init__(self, *args, **kargs):
super(AtomicSingleOp, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.suffix = buildMemSuffix(not self.unsign, self.size)
if self.size == 8:
self.res = 'XResult_ud' #if self.unsign else 'XResult_sd'
@@ -267,7 +267,7 @@ let {{
execBase = 'AmoOp'
def __init__(self, *args, **kargs):
super(CasPair64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.paired = True
self.offset = ""
if self.size == 8:
@@ -386,7 +386,7 @@ let {{
execBase = 'AmoOp'
def __init__(self, *args, **kargs):
super(AtomicArithmeticSingleOp, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
store_res = "%(utype)s unsMem = Mem%(suffix)s"
if self.size != 8:

12
src/arch/arm/isa/insts/ldr.isa
View File

@@ -47,7 +47,7 @@ let {{
def __init__(self, mnem, post, add, writeback,
size=4, sign=False, user=False, flavor="normal"):
super(LoadInst, self).__init__()
super().__init__()
self.name = mnem
self.post = post
@@ -89,7 +89,7 @@ let {{
decConstBase = 'Rfe'
def __init__(self, mnem, post, add, writeback):
super(RfeInst, self).__init__(mnem, post, add, writeback)
super().__init__(mnem, post, add, writeback)
self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
self.memFlags.append("ArmISA::MMU::AlignWord")
@@ -126,7 +126,7 @@ let {{
class LoadImmInst(LoadInst):
def __init__(self, *args, **kargs):
super(LoadImmInst, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = self.op + " imm"
if self.add:
@@ -140,7 +140,7 @@ let {{
class LoadRegInst(LoadInst):
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
" shiftType, OptShiftRmCondCodesC)"
if self.add:
@@ -154,7 +154,7 @@ let {{
class LoadSingle(LoadInst):
def __init__(self, *args, **kargs):
super(LoadSingle, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
# Build the default class name
self.Name = self.nameFunc(self.post, self.add, self.writeback,
@@ -240,7 +240,7 @@ let {{
class LoadDouble(LoadInst):
def __init__(self, *args, **kargs):
super(LoadDouble, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
# Build the default class name
self.Name = self.nameFunc(self.post, self.add, self.writeback)

8
src/arch/arm/isa/insts/ldr64.isa
View File

@@ -47,7 +47,7 @@ let {{
def __init__(self, mnem, Name, size=4, sign=False, user=False,
literal=False, flavor="normal", top=False):
super(LoadInst64, self).__init__()
super().__init__()
self.name = mnem
self.Name = Name
@@ -175,14 +175,14 @@ let {{
class LoadImmInst64(LoadInst64):
def __init__(self, *args, **kargs):
super(LoadImmInst64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = " + imm"
self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);"
class LoadRegInst64(LoadInst64):
def __init__(self, *args, **kargs):
super(LoadRegInst64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = " + extendReg64(XOffset, type, shiftAmt, 64)"
self.wbDecl = \
@@ -191,7 +191,7 @@ let {{
class LoadRawRegInst64(LoadInst64):
def __init__(self, *args, **kargs):
super(LoadRawRegInst64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = ""
class LoadSingle64(LoadInst64):

16
src/arch/arm/isa/insts/str.isa
View File

@@ -47,7 +47,7 @@ let {{
def __init__(self, mnem, post, add, writeback, size=4,
sign=False, user=False, flavor="normal"):
super(StoreInst, self).__init__()
super().__init__()
self.name = mnem
self.post = post
@@ -88,7 +88,7 @@ let {{
decConstBase = 'Srs'
def __init__(self, mnem, post, add, writeback):
super(SrsInst, self).__init__()
super().__init__()
self.name = mnem
self.post = post
self.add = add
@@ -145,7 +145,7 @@ let {{
class StoreImmInst(StoreInst):
def __init__(self, *args, **kargs):
super(StoreImmInst, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = self.op + " imm"
if self.add:
@@ -155,7 +155,7 @@ let {{
class StoreRegInst(StoreInst):
def __init__(self, *args, **kargs):
super(StoreRegInst, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
" shiftType, OptShiftRmCondCodesC)"
if self.add:
@@ -169,7 +169,7 @@ let {{
class StoreSingle(StoreInst):
def __init__(self, *args, **kargs):
super(StoreSingle, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
# Build the default class name
self.Name = self.nameFunc(self.post, self.add, self.writeback,
@@ -235,7 +235,7 @@ let {{
nameFunc = staticmethod(storeImmClassName)
def __init__(self, *args, **kargs):
super(StoreImmEx, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.codeBlobs["postacc_code"] = \
"Result = !writeResult; SevMailbox = 1; LLSCLock = 0;"
@@ -254,7 +254,7 @@ let {{
class StoreDouble(StoreInst):
def __init__(self, *args, **kargs):
super(StoreDouble, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
# Build the default class name
self.Name = self.nameFunc(self.post, self.add, self.writeback)
@@ -321,7 +321,7 @@ let {{
nameFunc = staticmethod(storeDoubleImmClassName)
def __init__(self, *args, **kargs):
super(StoreDoubleImmEx, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.codeBlobs["postacc_code"] = \
"Result = !writeResult; SevMailbox = 1; LLSCLock = 0;"

12
src/arch/arm/isa/insts/str64.isa
View File

@@ -47,7 +47,7 @@ let {{
def __init__(self, mnem, Name, size=4, user=False, flavor="normal",
top = False):
super(StoreInst64, self).__init__()
super().__init__()
self.name = mnem
self.Name = Name
@@ -143,14 +143,14 @@ let {{
class StoreImmInst64(StoreInst64):
def __init__(self, *args, **kargs):
super(StoreImmInst64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = "+ imm"
self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);"
class StoreRegInst64(StoreInst64):
def __init__(self, *args, **kargs):
super(StoreRegInst64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = "+ extendReg64(XOffset, type, shiftAmt, 64)"
self.wbDecl = \
@@ -159,7 +159,7 @@ let {{
class StoreRawRegInst64(StoreInst64):
def __init__(self, *args, **kargs):
super(StoreRawRegInst64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.offset = ""
class StoreSingle64(StoreInst64):
@@ -283,7 +283,7 @@ let {{
post = False
execBase = 'StoreEx64'
def __init__(self, *args, **kargs):
super(StoreEx64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.codeBlobs["postacc_code"] = \
"XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;"
@@ -350,7 +350,7 @@ let {{
post = False
writeback = False
def __init__(self, *args, **kargs):
super(StoreImmDEx64, self).__init__(*args, **kargs)
super().__init__(*args, **kargs)
self.codeBlobs["postacc_code"] = \
"XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;"

5
src/arch/isa_parser/isa_parser.py
View File

@@ -482,7 +482,7 @@ class InstObjParams(object):
class ISAParser(Grammar):
def __init__(self, output_dir):
super(ISAParser, self).__init__()
super().__init__()
self.output_dir = output_dir
self.filename = None # for output file watermarking/scaremongering
@@ -1436,8 +1436,7 @@ StaticInstPtr
# Create a wrapper class that allows us to grab the current parser.
class InstObjParamsWrapper(InstObjParams):
def __init__(iop, *args, **kwargs):
super(InstObjParamsWrapper, iop).__init__(
self, *args, **kwargs)
super().__init__(self, *args, **kwargs)
self.exportContext['InstObjParams'] = InstObjParamsWrapper
self.exportContext.update(self.templateMap)

6
src/arch/isa_parser/operand_types.py
View File

@@ -449,7 +449,7 @@ class VecRegOperand(Operand):
return wb
def finalize(self, predRead, predWrite):
super(VecRegOperand, self).finalize(predRead, predWrite)
super().finalize(predRead, predWrite)
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
@@ -585,7 +585,7 @@ class VecPredRegOperand(Operand):
return wb
def finalize(self, predRead, predWrite):
super(VecPredRegOperand, self).finalize(predRead, predWrite)
super().finalize(predRead, predWrite)
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
@@ -738,7 +738,7 @@ class MemOperand(Operand):
class PCStateOperand(Operand):
def __init__(self, parser, *args, **kwargs):
super(PCStateOperand, self).__init__(parser, *args, **kwargs)
super().__init__(parser, *args, **kwargs)
self.parser = parser
def makeConstructor(self, predRead, predWrite):

6
src/arch/micro_asm.py
View File

@@ -70,7 +70,7 @@ class Rom_Macroop(object):
class Rom(Micro_Container):
def __init__(self, name):
super(Rom, self).__init__(name)
super().__init__(name)
self.externs = {}
##########################################################################
@@ -96,14 +96,14 @@ class Statement(object):
class Microop(Statement):
def __init__(self):
super(Microop, self).__init__()
super().__init__()
self.mnemonic = ""
self.labels = []
self.is_microop = True
class Directive(Statement):
def __init__(self):
super(Directive, self).__init__()
super().__init__()
self.name = ""
self.is_directive = True

2
src/arch/micro_asm_test.py
View File

@@ -59,7 +59,7 @@ class TestMacroop(Combinational_Macroop):
print(message)
def __init__(self, name):
super(TestMacroop, self).__init__(name)
super().__init__(name)
self.directives = {
"tweak": self.tweak,
"untweak": self.untweak,

2
src/arch/x86/isa/macroop.isa
View File

@@ -158,7 +158,7 @@ let {{
self.control_indirect = True
def __init__(self, name):
super(X86Macroop, self).__init__(name)
super().__init__(name)
self.directives = {
"adjust_env" : self.setAdjustEnv,
"adjust_imm" : self.adjustImm,

4
src/arch/x86/isa/microops/base.isa
View File

@@ -89,7 +89,7 @@ let {{
def __init__(self, it):
self.value = next(it)
super(ImmOp, self).__init__()
super().__init__()
def ctor_args(self):
return str(self.value)
@@ -109,7 +109,7 @@ let {{
class RegisterOp(object):
def __init__(self, it):
self.idx = next(it)
super(RegisterOp, self).__init__()
super().__init__()
def ctor_args(self):
return str(self.idx)

5
src/arch/x86/isa/microops/debug.isa
View File

@@ -136,8 +136,7 @@ let {{
class MicroDebugChild(MicroDebug):
def __init__(self, message, flags=None):
super(MicroDebugChild, self).__init__(
name, fault_class, message, False, flags)
super().__init__(name, fault_class, message, False, flags)
microopClasses[name] = MicroDebugChild
@@ -148,7 +147,7 @@ let {{
class MicroDebugOnceChild(MicroDebug):
def __init__(self, message, flags=None):
super(MicroDebugOnceChild, self).__init__(
super().__init__(
name_once, fault_once_class, message, True, flags)
microopClasses[name_once] = MicroDebugOnceChild

10
src/arch/x86/isa/microops/fpop.isa
View File

@@ -175,7 +175,7 @@ let {{
abstract = dict['abstract']
del dict['abstract']
cls = super(FpOpMeta, mcls).__new__(mcls, Name, bases, dict)
cls = super().__new__(mcls, Name, bases, dict)
if not abstract:
cls.className = Name
cls.mnemonic = name
@@ -236,25 +236,25 @@ let {{
abstract = True
operand_types = ()
def __init__(self, **kwargs):
super(Fp0Op, self).__init__(**kwargs)
super().__init__(**kwargs)
class Fp1Op(FpOp):
abstract = True
operand_types = (FloatDestOp)
def __init__(self, reg1, **kwargs):
super(Fp1Op, self).__init__(reg1, **kwargs)
super().__init__(reg1, **kwargs)
class Fp2Op(FpOp):
abstract = True
operand_types = (FloatDestOp, FloatSrc1Op)
def __init__(self, reg1, reg2, **kwargs):
super(Fp2Op, self).__init__(reg1, reg2, **kwargs)
super().__init__(reg1, reg2, **kwargs)
class Fp3Op(FpOp):
abstract = True
operand_types = (FloatDestOp, FloatSrc1Op, FloatSrc2Op)
def __init__(self, reg1, reg2, reg3, **kwargs):
super(Fp3Op, self).__init__(reg1, reg2, reg3, **kwargs)
super().__init__(reg1, reg2, reg3, **kwargs)
class Movfp(Fp2Op):
code = 'FpDestReg_uqw = FpSrcReg1_uqw;'

14
src/arch/x86/isa/microops/ldstop.isa
View File

@@ -389,7 +389,7 @@ let {{
def __init__(self, data, segment, addr, disp,
dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
implicitStack, uncacheable):
super(LdStSplitOp, self).__init__(0, segment, addr, disp,
super().__init__(0, segment, addr, disp,
dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
implicitStack, uncacheable)
(self.dataLow, self.dataHi) = data
@@ -503,7 +503,7 @@ let {{
addressSize=addressSize,
atCPL0=False, prefetch=False, nonSpec=nonSpec,
implicitStack=implicitStack, uncacheable=False):
super(LoadOp, self).__init__(data, segment, addr,
super().__init__(data, segment, addr,
disp, dataSize, addressSize, mem_flags,
atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
self.className = Name
@@ -585,7 +585,7 @@ let {{
addressSize="env.addressSize",
atCPL0=False, prefetch=False, nonSpec=nonSpec,
implicitStack=False, uncacheable=False):
super(LoadOp, self).__init__(data, segment, addr,
super().__init__(data, segment, addr,
disp, dataSize, addressSize, mem_flags,
atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
self.className = Name
@@ -646,7 +646,7 @@ let {{
dataSize="env.dataSize", addressSize=addressSize,
atCPL0=False, nonSpec=False,
implicitStack=implicitStack, uncacheable=False):
super(StoreOp, self).__init__(data, segment, addr, disp,
super().__init__(data, segment, addr, disp,
dataSize, addressSize, mem_flags, atCPL0, False,
nonSpec, implicitStack, uncacheable)
self.className = Name
@@ -655,7 +655,7 @@ let {{
class StoreOp(MemNoDataOp):
def __init__(self, segment, addr, disp=0,
dataSize="env.dataSize", addressSize=addressSize):
super(StoreOp, self).__init__(segment, addr, disp,
super().__init__(segment, addr, disp,
dataSize, addressSize, mem_flags)
self.className = Name
self.mnemonic = name
@@ -720,7 +720,7 @@ let {{
addressSize="env.addressSize",
atCPL0=False, nonSpec=False, implicitStack=False,
uncacheable=False):
super(StoreOp, self).__init__(data, segment, addr, disp,
super().__init__(data, segment, addr, disp,
dataSize, addressSize, mem_flags, atCPL0, False,
nonSpec, implicitStack, uncacheable)
self.className = Name
@@ -748,7 +748,7 @@ let {{
class LeaOp(LdStOp):
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize", addressSize="env.addressSize"):
super(LeaOp, self).__init__(data, segment, addr, disp,
super().__init__(data, segment, addr, disp,
dataSize, addressSize, "0",
False, False, False, False, False)
self.className = "Lea"

22
src/arch/x86/isa/microops/mediaop.isa
View File

@@ -128,7 +128,7 @@ let {{
if not "op_class" in dict:
dict["op_class"] = None
cls = super(MediaOpMeta, mcls).__new__(mcls, Name, bases, dict)
cls = super().__new__(mcls, Name, bases, dict)
if not abstract:
cls.className = Name
cls.base_mnemonic = name
@@ -207,23 +207,23 @@ let {{
abstract = True
operand_types = ()
def __init__(self, **kwargs):
super(Media0Op, self).__init__(**kwargs)
super().__init__(**kwargs)
class Media2Op(MediaOp):
abstract = True
operand_types = (FloatDestOp, FloatSrc1Op)
def __init__(self, op1, op2, **kwargs):
super(Media2Op, self).__init__(op1, op2, **kwargs)
super().__init__(op1, op2, **kwargs)
class Media3Op(MediaOp):
abstract = True
operand_types = (FloatDestOp, FloatSrc1Op, FloatSrc2Op)
def __init__(self, op1, op2, op3, **kwargs):
super(Media3Op, self).__init__(op1, op2, op3, **kwargs)
super().__init__(op1, op2, op3, **kwargs)
class Mov2int(Media3Op):
def __init__(self, dest, src1, src2=0, **kwargs):
super(Mov2int, self).__init__(dest, src1, src2, **kwargs)
super().__init__(dest, src1, src2, **kwargs)
operand_types = (IntDestOp, FloatSrc1Op, Imm8Op)
op_class = 'SimdMiscOp'
code = '''
@@ -244,7 +244,7 @@ let {{
class Mov2fp(Media3Op):
def __init__(self, dest, src1, src2=0, **kwargs):
super(Mov2fp, self).__init__(dest, src1, src2, **kwargs)
super().__init__(dest, src1, src2, **kwargs)
operand_types = (FloatDestOp, IntSrc1Op, Imm8Op)
op_class = 'SimdMiscOp'
code = '''
@@ -445,7 +445,7 @@ let {{
class Mxor(Media3Op):
def __init__(self, dest, src1, src2):
super(Mxor, self).__init__(dest, src1, src2, size=1)
super().__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;
@@ -453,7 +453,7 @@ let {{
class Mor(Media3Op):
def __init__(self, dest, src1, src2):
super(Mor, self).__init__(dest, src1, src2, size=1)
super().__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = FpSrcReg1_uqw | FpSrcReg2_uqw;
@@ -461,7 +461,7 @@ let {{
class Mand(Media3Op):
def __init__(self, dest, src1, src2):
super(Mand, self).__init__(dest, src1, src2, size=1)
super().__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = FpSrcReg1_uqw & FpSrcReg2_uqw;
@@ -469,7 +469,7 @@ let {{
class Mandn(Media3Op):
def __init__(self, dest, src1, src2):
super(Mandn, self).__init__(dest, src1, src2, size=1)
super().__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = ~FpSrcReg1_uqw & FpSrcReg2_uqw;
@@ -1551,7 +1551,7 @@ let {{
class Emms(Media0Op):
def __init__(self):
super(Emms, self).__init__(size=2)
super().__init__(size=2)
op_class = 'FloatMiscOp'
code = 'FTW = 0xFFFF;'
}};

44
src/arch/x86/isa/microops/regop.isa
View File

@@ -279,7 +279,7 @@ let {{
abstract = dict['abstract']
del dict['abstract']
cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
cls = super().__new__(mcls, Name, bases, dict)
if abstract:
return cls
@@ -392,8 +392,7 @@ let {{
def __init__(self, dest, src1, src2, flags=None,
dataSize="env.dataSize"):
super(BasicRegOp, self).__init__(dest, src1, src2, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, src2, flags=flags, dataSize=dataSize)
class LogicRegOp(BasicRegOp):
abstract = True
@@ -451,15 +450,14 @@ let {{
def __init__(self, dest, src1=None, dataSize="env.dataSize"):
if not src1:
src1 = dest
super(RdRegOp, self).__init__(dest, src1, dataSize=dataSize)
super().__init__(dest, src1, dataSize=dataSize)
class WrRegOp(RegOp):
operand_types = (FoldedSrc1Op, Op2)
abstract = True
def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
super(WrRegOp, self).__init__(
src1, src2, flags=flags, dataSize=dataSize)
super().__init__(src1, src2, flags=flags, dataSize=dataSize)
class Add(FlagRegOp):
code = '''
@@ -597,7 +595,7 @@ let {{
dataSize="env.dataSize"):
if not src1:
src1 = dest
super(RdRegOp, self).__init__(dest, src1, dataSize=dataSize)
super().__init__(dest, src1, dataSize=dataSize)
code = 'DestReg = merge(SrcReg1, dest, ProdHi, dataSize);'
big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
@@ -1222,8 +1220,7 @@ let {{
operand_types = (FoldedDestOp, Imm8Op)
def __init__(self, dest, imm, flags=None, dataSize="env.dataSize"):
super(Ruflag, self).__init__(dest, imm, flags=flags,
dataSize=dataSize)
super().__init__(dest, imm, flags=flags, dataSize=dataSize)
class Rflag(RegOp):
code = '''
@@ -1248,8 +1245,7 @@ let {{
operand_types = (FoldedDestOp, Imm8Op)
def __init__(self, dest, imm, flags=None, dataSize="env.dataSize"):
super(Rflag, self).__init__(dest, imm, flags=flags,
dataSize=dataSize)
super().__init__(dest, imm, flags=flags, dataSize=dataSize)
class Sext(BasicRegOp):
code = '''
@@ -1295,8 +1291,7 @@ let {{
class Rddr(RegOp):
operand_types = (FoldedDestOp, DbgSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rddr, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
rdrCode = '''
CR4 cr4 = CR4Op;
DR7 dr7 = DR7Op;
@@ -1314,8 +1309,7 @@ let {{
class Wrdr(RegOp):
operand_types = (DbgDestOp, FoldedSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrdr, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
code = '''
CR4 cr4 = CR4Op;
DR7 dr7 = DR7Op;
@@ -1334,8 +1328,7 @@ let {{
class Rdcr(RegOp):
operand_types = (FoldedDestOp, CrSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rdcr, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
rdcrCode = '''
if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
fault = std::make_shared<InvalidOpcode>();
@@ -1350,8 +1343,7 @@ let {{
class Wrcr(RegOp):
operand_types = (CrDestOp, FoldedSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrcr, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
code = '''
if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
fault = std::make_shared<InvalidOpcode>();
@@ -1404,8 +1396,7 @@ let {{
abstract = True
operand_types = (SegDestOp, FoldedSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(SegOp, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
class WrSegOp(SegOp):
abstract = True
@@ -1454,8 +1445,7 @@ let {{
class Rdval(RegOp):
operand_types = (FoldedDestOp, MiscSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rdval, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
code = '''
DestReg = MiscRegSrc1;
'''
@@ -1463,8 +1453,7 @@ let {{
class Wrval(RegOp):
operand_types = (MiscDestOp, FoldedSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrval, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
super().__init__(dest, src1, flags=flags, dataSize=dataSize)
code = '''
MiscRegDest = SrcReg1;
'''
@@ -1473,8 +1462,7 @@ let {{
operand_types = (FoldedSrc1Op, FoldedSrc2Op, Imm8Op)
def __init__(self, src1, src2, imm=0, flags=None,
dataSize="env.dataSize"):
super(Chks, self).__init__(src1, src2, imm, flags=flags,
dataSize=dataSize)
super().__init__(src1, src2, imm, flags=flags, dataSize=dataSize)
code = '''
// The selector is in source 1 and can be at most 16 bits.
SegSelector selector = SrcReg1;
@@ -1691,7 +1679,7 @@ let {{
class Wrxftw(RegOp):
operand_types = (FoldedSrc1Op,)
def __init__(self, src1, flags=None, dataSize="env.dataSize"):
super(Wrxftw, self).__init__(src1, flags=None, dataSize=dataSize)
super().__init__(src1, flags=None, dataSize=dataSize)
code = '''
FTW = X86ISA::convX87XTagsToTags(SrcReg1);

2
src/arch/x86/isa/rom.isa
View File

@@ -42,7 +42,7 @@ let {{
class X86MicrocodeRom(Rom):
def __init__(self, name):
super(X86MicrocodeRom, self).__init__(name)
super().__init__(name)
self.directives = {}
def add_microop(self, mnemonic, microop):

2
src/cpu/BaseCPU.py
View File

@@ -302,5 +302,5 @@ class BaseCPU(ClockedObject):
yield child_node
def __init__(self, **kwargs):
super(BaseCPU, self).__init__(**kwargs)
super().__init__(**kwargs)
self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']

7
src/dev/IntPin.py
View File

@@ -33,18 +33,17 @@ Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE)
# multiple sinks.
class IntSourcePin(VectorPort):
def __init__(self, desc):
super(IntSourcePin, self).__init__(
INT_SOURCE_ROLE, desc, is_source=True)
super().__init__(INT_SOURCE_ROLE, desc, is_source=True)
# Each "physical" pin can be driven by a single source pin since there are no
# provisions for resolving competing signals running to the same pin.
class IntSinkPin(Port):
def __init__(self, desc):
super(IntSinkPin, self).__init__(INT_SINK_ROLE, desc)
super().__init__(INT_SINK_ROLE, desc)
# A vector of sink pins represents a bank of physical pins. For instance, an
# interrupt controller with many numbered input interrupts could represent them
# as a VectorIntSinkPin.
class VectorIntSinkPin(VectorPort):
def __init__(self, desc):
super(VectorIntSinkPin, self).__init__(INT_SINK_ROLE, desc)
super().__init__(INT_SINK_ROLE, desc)

46
src/dev/arm/RealView.py
View File

@@ -604,7 +604,7 @@ class ParentMem(SimpleMemory):
helper via the ParentMem interface.
"""
def __init__(self, *args, **kwargs):
super(ParentMem, self).__init__(*args, **kwargs)
super().__init__(*args, **kwargs)
self._generators = []
def addSubnodeGenerator(self, gen):
@@ -624,7 +624,7 @@ class ParentMem(SimpleMemory):
class MmioSRAM(ParentMem):
def __init__(self, *args, **kwargs):
super(MmioSRAM, self).__init__(**kwargs)
super().__init__(**kwargs)
def generateDeviceTree(self, state):
node = FdtNode("sram@%x" % int(self.range.start))
@@ -913,8 +913,7 @@ class VExpress_EMM(RealView):
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = loc('boot_emm.arm')
super(VExpress_EMM, self).setupBootLoader(
cur_sys, boot_loader, 0x8000000, 0x80000000)
super().setupBootLoader(cur_sys, boot_loader, 0x8000000, 0x80000000)
class VExpress_EMM64(VExpress_EMM):
# Three memory regions are specified totalling 512GiB
@@ -1230,7 +1229,7 @@ Interrupts:
]
def __init__(self, **kwargs):
super(VExpress_GEM5_Base, self).__init__(**kwargs)
super().__init__(**kwargs)
self.clock32KHz.voltage_domain = self.io_voltage
self.clock24MHz.voltage_domain = self.io_voltage
self.system_watchdog.clk_domain = self.dcc.osc_sys
@@ -1273,8 +1272,7 @@ Interrupts:
self.smmu.connect(dev)
def setupBootLoader(self, cur_sys, boot_loader):
super(VExpress_GEM5_Base, self).setupBootLoader(
cur_sys, boot_loader, 0x8000000, 0x80000000)
super().setupBootLoader(cur_sys, boot_loader, 0x8000000, 0x80000000)
# Setup m5ops. It's technically not a part of the boot
# loader, but this is the only place we can configure the
@@ -1302,7 +1300,7 @@ Interrupts:
def generateDeviceTree(self, state):
# Generate using standard RealView function
dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state))
dt = list(super().generateDeviceTree(state))
if len(dt) > 1:
raise Exception("System returned too many DT nodes")
node = dt[0]
@@ -1344,11 +1342,10 @@ class VExpress_GEM5_V1_Base(VExpress_GEM5_Base):
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot.arm64'), loc('boot.arm') ]
super(VExpress_GEM5_V1_Base, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)
def _on_chip_devices(self):
return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [
return super()._on_chip_devices() + [
self.gic, self.vgic, self.gicv2m,
]
@@ -1364,9 +1361,7 @@ class VExpress_GEM5_V1_HDLcd(VExpress_GEM5_V1_Base):
pio_addr=0x2b000000, interrupt=ArmSPI(num=95))
def _on_chip_devices(self):
return super(VExpress_GEM5_V1_HDLcd,self)._on_chip_devices() + [
self.hdlcd,
]
return super()._on_chip_devices() + [self.hdlcd,]
class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000,
@@ -1377,15 +1372,12 @@ class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
gic.cpu_max = 128
def _on_chip_devices(self):
return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
self.gic, self.gic.its
]
return super()._on_chip_devices() + [self.gic, self.gic.its]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
super(VExpress_GEM5_V2_Base, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)
class VExpress_GEM5_V2(VExpress_GEM5_V2_Base):
"""
@@ -1399,9 +1391,7 @@ class VExpress_GEM5_V2_HDLcd(VExpress_GEM5_V2_Base):
pio_addr=0x2b000000, interrupt=ArmSPI(num=95))
def _on_chip_devices(self):
return super(VExpress_GEM5_V2_HDLcd,self)._on_chip_devices() + [
self.hdlcd,
]
return super()._on_chip_devices() + [self.hdlcd,]
class VExpress_GEM5_Foundation(VExpress_GEM5_Base):
"""
@@ -1439,18 +1429,12 @@ class VExpress_GEM5_Foundation(VExpress_GEM5_Base):
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
def _on_chip_devices(self):
return super(VExpress_GEM5_Foundation, self)._on_chip_devices() + [
self.gic
]
return super()._on_chip_devices() + [self.gic]
def _off_chip_devices(self):
return super(VExpress_GEM5_Foundation, self)._off_chip_devices() + [
self.clcd,
self.sp810_fake,
]
return super()._off_chip_devices() + [self.clcd, self.sp810_fake,]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
super(VExpress_GEM5_Foundation, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)

3
src/dev/arm/VExpressFastmodel.py
View File

@@ -57,5 +57,4 @@ class VExpressFastmodel(VExpress_GEM5_Base):
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
super(VExpressFastmodel, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)

2
src/dev/arm/css/Scmi.py
View File

@@ -57,7 +57,7 @@ class ScmiChannel(SimObject):
"This is the doorbell used to notify the SCMI platform")
def __init__(self, shmem, *args, **kwargs):
super(ScmiChannel, self).__init__(**kwargs)
super().__init__(**kwargs)
def shmemGenerator(state):
shmem_node = FdtNode("scp-shmem@%x" % 0)

4
src/dev/net/Ethernet.py
View File

@@ -47,11 +47,11 @@ Port.compat(ETHERNET_ROLE, ETHERNET_ROLE)
class EtherInt(Port):
def __init__(self, desc):
super(EtherInt, self).__init__(ETHERNET_ROLE, desc)
super().__init__(ETHERNET_ROLE, desc)
class VectorEtherInt(VectorPort):
def __init__(self, desc):
super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc)
super().__init__(ETHERNET_ROLE, desc)
class EtherLink(SimObject):
type = 'EtherLink'

2
src/mem/cache/prefetch/Prefetcher.py vendored
View File

@@ -85,7 +85,7 @@ class BasePrefetcher(ClockedObject):
"Size of pages for virtual addresses")
def __init__(self, **kwargs):
super(BasePrefetcher, self).__init__(**kwargs)
super().__init__(**kwargs)
self._events = []
self._tlbs = []

2
src/mem/slicc/ast/ActionDeclAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Action, Type, Var
class ActionDeclAST(DeclAST):
def __init__(self, slicc, ident, pairs, statement_list):
super(ActionDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.ident = ident
self.statement_list = statement_list

2
src/mem/slicc/ast/AssignStatementAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.StatementAST import StatementAST
class AssignStatementAST(StatementAST):
def __init__(self, slicc, lvalue, rvalue):
super(AssignStatementAST, self).__init__(slicc)
super().__init__(slicc)
self.lvalue = lvalue
self.rvalue = rvalue

2
src/mem/slicc/ast/CheckAllocateStatementAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.StatementAST import StatementAST
class CheckAllocateStatementAST(StatementAST):
def __init__(self, slicc, variable):
super(StatementAST, self).__init__(slicc)
super().__init__(slicc)
self.variable = variable
def __repr__(self):

2
src/mem/slicc/ast/CheckNextCycleAST.py
View File

@@ -30,7 +30,7 @@ from slicc.ast.StatementAST import StatementAST
class CheckNextCycleAST(StatementAST):
def __init__(self, slicc):
super(CheckNextCycleAST, self).__init__(slicc)
super().__init__(slicc)
def __repr__(self):
return "[CheckNextCycleAST]"

2
src/mem/slicc/ast/CheckProbeStatementAST.py
View File

@@ -30,7 +30,7 @@ from slicc.ast.StatementAST import StatementAST
class CheckProbeStatementAST(StatementAST):
def __init__(self, slicc, in_port, address):
super(StatementAST, self).__init__(slicc)
super().__init__(slicc)
self.in_port = in_port
self.address = address

2
src/mem/slicc/ast/DeclAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.AST import AST
class DeclAST(AST):
def __init__(self, slicc, pairs = None):
super(DeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
def files(self, parent=None):
return set()

2
src/mem/slicc/ast/DeclListAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.AST import AST
class DeclListAST(AST):
def __init__(self, slicc, decls):
super(DeclListAST, self).__init__(slicc)
super().__init__(slicc)
if not isinstance(decls, (list, tuple)):
decls = [ decls ]

2
src/mem/slicc/ast/DeferEnqueueingStatementAST.py
View File

@@ -35,7 +35,7 @@ from slicc.symbols import Var
class DeferEnqueueingStatementAST(StatementAST):
def __init__(self, slicc, queue_name, type_ast, statements):
super(DeferEnqueueingStatementAST, self).__init__(slicc)
super().__init__(slicc)
self.queue_name = queue_name
self.type_ast = type_ast

2
src/mem/slicc/ast/EnqueueStatementAST.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols import Var
class EnqueueStatementAST(StatementAST):
def __init__(self, slicc, queue_name, type_ast, lexpr, statements):
super(EnqueueStatementAST, self).__init__(slicc)
super().__init__(slicc)
self.queue_name = queue_name
self.type_ast = type_ast

2
src/mem/slicc/ast/EnumDeclAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Func, Type
class EnumDeclAST(DeclAST):
def __init__(self, slicc, type_ast, pairs, fields):
super(EnumDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.type_ast = type_ast
self.fields = fields

2
src/mem/slicc/ast/EnumExprAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST
class EnumExprAST(ExprAST):
def __init__(self, slicc, type_ast, value):
super(EnumExprAST, self).__init__(slicc)
super().__init__(slicc)
assert type_ast
assert value

2
src/mem/slicc/ast/ExprAST.py
View File

@@ -28,7 +28,7 @@ from slicc.ast.AST import AST
class ExprAST(AST):
def __init__(self, slicc):
super(ExprAST, self).__init__(slicc)
super().__init__(slicc)
def findResources(self, resources):
# The default is no resources

2
src/mem/slicc/ast/ExprStatementAST.py
View File

@@ -32,7 +32,7 @@ from slicc.symbols import Type
class ExprStatementAST(StatementAST):
def __init__(self, slicc, expr):
super(ExprStatementAST, self).__init__(slicc)
super().__init__(slicc)
self.expr = expr
def __repr__(self):

2
src/mem/slicc/ast/FormalParamAST.py
View File

@@ -42,7 +42,7 @@ from slicc.symbols import Var
class FormalParamAST(AST):
def __init__(self, slicc, type_ast, ident, default = None, qualifier=""):
super(FormalParamAST, self).__init__(slicc)
super().__init__(slicc)
self.type_ast = type_ast
self.ident = ident
self.default = default

2
src/mem/slicc/ast/FuncCallExprAST.py
View File

@@ -43,7 +43,7 @@ from slicc.symbols import Func, Type
class FuncCallExprAST(ExprAST):
def __init__(self, slicc, proc_name, exprs):
super(FuncCallExprAST, self).__init__(slicc)
super().__init__(slicc)
self.proc_name = proc_name
self.exprs = exprs

2
src/mem/slicc/ast/FuncDeclAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Func, Type
class FuncDeclAST(DeclAST):
def __init__(self, slicc, return_type, ident, formals, pairs, statements):
super(FuncDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.return_type = return_type
self.ident = ident

2
src/mem/slicc/ast/IfStatementAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Type
class IfStatementAST(StatementAST):
def __init__(self, slicc, cond, then, else_):
super(IfStatementAST, self).__init__(slicc)
super().__init__(slicc)
assert cond is not None
assert then is not None

2
src/mem/slicc/ast/InPortDeclAST.py
View File

@@ -43,7 +43,7 @@ from slicc.symbols import Func, Type, Var
class InPortDeclAST(DeclAST):
def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements):
super(InPortDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.ident = ident
self.msg_type = msg_type

2
src/mem/slicc/ast/IsValidPtrExprAST.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols import Type
class IsValidPtrExprAST(ExprAST):
def __init__(self, slicc, variable, flag):
super(IsValidPtrExprAST, self).__init__(slicc)
super().__init__(slicc)
self.variable = variable
self.flag = flag

2
src/mem/slicc/ast/LiteralExprAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Type
class LiteralExprAST(ExprAST):
def __init__(self, slicc, literal, type):
super(LiteralExprAST, self).__init__(slicc)
super().__init__(slicc)
self.literal = literal
self.type = type

2
src/mem/slicc/ast/LocalVariableAST.py
View File

@@ -32,7 +32,7 @@ from slicc.symbols import Var
class LocalVariableAST(StatementAST):
def __init__(self, slicc, type_ast, ident, pointer = False):
super(LocalVariableAST, self).__init__(slicc)
super().__init__(slicc)
self.type_ast = type_ast
self.ident = ident
self.pointer = pointer

2
src/mem/slicc/ast/MachineAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import StateMachine, Type
class MachineAST(DeclAST):
def __init__(self, slicc, mtype, pairs_ast, config_parameters, decls):
super(MachineAST, self).__init__(slicc, pairs_ast)
super().__init__(slicc, pairs_ast)
self.ident = mtype.value
self.pairs_ast = pairs_ast

2
src/mem/slicc/ast/MemberExprAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST
class MemberExprAST(ExprAST):
def __init__(self, slicc, expr_ast, field):
super(MemberExprAST, self).__init__(slicc)
super().__init__(slicc)
self.expr_ast = expr_ast
self.field = field

6
src/mem/slicc/ast/MethodCallExprAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST
class MethodCallExprAST(ExprAST):
def __init__(self, slicc, proc_name, expr_ast_vec):
super(MethodCallExprAST, self).__init__(slicc)
super().__init__(slicc)
self.proc_name = proc_name
self.expr_ast_vec = expr_ast_vec
@@ -67,7 +67,7 @@ class MethodCallExprAST(ExprAST):
class MemberMethodCallExprAST(MethodCallExprAST):
def __init__(self, slicc, obj_expr_ast, func_call):
s = super(MemberMethodCallExprAST, self)
s = super()
s.__init__(slicc, func_call.proc_name, func_call.exprs)
self.obj_expr_ast = obj_expr_ast
@@ -157,7 +157,7 @@ class MemberMethodCallExprAST(MethodCallExprAST):
class ClassMethodCallExprAST(MethodCallExprAST):
def __init__(self, slicc, type_ast, proc_name, expr_ast_vec):
s = super(ClassMethodCallExprAST, self)
s = super()
s.__init__(slicc, proc_name, expr_ast_vec)
self.type_ast = type_ast

2
src/mem/slicc/ast/NewExprAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST
class NewExprAST(ExprAST):
def __init__(self, slicc, type_ast):
super(NewExprAST, self).__init__(slicc)
super().__init__(slicc)
self.type_ast = type_ast
def __repr__(self):

2
src/mem/slicc/ast/ObjDeclAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Var
class ObjDeclAST(DeclAST):
def __init__(self, slicc, type_ast, ident, pairs, rvalue, pointer):
super(ObjDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.type_ast = type_ast
self.ident = ident

2
src/mem/slicc/ast/OodAST.py
View File

@@ -30,7 +30,7 @@ from slicc.ast.ExprAST import ExprAST
class OodAST(ExprAST):
def __init__(self, slicc):
super(OodAST, self).__init__(slicc)
super().__init__(slicc)
def __repr__(self):
return "[Ood:]"

4
src/mem/slicc/ast/OperatorExprAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Type
class InfixOperatorExprAST(ExprAST):
def __init__(self, slicc, left, op, right):
super(InfixOperatorExprAST, self).__init__(slicc)
super().__init__(slicc)
self.left = left
self.op = op
@@ -96,7 +96,7 @@ class InfixOperatorExprAST(ExprAST):
class PrefixOperatorExprAST(ExprAST):
def __init__(self, slicc, op, operand):
super(PrefixOperatorExprAST, self).__init__(slicc)
super().__init__(slicc)
self.op = op
self.operand = operand

2
src/mem/slicc/ast/OutPortDeclAST.py
View File

@@ -32,7 +32,7 @@ from slicc.symbols import Type
class OutPortDeclAST(DeclAST):
def __init__(self, slicc, ident, msg_type, var_expr, pairs):
super(OutPortDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.ident = ident
self.msg_type = msg_type

2
src/mem/slicc/ast/PairAST.py
View File

@@ -28,7 +28,7 @@ from slicc.ast.AST import AST
class PairAST(AST):
def __init__(self, slicc, key, value):
super(PairAST, self).__init__(slicc)
super().__init__(slicc)
self.key = key
self.value = value

2
src/mem/slicc/ast/PairListAST.py
View File

@@ -28,7 +28,7 @@ from slicc.ast.AST import AST
class PairListAST(AST):
def __init__(self, slicc):
super(PairListAST, self).__init__(slicc)
super().__init__(slicc)
def __repr__(self):
return "[PairListAST] %r" % self.pairs

2
src/mem/slicc/ast/PeekStatementAST.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols import Var
class PeekStatementAST(StatementAST):
def __init__(self, slicc, queue_name, type_ast, pairs, statements, method):
super(PeekStatementAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.queue_name = queue_name
self.type_ast = type_ast

2
src/mem/slicc/ast/ReturnStatementAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.StatementAST import StatementAST
class ReturnStatementAST(StatementAST):
def __init__(self, slicc, expr_ast):
super(ReturnStatementAST, self).__init__(slicc)
super().__init__(slicc)
self.expr_ast = expr_ast

2
src/mem/slicc/ast/StallAndWaitStatementAST.py
View File

@@ -30,7 +30,7 @@ from slicc.ast.StatementAST import StatementAST
class StallAndWaitStatementAST(StatementAST):
def __init__(self, slicc, in_port, address):
super(StatementAST, self).__init__(slicc)
super().__init__(slicc)
self.in_port = in_port
self.address = address

2
src/mem/slicc/ast/StateDeclAST.py
View File

@@ -29,7 +29,7 @@ from slicc.symbols import Func, Type
class StateDeclAST(DeclAST):
def __init__(self, slicc, type_ast, pairs, states):
super(StateDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.type_ast = type_ast
self.states = states

2
src/mem/slicc/ast/StatementAST.py
View File

@@ -28,7 +28,7 @@ from slicc.ast.AST import AST
class StatementAST(AST):
def __init__(self, slicc, pairs=None):
super(StatementAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
def findResources(self, resources):
pass

2
src/mem/slicc/ast/StatementListAST.py
View File

@@ -29,7 +29,7 @@ from slicc.ast.AST import AST
class StatementListAST(AST):
def __init__(self, slicc, statements):
super(StatementListAST, self).__init__(slicc)
super().__init__(slicc)
if not isinstance(statements, (list, tuple)):
statements = [ statements ]
self.statements = statements

2
src/mem/slicc/ast/StaticCastAST.py
View File

@@ -28,7 +28,7 @@ from slicc.ast.ExprAST import ExprAST
class StaticCastAST(ExprAST):
def __init__(self, slicc, type_ast, type_modifier, expr_ast):
super(StaticCastAST, self).__init__(slicc)
super().__init__(slicc)
self.type_ast = type_ast
self.expr_ast = expr_ast

2
src/mem/slicc/ast/TransitionDeclAST.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols import Transition
class TransitionDeclAST(DeclAST):
def __init__(self, slicc, request_types, states, events, next_state,
actions):
super(TransitionDeclAST, self).__init__(slicc)
super().__init__(slicc)
self.request_types = request_types
self.states = states

2
src/mem/slicc/ast/TypeAST.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols import Type
class TypeAST(AST):
def __init__(self, slicc, ident):
super(TypeAST, self).__init__(slicc)
super().__init__(slicc)
self.ident = ident

2
src/mem/slicc/ast/TypeDeclAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols.Type import Type
class TypeDeclAST(DeclAST):
def __init__(self, slicc, type_ast, pairs, field_asts):
super(TypeDeclAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)
self.type_ast = type_ast
self.field_asts = field_asts

2
src/mem/slicc/ast/TypeFieldAST.py
View File

@@ -29,4 +29,4 @@ from slicc.ast.AST import AST
class TypeFieldAST(AST):
def __init__(self, slicc, pairs):
super(TypeFieldAST, self).__init__(slicc, pairs)
super().__init__(slicc, pairs)

2
src/mem/slicc/ast/TypeFieldEnumAST.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols import Event, State, RequestType
class TypeFieldEnumAST(TypeFieldAST):
def __init__(self, slicc, field_id, pairs_ast):
super(TypeFieldEnumAST, self).__init__(slicc, pairs_ast)
super().__init__(slicc, pairs_ast)
self.field_id = field_id
self.pairs_ast = pairs_ast

2
src/mem/slicc/ast/TypeFieldStateAST.py
View File

@@ -29,7 +29,7 @@ from slicc.symbols import Event, State
class TypeFieldStateAST(TypeFieldAST):
def __init__(self, slicc, field_id, perm_ast, pairs_ast):
super(TypeFieldStateAST, self).__init__(slicc, pairs_ast)
super().__init__(slicc, pairs_ast)
self.field_id = field_id
self.perm_ast = perm_ast

2
src/mem/slicc/ast/VarExprAST.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols import Type, Var
class VarExprAST(ExprAST):
def __init__(self, slicc, var):
super(VarExprAST, self).__init__(slicc)
super().__init__(slicc)
self._var = var
def __repr__(self):

2
src/mem/slicc/ast/WakeupPortStatementAST.py
View File

@@ -37,7 +37,7 @@ from slicc.ast.StatementAST import StatementAST
class WakeupPortStatementAST(StatementAST):
def __init__(self, slicc, in_port, address):
super(StatementAST, self).__init__(slicc)
super().__init__(slicc)
self.in_port = in_port
self.address = address

2
src/mem/slicc/symbols/Action.py
View File

@@ -29,7 +29,7 @@ from slicc.symbols.Symbol import Symbol
class Action(Symbol):
def __init__(self, table, ident, resources, location, pairs):
super(Action, self).__init__(table, ident, location, pairs)
super().__init__(table, ident, location, pairs)
self.resources = resources
def __repr__(self):

2
src/mem/slicc/symbols/Func.py
View File

@@ -31,7 +31,7 @@ from slicc.symbols.Type import Type
class Func(Symbol):
def __init__(self, table, ident, name, location, return_type, param_types,
param_strings, body, pairs):
super(Func, self).__init__(table, ident, location, pairs)
super().__init__(table, ident, location, pairs)
self.return_type = return_type
self.param_types = param_types
self.param_strings = param_strings

2
src/mem/slicc/symbols/StateMachine.py
View File

@@ -68,7 +68,7 @@ python_class_map = {
class StateMachine(Symbol):
def __init__(self, symtab, ident, location, pairs, config_parameters):
super(StateMachine, self).__init__(symtab, ident, location, pairs)
super().__init__(symtab, ident, location, pairs)
self.table = None
# Data members in the State Machine that have been declared before

4
src/mem/slicc/symbols/Symbol.py
View File

@@ -29,7 +29,7 @@ from slicc.util import PairContainer
class Symbol(PairContainer):
def __init__(self, symtab, ident, location, pairs=None):
super(Symbol, self).__init__()
super().__init__()
from slicc.util import Location
from slicc.symbols import SymbolTable
@@ -56,7 +56,7 @@ class Symbol(PairContainer):
if key in self.pairs:
self.warning("Pair key '%s' re-defined. new: '%s' old: '%s'",
key, value, self.pairs[key])
super(Symbol, self).__setitem__(key, value)
super().__setitem__(key, value)
@property
def short(self):

2
src/mem/slicc/symbols/Transition.py
View File

@@ -32,7 +32,7 @@ class Transition(Symbol):
def __init__(self, table, machine, state, event, nextState, actions,
request_types, location):
ident = "%s|%s" % (state, event)
super(Transition, self).__init__(table, ident, location)
super().__init__(table, ident, location)
self.state = machine.states[state]
self.event = machine.events[event]

7
src/mem/slicc/symbols/Type.py
View File

@@ -46,8 +46,7 @@ from slicc.symbols.Var import Var
class DataMember(Var):
def __init__(self, symtab, ident, location, type, code, pairs,
machine, init_code):
super(DataMember, self).__init__(symtab, ident, location, type,
code, pairs, machine)
super().__init__(symtab, ident, location, type, code, pairs, machine)
self.init_code = init_code
self.real_c_type = self.type.c_ident
if "template" in pairs:
@@ -55,13 +54,13 @@ class DataMember(Var):
class Enumeration(PairContainer):
def __init__(self, ident, pairs):
super(Enumeration, self).__init__(pairs)
super().__init__(pairs)
self.ident = ident
self.primary = False
class Type(Symbol):
def __init__(self, table, ident, location, pairs, machine=None):
super(Type, self).__init__(table, ident, location, pairs)
super().__init__(table, ident, location, pairs)
self.c_ident = ident
self.abstract_ident = ""
if machine:

2
src/mem/slicc/symbols/Var.py
View File

@@ -30,7 +30,7 @@ from slicc.symbols.Symbol import Symbol
class Var(Symbol):
def __init__(self, symtab, ident, location, type, code, pairs,
machine=None):
super(Var, self).__init__(symtab, ident, location, pairs)
super().__init__(symtab, ident, location, pairs)
self.machine = machine
self.type = type

2
src/python/gem5/components/boards/abstract_board.py
View File

@@ -68,7 +68,7 @@ class AbstractBoard(System):
memory: "AbstractMemory",
cache_hierarchy: "AbstractCacheHierarchy",
) -> None:
super(AbstractBoard, self).__init__()
super().__init__()
"""
:param clk_freq: The clock frequency for this board.
:param processor: The processor for this board.

4
src/python/gem5/components/boards/simple_board.py
View File

@@ -58,7 +58,7 @@ class SimpleBoard(AbstractBoard, SEBinaryWorkload):
memory: AbstractMemorySystem,
cache_hierarchy: AbstractCacheHierarchy,
) -> None:
super(SimpleBoard, self).__init__(
super().__init__(
clk_freq=clk_freq,
processor=processor,
memory=memory,
@@ -110,4 +110,4 @@ class SimpleBoard(AbstractBoard, SEBinaryWorkload):
# The simple board just has one memory range that is the size of the
# memory.
self.mem_ranges = [AddrRange(memory.get_size())]
memory.set_memory_range(self.mem_ranges)
memory.set_memory_range(self.mem_ranges)

2
src/python/gem5/components/boards/test_board.py
View File

@@ -56,7 +56,7 @@ class TestBoard(AbstractBoard):
memory: AbstractMemorySystem,
cache_hierarchy: AbstractCacheHierarchy,
):
super(TestBoard, self).__init__(
super().__init__(
clk_freq=clk_freq,
processor=processor,
memory=memory,

2
src/python/gem5/components/boards/x86_board.py
View File

@@ -78,7 +78,7 @@ class X86Board(AbstractBoard, KernelDiskWorkload):
memory: AbstractMemorySystem,
cache_hierarchy: AbstractCacheHierarchy,
) -> None:
super(X86Board, self).__init__(
super().__init__(
clk_freq=clk_freq,
processor=processor,
memory=memory,

2
src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py
View File

@@ -35,7 +35,7 @@ class AbstractCacheHierarchy(SubSystem):
__metaclass__ = ABCMeta
def __init__(self):
super(AbstractCacheHierarchy, self).__init__()
super().__init__()
"""
A Cache Hierarchy incorporates any system components which manages

2
src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py
View File

@@ -39,7 +39,7 @@ class AbstractClassicCacheHierarchy(AbstractCacheHierarchy):
"""
def __init__(self):
super(AbstractClassicCacheHierarchy, self).__init__()
super().__init__()
@overrides(AbstractCacheHierarchy)
def is_ruby(self) -> bool:

2
src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py
View File

@@ -48,7 +48,7 @@ class L1DCache(Cache):
writeback_clean: bool = True,
PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
):
super(L1DCache, self).__init__()
super().__init__()
self.size = size
self.assoc = assoc
self.tag_latency = tag_latency

2
src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py
View File

@@ -48,7 +48,7 @@ class L1ICache(Cache):
writeback_clean: bool = True,
PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
):
super(L1ICache, self).__init__()
super().__init__()
self.size = size
self.assoc = assoc
self.tag_latency = tag_latency

2
src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
View File

@@ -48,7 +48,7 @@ class L2Cache(Cache):
writeback_clean: bool = True,
PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
):
super(L2Cache, self).__init__()
super().__init__()
self.size = size
self.assoc = assoc
self.tag_latency = tag_latency

2
src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py
View File

@@ -44,7 +44,7 @@ class MMUCache(Cache):
tgts_per_mshr: int = 12,
writeback_clean: bool = True,
):
super(MMUCache, self).__init__()
super().__init__()
self.size = size
self.assoc = assoc
self.tag_latency = tag_latency

2
src/python/gem5/components/cachehierarchies/classic/no_cache.py
View File

@@ -82,7 +82,7 @@ class NoCache(AbstractClassicCacheHierarchy):
:type membus: BaseXBar
"""
super(NoCache, self).__init__()
super().__init__()
self.membus = membus
@overrides(AbstractClassicCacheHierarchy)

2
src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py
View File

@@ -35,7 +35,7 @@ class AbstractRubyCacheHierarchy(AbstractCacheHierarchy):
"""
def __init__(self):
super(AbstractRubyCacheHierarchy, self).__init__()
super().__init__()
@overrides(AbstractCacheHierarchy)
def is_ruby(self) -> bool:

2
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
View File

@@ -40,7 +40,7 @@ class AbstractDirectory(Directory_Controller):
def __init__(self, network, cache_line_size):
""" """
super(AbstractDirectory, self).__init__()
super().__init__()
self.version = self.versionCount()
self._cache_line_size = cache_line_size
self.connectQueues(network)

2
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
View File

@@ -39,7 +39,7 @@ class AbstractDMAController(DMA_Controller):
return cls._version - 1
def __init__(self, network, cache_line_size):
super(AbstractDMAController, self).__init__()
super().__init__()
self.version = self.versionCount()
self._cache_line_size = cache_line_size
self.connectQueues(network)

2
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
View File

@@ -47,7 +47,7 @@ class AbstractL1Cache(L1Cache_Controller):
# However, we need some way to set the index bits
def __init__(self, network, cache_line_size):
""" """
super(AbstractL1Cache, self).__init__()
super().__init__()
self.version = self.versionCount()
self._cache_line_size = cache_line_size

2
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
View File

@@ -39,7 +39,7 @@ class AbstractL2Cache(L2Cache_Controller):
return cls._version - 1
def __init__(self, network, cache_line_size):
super(AbstractL2Cache, self).__init__()
super().__init__()
self.version = self.versionCount()
self._cache_line_size = cache_line_size

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
View File

@@ -36,7 +36,7 @@ from m5.objects import (
class Directory(AbstractDirectory):
def __init__(self, network, cache_line_size, mem_range, port):
super(Directory, self).__init__(network, cache_line_size)
super().__init__(network, cache_line_size)
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory()
# Connect this directory to the memory side.

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
View File

@@ -32,7 +32,7 @@ from m5.objects import MessageBuffer
class DMAController(AbstractDMAController):
def __init__(self, network, cache_line_size):
super(DMAController, self).__init__(network, cache_line_size)
super().__init__(network, cache_line_size)
@overrides(AbstractDMAController)
def connectQueues(self, network):

Some files were not shown because too many files have changed in this diff Show More