From ba5f68db3df88823338abb388a4c4b0229239d1d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 28 Oct 2021 16:16:07 -0700 Subject: [PATCH] misc: Use python 3's argumentless super(). When calling a method in a superclass, you can/should use the super() method to get a reference to that class. The python 2 version of that method takes two parameters, the current class name, and the "self" instance. The python 3 version takes no arguments. This is better for a at least three reasons. First, this version is less verbose because you don't have to specify any arguments. Second, you don't have to remember which argument goes where (I always have to look it up), and you can't accidentally use the wrong class name, or forget to update it if you copy code from a different class. Third, this version will work correctly if you use a class decorator. I don't know exactly how the mechanics of this work, but it is referred to in a comment on this stackoverflow question: https://stackoverflow.com/questions/681953/how-to-decorate-a-class Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/SConscript | 20 ++++---- src/arch/arm/fastmodel/FastModel.py | 14 +++--- src/arch/arm/fastmodel/GIC/FastModelGIC.py | 9 ++-- src/arch/arm/fastmodel/SConscript | 12 ++--- src/arch/arm/isa/arminstobjparams.isa | 2 +- src/arch/arm/isa/insts/amo64.isa | 8 ++-- src/arch/arm/isa/insts/ldr.isa | 12 ++--- src/arch/arm/isa/insts/ldr64.isa | 8 ++-- src/arch/arm/isa/insts/str.isa | 16 +++---- src/arch/arm/isa/insts/str64.isa | 12 ++--- src/arch/isa_parser/isa_parser.py | 5 +- src/arch/isa_parser/operand_types.py | 6 +-- src/arch/micro_asm.py | 6 +-- src/arch/micro_asm_test.py | 2 +- src/arch/x86/isa/macroop.isa | 2 +- src/arch/x86/isa/microops/base.isa | 4 +- src/arch/x86/isa/microops/debug.isa | 5 +- src/arch/x86/isa/microops/fpop.isa | 10 ++-- src/arch/x86/isa/microops/ldstop.isa | 14 +++--- src/arch/x86/isa/microops/mediaop.isa | 22 ++++----- src/arch/x86/isa/microops/regop.isa | 44 +++++++----------- src/arch/x86/isa/rom.isa | 2 +- src/cpu/BaseCPU.py | 2 +- src/dev/IntPin.py | 7 ++- src/dev/arm/RealView.py | 46 ++++++------------- src/dev/arm/VExpressFastmodel.py | 3 +- src/dev/arm/css/Scmi.py | 2 +- src/dev/net/Ethernet.py | 4 +- src/mem/cache/prefetch/Prefetcher.py | 2 +- src/mem/slicc/ast/ActionDeclAST.py | 2 +- src/mem/slicc/ast/AssignStatementAST.py | 2 +- .../slicc/ast/CheckAllocateStatementAST.py | 2 +- src/mem/slicc/ast/CheckNextCycleAST.py | 2 +- src/mem/slicc/ast/CheckProbeStatementAST.py | 2 +- src/mem/slicc/ast/DeclAST.py | 2 +- src/mem/slicc/ast/DeclListAST.py | 2 +- .../slicc/ast/DeferEnqueueingStatementAST.py | 2 +- src/mem/slicc/ast/EnqueueStatementAST.py | 2 +- src/mem/slicc/ast/EnumDeclAST.py | 2 +- src/mem/slicc/ast/EnumExprAST.py | 2 +- src/mem/slicc/ast/ExprAST.py | 2 +- src/mem/slicc/ast/ExprStatementAST.py | 2 +- src/mem/slicc/ast/FormalParamAST.py | 2 +- src/mem/slicc/ast/FuncCallExprAST.py | 2 +- src/mem/slicc/ast/FuncDeclAST.py | 2 +- src/mem/slicc/ast/IfStatementAST.py | 2 +- src/mem/slicc/ast/InPortDeclAST.py | 2 +- src/mem/slicc/ast/IsValidPtrExprAST.py | 2 +- src/mem/slicc/ast/LiteralExprAST.py | 2 +- src/mem/slicc/ast/LocalVariableAST.py | 2 +- src/mem/slicc/ast/MachineAST.py | 2 +- src/mem/slicc/ast/MemberExprAST.py | 2 +- src/mem/slicc/ast/MethodCallExprAST.py | 6 +-- src/mem/slicc/ast/NewExprAST.py | 2 +- src/mem/slicc/ast/ObjDeclAST.py | 2 +- src/mem/slicc/ast/OodAST.py | 2 +- src/mem/slicc/ast/OperatorExprAST.py | 4 +- src/mem/slicc/ast/OutPortDeclAST.py | 2 +- src/mem/slicc/ast/PairAST.py | 2 +- src/mem/slicc/ast/PairListAST.py | 2 +- src/mem/slicc/ast/PeekStatementAST.py | 2 +- src/mem/slicc/ast/ReturnStatementAST.py | 2 +- src/mem/slicc/ast/StallAndWaitStatementAST.py | 2 +- src/mem/slicc/ast/StateDeclAST.py | 2 +- src/mem/slicc/ast/StatementAST.py | 2 +- src/mem/slicc/ast/StatementListAST.py | 2 +- src/mem/slicc/ast/StaticCastAST.py | 2 +- src/mem/slicc/ast/TransitionDeclAST.py | 2 +- src/mem/slicc/ast/TypeAST.py | 2 +- src/mem/slicc/ast/TypeDeclAST.py | 2 +- src/mem/slicc/ast/TypeFieldAST.py | 2 +- src/mem/slicc/ast/TypeFieldEnumAST.py | 2 +- src/mem/slicc/ast/TypeFieldStateAST.py | 2 +- src/mem/slicc/ast/VarExprAST.py | 2 +- src/mem/slicc/ast/WakeupPortStatementAST.py | 2 +- src/mem/slicc/symbols/Action.py | 2 +- src/mem/slicc/symbols/Func.py | 2 +- src/mem/slicc/symbols/StateMachine.py | 2 +- src/mem/slicc/symbols/Symbol.py | 4 +- src/mem/slicc/symbols/Transition.py | 2 +- src/mem/slicc/symbols/Type.py | 7 ++- src/mem/slicc/symbols/Var.py | 2 +- .../gem5/components/boards/abstract_board.py | 2 +- .../gem5/components/boards/simple_board.py | 4 +- .../gem5/components/boards/test_board.py | 2 +- .../gem5/components/boards/x86_board.py | 2 +- .../abstract_cache_hierarchy.py | 2 +- .../abstract_classic_cache_hierarchy.py | 2 +- .../classic/caches/l1dcache.py | 2 +- .../classic/caches/l1icache.py | 2 +- .../classic/caches/l2cache.py | 2 +- .../classic/caches/mmu_cache.py | 2 +- .../cachehierarchies/classic/no_cache.py | 2 +- .../ruby/abstract_ruby_cache_hierarchy.py | 2 +- .../ruby/caches/abstract_directory.py | 2 +- .../ruby/caches/abstract_dma_controller.py | 2 +- .../ruby/caches/abstract_l1_cache.py | 2 +- .../ruby/caches/abstract_l2_cache.py | 2 +- .../ruby/caches/mesi_two_level/directory.py | 2 +- .../caches/mesi_two_level/dma_controller.py | 2 +- .../ruby/caches/mesi_two_level/l1_cache.py | 2 +- .../ruby/caches/mesi_two_level/l2_cache.py | 2 +- .../ruby/caches/mi_example/directory.py | 2 +- .../ruby/caches/mi_example/dma_controller.py | 2 +- .../ruby/caches/mi_example/l1_cache.py | 2 +- .../ruby/topologies/simple_pt2pt.py | 2 +- .../memory/abstract_memory_system.py | 2 +- .../gem5/components/memory/dramsim_3.py | 4 +- .../components/processors/abstract_core.py | 2 +- .../processors/abstract_generator_core.py | 2 +- .../processors/abstract_processor.py | 2 +- .../processors/complex_generator.py | 2 +- .../processors/complex_generator_core.py | 2 +- .../components/processors/gups_generator.py | 2 +- .../processors/gups_generator_core.py | 2 +- .../processors/gups_generator_ep.py | 2 +- .../processors/gups_generator_par.py | 2 +- .../components/processors/linear_generator.py | 2 +- .../processors/linear_generator_core.py | 2 +- .../components/processors/random_generator.py | 2 +- .../processors/random_generator_core.py | 2 +- .../gem5/components/processors/simple_core.py | 2 +- .../components/processors/simple_processor.py | 2 +- .../processors/simple_switchable_processor.py | 2 +- .../processors/switchable_processor.py | 2 +- src/python/gem5/resources/resource.py | 2 +- src/python/importer.py | 2 +- src/python/m5/SimObject.py | 6 +-- src/python/m5/event.py | 4 +- src/python/m5/ext/pystats/group.py | 6 +-- src/python/m5/ext/pystats/jsonloader.py | 4 +- src/python/m5/ext/pystats/statistic.py | 36 ++++----------- src/python/m5/options.py | 8 ++-- src/python/m5/params.py | 42 ++++++++--------- src/python/m5/proxy.py | 6 +-- src/python/m5/util/__init__.py | 2 +- src/python/m5/util/attrdict.py | 10 ++-- src/python/m5/util/fdthelper.py | 12 ++--- src/sim/Workload.py | 2 +- src/systemc/Tlm.py | 9 ++-- src/systemc/tests/SConscript | 6 +-- src/systemc/tests/verify.py | 4 +- 142 files changed, 301 insertions(+), 370 deletions(-) diff --git a/src/SConscript b/src/SConscript index 25ac888cf1..03f339ff03 100644 --- a/src/SConscript +++ b/src/SConscript @@ -94,7 +94,7 @@ class PySource(SourceFile): def __init__(self, package, source, tags=None, add_tags=None): '''specify the python package, the source file, and any tags''' - super(PySource, self).__init__(source, tags, add_tags) + super().__init__(source, tags, add_tags) basename = os.path.basename(self.filename) modname, ext = os.path.splitext(basename) @@ -145,7 +145,7 @@ class SimObject(PySource): def __init__(self, source, tags=None, add_tags=None): '''Specify the source file and any tags (automatically in the m5.objects package)''' - super(SimObject, self).__init__('m5.objects', source, tags, add_tags) + super().__init__('m5.objects', source, tags, add_tags) if self.fixed: raise AttributeError("Too late to call SimObject now.") @@ -226,7 +226,7 @@ class TopLevelMeta(type): def __init__(cls, name, bases, d): TopLevelMeta.all.append(cls) - super(TopLevelMeta, cls).__init__(name, bases, d) + super().__init__(name, bases, d) cls.all = [] class TopLevelBase(object, metaclass=TopLevelMeta): @@ -235,7 +235,7 @@ class TopLevelBase(object, metaclass=TopLevelMeta): def __init__(self, target, *srcs_and_filts): '''Specify the target name and any sources. Sources that are not SourceFiles are evalued with Source().''' - super(TopLevelBase, self).__init__() + super().__init__() self.all.append(self) self.target = target @@ -325,7 +325,7 @@ class Gem5(Executable): env.Depends(date_obj, objs) objs.append(date_obj) - return super(Gem5, self).declare(env, objs) + return super().declare(env, objs) class GTest(Executable): @@ -334,7 +334,7 @@ class GTest(Executable): def __init__(self, *srcs_and_filts, **kwargs): if not kwargs.pop('skip_lib', False): srcs_and_filts = srcs_and_filts + (with_tag('gtest lib'),) - super(GTest, self).__init__(*srcs_and_filts) + super().__init__(*srcs_and_filts) @classmethod def declare_all(cls, env): @@ -345,10 +345,10 @@ class GTest(Executable): env.Append(CPPFLAGS=env['GTEST_CPPFLAGS']) env['GTEST_OUT_DIR'] = \ Dir(env['BUILDDIR']).Dir('unittests.${ENV_LABEL}') - return super(GTest, cls).declare_all(env) + return super().declare_all(env) def declare(self, env): - binary, stripped = super(GTest, self).declare(env) + binary, stripped = super().declare(env) out_dir = env['GTEST_OUT_DIR'] xml_file = out_dir.Dir(str(self.dir)).File(self.target + '.xml') @@ -520,7 +520,7 @@ SimObject.fixed = True class SimpleModuleLoader(importlib.abc.Loader): '''A simple wrapper which delegates setting up a module to a function.''' def __init__(self, executor): - super(SimpleModuleLoader, self).__init__() + super().__init__() self.executor = executor def create_module(self, spec): return None @@ -530,7 +530,7 @@ class SimpleModuleLoader(importlib.abc.Loader): class M5MetaPathFinder(importlib.abc.MetaPathFinder): def __init__(self, modules): - super(M5MetaPathFinder, self).__init__() + super().__init__() self.modules = modules self.installed = set() diff --git a/src/arch/arm/fastmodel/FastModel.py b/src/arch/arm/fastmodel/FastModel.py index 66785f8c38..f3e93a0439 100644 --- a/src/arch/arm/fastmodel/FastModel.py +++ b/src/arch/arm/fastmodel/FastModel.py @@ -47,7 +47,7 @@ class AmbaTargetSocket(Port): peer_role = AMBA_TARGET_ROLE(width) Port.compat(my_role, peer_role) - super(AmbaTargetSocket, self).__init__(my_role, desc) + super().__init__(my_role, desc) class VectorAmbaTargetSocket(VectorPort): def __init__(self, width, desc): @@ -55,7 +55,7 @@ class VectorAmbaTargetSocket(VectorPort): peer_role = AMBA_TARGET_ROLE(width) Port.compat(my_role, peer_role) - super(VectorAmbaTargetSocket, self).__init__(my_role, desc) + super().__init__(my_role, desc) class AmbaInitiatorSocket(Port): def __init__(self, width, desc): @@ -63,8 +63,7 @@ class AmbaInitiatorSocket(Port): peer_role = AMBA_INITIATOR_ROLE(width) Port.compat(my_role, peer_role) - super(AmbaInitiatorSocket, self).__init__( - my_role, desc, is_source=True) + super().__init__(my_role, desc, is_source=True) class VectorAmbaInitiatorSocket(VectorPort): def __init__(self, width, desc): @@ -72,8 +71,7 @@ class VectorAmbaInitiatorSocket(VectorPort): peer_role = AMBA_INITIATOR_ROLE(width) Port.compat(my_role, peer_role) - super(VectorAmbaInitiatorSocket, self).__init__( - my_role, desc, is_source=True) + super().__init__(my_role, desc, is_source=True) class ScRequestPort(Port): def __init__(self, desc, port_type): @@ -81,7 +79,7 @@ class ScRequestPort(Port): peer_role = SC_RESPONSE_PORT_ROLE(port_type) Port.compat(my_role, peer_role) - super(ScRequestPort, self).__init__(my_role, desc) + super().__init__(my_role, desc) class ScResponsePort(Port): def __init__(self, desc, port_type): @@ -89,7 +87,7 @@ class ScResponsePort(Port): peer_role = SC_REQUEST_PORT_ROLE(port_type) Port.compat(my_role, peer_role) - super(ScResponsePort, self).__init__(my_role, desc) + super().__init__(my_role, desc) class AmbaToTlmBridge64(SystemC_ScModule): type = 'AmbaToTlmBridge64' diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py b/src/arch/arm/fastmodel/GIC/FastModelGIC.py index 2386b2f8c6..5a551dfb97 100644 --- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py +++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py @@ -50,18 +50,15 @@ Port.compat(GICV3_COMMS_TARGET_ROLE, GICV3_COMMS_INITIATOR_ROLE) class Gicv3CommsTargetSocket(Port): def __init__(self, desc): - super(Gicv3CommsTargetSocket, self).__init__( - GICV3_COMMS_INITIATOR_ROLE, desc) + super().__init__(GICV3_COMMS_INITIATOR_ROLE, desc) class Gicv3CommsInitiatorSocket(Port): def __init__(self, desc): - super(Gicv3CommsInitiatorSocket, self).__init__( - GICV3_COMMS_TARGET_ROLE, desc, is_source=True) + super().__init__(GICV3_COMMS_TARGET_ROLE, desc, is_source=True) class VectorGicv3CommsInitiatorSocket(VectorPort): def __init__(self, desc): - super(VectorGicv3CommsInitiatorSocket, self).__init__( - GICV3_COMMS_TARGET_ROLE, desc, is_source=True) + super().__init__(GICV3_COMMS_TARGET_ROLE, desc, is_source=True) class SCFastModelGIC(SystemC_ScModule): diff --git a/src/arch/arm/fastmodel/SConscript b/src/arch/arm/fastmodel/SConscript index 80717fe691..214580e47b 100644 --- a/src/arch/arm/fastmodel/SConscript +++ b/src/arch/arm/fastmodel/SConscript @@ -149,8 +149,7 @@ class ProjectFileParser(Grammar): class StringParam(Param): def __init__(self, name, value): - super(ProjectFileParser.StringParam, self).__init__( - is_object=False) + super().__init__(is_object=False) self.name = name self.value = value @@ -160,8 +159,7 @@ class ProjectFileParser(Grammar): class ObjectParam(Param): def __init__(self, type_name, name, params): - super(ProjectFileParser.ObjectParam, self).__init__( - is_object=True) + super().__init__(is_object=True) self.type_name = type_name self.name = name self.params = params @@ -362,13 +360,13 @@ class ArmFastModelBin(Executable): sources = list(filter(not_component, components_and_sources)) self.components = components - super(ArmFastModelBin, self).__init__(target, *sources) + super().__init__(target, *sources) @classmethod def declare_all(cls, env): env = env.Clone() env.Prepend(LIBS=env['STATIC_LIB'][0]) - super(ArmFastModelBin, cls).declare_all(env) + super().declare_all(env) def declare(self, env): env = env.Clone() @@ -383,7 +381,7 @@ class ArmFastModelBin(Executable): for component in self.components: component.prepare_env(env) - binary = super(ArmFastModelBin, self).declare(env, objs)[0] + binary = super().declare(env, objs)[0] # We need a copy of the simulation engine lib alongside the executable # so that the license check works properly. diff --git a/src/arch/arm/isa/arminstobjparams.isa b/src/arch/arm/isa/arminstobjparams.isa index f8fab23328..f47221af14 100644 --- a/src/arch/arm/isa/arminstobjparams.isa +++ b/src/arch/arm/isa/arminstobjparams.isa @@ -29,7 +29,7 @@ let {{ class ArmInstObjParams(InstObjParams): def __init__(self, *args, **kwargs): - super(ArmInstObjParams, self).__init__(*args, **kwargs) + super().__init__(*args, **kwargs) self.padSrcRegIdx(self.operands.numDestRegs) }}; diff --git a/src/arch/arm/isa/insts/amo64.isa b/src/arch/arm/isa/insts/amo64.isa index a6386af117..72eea89518 100644 --- a/src/arch/arm/isa/insts/amo64.isa +++ b/src/arch/arm/isa/insts/amo64.isa @@ -65,7 +65,7 @@ let {{ def __init__(self, mnem, Name, size=4, user=False, flavor="normal", unsign=True, top = False, paired=False, ret_op=True): - super(AtomicInst64, self).__init__() + super().__init__() self.name= mnem self.Name = Name @@ -166,7 +166,7 @@ let {{ execBase = 'AmoOp' def __init__(self, *args, **kargs): - super(AtomicSingleOp, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.suffix = buildMemSuffix(not self.unsign, self.size) if self.size == 8: self.res = 'XResult_ud' #if self.unsign else 'XResult_sd' @@ -267,7 +267,7 @@ let {{ execBase = 'AmoOp' def __init__(self, *args, **kargs): - super(CasPair64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.paired = True self.offset = "" if self.size == 8: @@ -386,7 +386,7 @@ let {{ execBase = 'AmoOp' def __init__(self, *args, **kargs): - super(AtomicArithmeticSingleOp, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) store_res = "%(utype)s unsMem = Mem%(suffix)s" if self.size != 8: diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 7a6b5cd41c..1f011bc58c 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -47,7 +47,7 @@ let {{ def __init__(self, mnem, post, add, writeback, size=4, sign=False, user=False, flavor="normal"): - super(LoadInst, self).__init__() + super().__init__() self.name = mnem self.post = post @@ -89,7 +89,7 @@ let {{ decConstBase = 'Rfe' def __init__(self, mnem, post, add, writeback): - super(RfeInst, self).__init__(mnem, post, add, writeback) + super().__init__(mnem, post, add, writeback) self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8) self.memFlags.append("ArmISA::MMU::AlignWord") @@ -126,7 +126,7 @@ let {{ class LoadImmInst(LoadInst): def __init__(self, *args, **kargs): - super(LoadImmInst, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = self.op + " imm" if self.add: @@ -140,7 +140,7 @@ let {{ class LoadRegInst(LoadInst): def __init__(self, *args, **kargs): - super(LoadRegInst, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ " shiftType, OptShiftRmCondCodesC)" if self.add: @@ -154,7 +154,7 @@ let {{ class LoadSingle(LoadInst): def __init__(self, *args, **kargs): - super(LoadSingle, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) # Build the default class name self.Name = self.nameFunc(self.post, self.add, self.writeback, @@ -240,7 +240,7 @@ let {{ class LoadDouble(LoadInst): def __init__(self, *args, **kargs): - super(LoadDouble, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) # Build the default class name self.Name = self.nameFunc(self.post, self.add, self.writeback) diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa index b3111a86b0..72bbd5a764 100644 --- a/src/arch/arm/isa/insts/ldr64.isa +++ b/src/arch/arm/isa/insts/ldr64.isa @@ -47,7 +47,7 @@ let {{ def __init__(self, mnem, Name, size=4, sign=False, user=False, literal=False, flavor="normal", top=False): - super(LoadInst64, self).__init__() + super().__init__() self.name = mnem self.Name = Name @@ -175,14 +175,14 @@ let {{ class LoadImmInst64(LoadInst64): def __init__(self, *args, **kargs): - super(LoadImmInst64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = " + imm" self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);" class LoadRegInst64(LoadInst64): def __init__(self, *args, **kargs): - super(LoadRegInst64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = " + extendReg64(XOffset, type, shiftAmt, 64)" self.wbDecl = \ @@ -191,7 +191,7 @@ let {{ class LoadRawRegInst64(LoadInst64): def __init__(self, *args, **kargs): - super(LoadRawRegInst64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = "" class LoadSingle64(LoadInst64): diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index 49463b7b43..8700293f62 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -47,7 +47,7 @@ let {{ def __init__(self, mnem, post, add, writeback, size=4, sign=False, user=False, flavor="normal"): - super(StoreInst, self).__init__() + super().__init__() self.name = mnem self.post = post @@ -88,7 +88,7 @@ let {{ decConstBase = 'Srs' def __init__(self, mnem, post, add, writeback): - super(SrsInst, self).__init__() + super().__init__() self.name = mnem self.post = post self.add = add @@ -145,7 +145,7 @@ let {{ class StoreImmInst(StoreInst): def __init__(self, *args, **kargs): - super(StoreImmInst, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = self.op + " imm" if self.add: @@ -155,7 +155,7 @@ let {{ class StoreRegInst(StoreInst): def __init__(self, *args, **kargs): - super(StoreRegInst, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ " shiftType, OptShiftRmCondCodesC)" if self.add: @@ -169,7 +169,7 @@ let {{ class StoreSingle(StoreInst): def __init__(self, *args, **kargs): - super(StoreSingle, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) # Build the default class name self.Name = self.nameFunc(self.post, self.add, self.writeback, @@ -235,7 +235,7 @@ let {{ nameFunc = staticmethod(storeImmClassName) def __init__(self, *args, **kargs): - super(StoreImmEx, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.codeBlobs["postacc_code"] = \ "Result = !writeResult; SevMailbox = 1; LLSCLock = 0;" @@ -254,7 +254,7 @@ let {{ class StoreDouble(StoreInst): def __init__(self, *args, **kargs): - super(StoreDouble, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) # Build the default class name self.Name = self.nameFunc(self.post, self.add, self.writeback) @@ -321,7 +321,7 @@ let {{ nameFunc = staticmethod(storeDoubleImmClassName) def __init__(self, *args, **kargs): - super(StoreDoubleImmEx, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.codeBlobs["postacc_code"] = \ "Result = !writeResult; SevMailbox = 1; LLSCLock = 0;" diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa index 93718591e3..ae50ee306f 100644 --- a/src/arch/arm/isa/insts/str64.isa +++ b/src/arch/arm/isa/insts/str64.isa @@ -47,7 +47,7 @@ let {{ def __init__(self, mnem, Name, size=4, user=False, flavor="normal", top = False): - super(StoreInst64, self).__init__() + super().__init__() self.name = mnem self.Name = Name @@ -143,14 +143,14 @@ let {{ class StoreImmInst64(StoreInst64): def __init__(self, *args, **kargs): - super(StoreImmInst64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = "+ imm" self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);" class StoreRegInst64(StoreInst64): def __init__(self, *args, **kargs): - super(StoreRegInst64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = "+ extendReg64(XOffset, type, shiftAmt, 64)" self.wbDecl = \ @@ -159,7 +159,7 @@ let {{ class StoreRawRegInst64(StoreInst64): def __init__(self, *args, **kargs): - super(StoreRawRegInst64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.offset = "" class StoreSingle64(StoreInst64): @@ -283,7 +283,7 @@ let {{ post = False execBase = 'StoreEx64' def __init__(self, *args, **kargs): - super(StoreEx64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.codeBlobs["postacc_code"] = \ "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" @@ -350,7 +350,7 @@ let {{ post = False writeback = False def __init__(self, *args, **kargs): - super(StoreImmDEx64, self).__init__(*args, **kargs) + super().__init__(*args, **kargs) self.codeBlobs["postacc_code"] = \ "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" diff --git a/src/arch/isa_parser/isa_parser.py b/src/arch/isa_parser/isa_parser.py index a110395a89..6e0373a57e 100755 --- a/src/arch/isa_parser/isa_parser.py +++ b/src/arch/isa_parser/isa_parser.py @@ -482,7 +482,7 @@ class InstObjParams(object): class ISAParser(Grammar): def __init__(self, output_dir): - super(ISAParser, self).__init__() + super().__init__() self.output_dir = output_dir self.filename = None # for output file watermarking/scaremongering @@ -1436,8 +1436,7 @@ StaticInstPtr # Create a wrapper class that allows us to grab the current parser. class InstObjParamsWrapper(InstObjParams): def __init__(iop, *args, **kwargs): - super(InstObjParamsWrapper, iop).__init__( - self, *args, **kwargs) + super().__init__(self, *args, **kwargs) self.exportContext['InstObjParams'] = InstObjParamsWrapper self.exportContext.update(self.templateMap) diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py index bc7815497f..8b493dab12 100755 --- a/src/arch/isa_parser/operand_types.py +++ b/src/arch/isa_parser/operand_types.py @@ -449,7 +449,7 @@ class VecRegOperand(Operand): return wb def finalize(self, predRead, predWrite): - super(VecRegOperand, self).finalize(predRead, predWrite) + super().finalize(predRead, predWrite) if self.is_dest: self.op_rd = self.makeReadW(predWrite) + self.op_rd @@ -585,7 +585,7 @@ class VecPredRegOperand(Operand): return wb def finalize(self, predRead, predWrite): - super(VecPredRegOperand, self).finalize(predRead, predWrite) + super().finalize(predRead, predWrite) if self.is_dest: self.op_rd = self.makeReadW(predWrite) + self.op_rd @@ -738,7 +738,7 @@ class MemOperand(Operand): class PCStateOperand(Operand): def __init__(self, parser, *args, **kwargs): - super(PCStateOperand, self).__init__(parser, *args, **kwargs) + super().__init__(parser, *args, **kwargs) self.parser = parser def makeConstructor(self, predRead, predWrite): diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py index 0305a024f8..5eac33d4aa 100644 --- a/src/arch/micro_asm.py +++ b/src/arch/micro_asm.py @@ -70,7 +70,7 @@ class Rom_Macroop(object): class Rom(Micro_Container): def __init__(self, name): - super(Rom, self).__init__(name) + super().__init__(name) self.externs = {} ########################################################################## @@ -96,14 +96,14 @@ class Statement(object): class Microop(Statement): def __init__(self): - super(Microop, self).__init__() + super().__init__() self.mnemonic = "" self.labels = [] self.is_microop = True class Directive(Statement): def __init__(self): - super(Directive, self).__init__() + super().__init__() self.name = "" self.is_directive = True diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py index 8bab7b9523..d3ad420580 100755 --- a/src/arch/micro_asm_test.py +++ b/src/arch/micro_asm_test.py @@ -59,7 +59,7 @@ class TestMacroop(Combinational_Macroop): print(message) def __init__(self, name): - super(TestMacroop, self).__init__(name) + super().__init__(name) self.directives = { "tweak": self.tweak, "untweak": self.untweak, diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 97646ff5f5..3710cf4d7a 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -158,7 +158,7 @@ let {{ self.control_indirect = True def __init__(self, name): - super(X86Macroop, self).__init__(name) + super().__init__(name) self.directives = { "adjust_env" : self.setAdjustEnv, "adjust_imm" : self.adjustImm, diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 9a0abd643e..aded50b472 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -89,7 +89,7 @@ let {{ def __init__(self, it): self.value = next(it) - super(ImmOp, self).__init__() + super().__init__() def ctor_args(self): return str(self.value) @@ -109,7 +109,7 @@ let {{ class RegisterOp(object): def __init__(self, it): self.idx = next(it) - super(RegisterOp, self).__init__() + super().__init__() def ctor_args(self): return str(self.idx) diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index 5023682d52..62c313f8df 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -136,8 +136,7 @@ let {{ class MicroDebugChild(MicroDebug): def __init__(self, message, flags=None): - super(MicroDebugChild, self).__init__( - name, fault_class, message, False, flags) + super().__init__(name, fault_class, message, False, flags) microopClasses[name] = MicroDebugChild @@ -148,7 +147,7 @@ let {{ class MicroDebugOnceChild(MicroDebug): def __init__(self, message, flags=None): - super(MicroDebugOnceChild, self).__init__( + super().__init__( name_once, fault_once_class, message, True, flags) microopClasses[name_once] = MicroDebugOnceChild diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index dc83362a0d..6fda08c82e 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -175,7 +175,7 @@ let {{ abstract = dict['abstract'] del dict['abstract'] - cls = super(FpOpMeta, mcls).__new__(mcls, Name, bases, dict) + cls = super().__new__(mcls, Name, bases, dict) if not abstract: cls.className = Name cls.mnemonic = name @@ -236,25 +236,25 @@ let {{ abstract = True operand_types = () def __init__(self, **kwargs): - super(Fp0Op, self).__init__(**kwargs) + super().__init__(**kwargs) class Fp1Op(FpOp): abstract = True operand_types = (FloatDestOp) def __init__(self, reg1, **kwargs): - super(Fp1Op, self).__init__(reg1, **kwargs) + super().__init__(reg1, **kwargs) class Fp2Op(FpOp): abstract = True operand_types = (FloatDestOp, FloatSrc1Op) def __init__(self, reg1, reg2, **kwargs): - super(Fp2Op, self).__init__(reg1, reg2, **kwargs) + super().__init__(reg1, reg2, **kwargs) class Fp3Op(FpOp): abstract = True operand_types = (FloatDestOp, FloatSrc1Op, FloatSrc2Op) def __init__(self, reg1, reg2, reg3, **kwargs): - super(Fp3Op, self).__init__(reg1, reg2, reg3, **kwargs) + super().__init__(reg1, reg2, reg3, **kwargs) class Movfp(Fp2Op): code = 'FpDestReg_uqw = FpSrcReg1_uqw;' diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 3c3b7e4847..72cb7bf530 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -389,7 +389,7 @@ let {{ def __init__(self, data, segment, addr, disp, dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec, implicitStack, uncacheable): - super(LdStSplitOp, self).__init__(0, segment, addr, disp, + super().__init__(0, segment, addr, disp, dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec, implicitStack, uncacheable) (self.dataLow, self.dataHi) = data @@ -503,7 +503,7 @@ let {{ addressSize=addressSize, atCPL0=False, prefetch=False, nonSpec=nonSpec, implicitStack=implicitStack, uncacheable=False): - super(LoadOp, self).__init__(data, segment, addr, + super().__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, atCPL0, prefetch, nonSpec, implicitStack, uncacheable) self.className = Name @@ -585,7 +585,7 @@ let {{ addressSize="env.addressSize", atCPL0=False, prefetch=False, nonSpec=nonSpec, implicitStack=False, uncacheable=False): - super(LoadOp, self).__init__(data, segment, addr, + super().__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, atCPL0, prefetch, nonSpec, implicitStack, uncacheable) self.className = Name @@ -646,7 +646,7 @@ let {{ dataSize="env.dataSize", addressSize=addressSize, atCPL0=False, nonSpec=False, implicitStack=implicitStack, uncacheable=False): - super(StoreOp, self).__init__(data, segment, addr, disp, + super().__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, atCPL0, False, nonSpec, implicitStack, uncacheable) self.className = Name @@ -655,7 +655,7 @@ let {{ class StoreOp(MemNoDataOp): def __init__(self, segment, addr, disp=0, dataSize="env.dataSize", addressSize=addressSize): - super(StoreOp, self).__init__(segment, addr, disp, + super().__init__(segment, addr, disp, dataSize, addressSize, mem_flags) self.className = Name self.mnemonic = name @@ -720,7 +720,7 @@ let {{ addressSize="env.addressSize", atCPL0=False, nonSpec=False, implicitStack=False, uncacheable=False): - super(StoreOp, self).__init__(data, segment, addr, disp, + super().__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, atCPL0, False, nonSpec, implicitStack, uncacheable) self.className = Name @@ -748,7 +748,7 @@ let {{ class LeaOp(LdStOp): def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize"): - super(LeaOp, self).__init__(data, segment, addr, disp, + super().__init__(data, segment, addr, disp, dataSize, addressSize, "0", False, False, False, False, False) self.className = "Lea" diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 7577728b71..7d765b21fc 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -128,7 +128,7 @@ let {{ if not "op_class" in dict: dict["op_class"] = None - cls = super(MediaOpMeta, mcls).__new__(mcls, Name, bases, dict) + cls = super().__new__(mcls, Name, bases, dict) if not abstract: cls.className = Name cls.base_mnemonic = name @@ -207,23 +207,23 @@ let {{ abstract = True operand_types = () def __init__(self, **kwargs): - super(Media0Op, self).__init__(**kwargs) + super().__init__(**kwargs) class Media2Op(MediaOp): abstract = True operand_types = (FloatDestOp, FloatSrc1Op) def __init__(self, op1, op2, **kwargs): - super(Media2Op, self).__init__(op1, op2, **kwargs) + super().__init__(op1, op2, **kwargs) class Media3Op(MediaOp): abstract = True operand_types = (FloatDestOp, FloatSrc1Op, FloatSrc2Op) def __init__(self, op1, op2, op3, **kwargs): - super(Media3Op, self).__init__(op1, op2, op3, **kwargs) + super().__init__(op1, op2, op3, **kwargs) class Mov2int(Media3Op): def __init__(self, dest, src1, src2=0, **kwargs): - super(Mov2int, self).__init__(dest, src1, src2, **kwargs) + super().__init__(dest, src1, src2, **kwargs) operand_types = (IntDestOp, FloatSrc1Op, Imm8Op) op_class = 'SimdMiscOp' code = ''' @@ -244,7 +244,7 @@ let {{ class Mov2fp(Media3Op): def __init__(self, dest, src1, src2=0, **kwargs): - super(Mov2fp, self).__init__(dest, src1, src2, **kwargs) + super().__init__(dest, src1, src2, **kwargs) operand_types = (FloatDestOp, IntSrc1Op, Imm8Op) op_class = 'SimdMiscOp' code = ''' @@ -445,7 +445,7 @@ let {{ class Mxor(Media3Op): def __init__(self, dest, src1, src2): - super(Mxor, self).__init__(dest, src1, src2, size=1) + super().__init__(dest, src1, src2, size=1) op_class = 'SimdAluOp' code = ''' FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw; @@ -453,7 +453,7 @@ let {{ class Mor(Media3Op): def __init__(self, dest, src1, src2): - super(Mor, self).__init__(dest, src1, src2, size=1) + super().__init__(dest, src1, src2, size=1) op_class = 'SimdAluOp' code = ''' FpDestReg_uqw = FpSrcReg1_uqw | FpSrcReg2_uqw; @@ -461,7 +461,7 @@ let {{ class Mand(Media3Op): def __init__(self, dest, src1, src2): - super(Mand, self).__init__(dest, src1, src2, size=1) + super().__init__(dest, src1, src2, size=1) op_class = 'SimdAluOp' code = ''' FpDestReg_uqw = FpSrcReg1_uqw & FpSrcReg2_uqw; @@ -469,7 +469,7 @@ let {{ class Mandn(Media3Op): def __init__(self, dest, src1, src2): - super(Mandn, self).__init__(dest, src1, src2, size=1) + super().__init__(dest, src1, src2, size=1) op_class = 'SimdAluOp' code = ''' FpDestReg_uqw = ~FpSrcReg1_uqw & FpSrcReg2_uqw; @@ -1551,7 +1551,7 @@ let {{ class Emms(Media0Op): def __init__(self): - super(Emms, self).__init__(size=2) + super().__init__(size=2) op_class = 'FloatMiscOp' code = 'FTW = 0xFFFF;' }}; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index c9e018b41b..e5f9e3dfde 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -279,7 +279,7 @@ let {{ abstract = dict['abstract'] del dict['abstract'] - cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) + cls = super().__new__(mcls, Name, bases, dict) if abstract: return cls @@ -392,8 +392,7 @@ let {{ def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): - super(BasicRegOp, self).__init__(dest, src1, src2, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, src2, flags=flags, dataSize=dataSize) class LogicRegOp(BasicRegOp): abstract = True @@ -451,15 +450,14 @@ let {{ def __init__(self, dest, src1=None, dataSize="env.dataSize"): if not src1: src1 = dest - super(RdRegOp, self).__init__(dest, src1, dataSize=dataSize) + super().__init__(dest, src1, dataSize=dataSize) class WrRegOp(RegOp): operand_types = (FoldedSrc1Op, Op2) abstract = True def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): - super(WrRegOp, self).__init__( - src1, src2, flags=flags, dataSize=dataSize) + super().__init__(src1, src2, flags=flags, dataSize=dataSize) class Add(FlagRegOp): code = ''' @@ -597,7 +595,7 @@ let {{ dataSize="env.dataSize"): if not src1: src1 = dest - super(RdRegOp, self).__init__(dest, src1, dataSize=dataSize) + super().__init__(dest, src1, dataSize=dataSize) code = 'DestReg = merge(SrcReg1, dest, ProdHi, dataSize);' big_code = 'DestReg = ProdHi & mask(dataSize * 8);' @@ -1222,8 +1220,7 @@ let {{ operand_types = (FoldedDestOp, Imm8Op) def __init__(self, dest, imm, flags=None, dataSize="env.dataSize"): - super(Ruflag, self).__init__(dest, imm, flags=flags, - dataSize=dataSize) + super().__init__(dest, imm, flags=flags, dataSize=dataSize) class Rflag(RegOp): code = ''' @@ -1248,8 +1245,7 @@ let {{ operand_types = (FoldedDestOp, Imm8Op) def __init__(self, dest, imm, flags=None, dataSize="env.dataSize"): - super(Rflag, self).__init__(dest, imm, flags=flags, - dataSize=dataSize) + super().__init__(dest, imm, flags=flags, dataSize=dataSize) class Sext(BasicRegOp): code = ''' @@ -1295,8 +1291,7 @@ let {{ class Rddr(RegOp): operand_types = (FoldedDestOp, DbgSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Rddr, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) rdrCode = ''' CR4 cr4 = CR4Op; DR7 dr7 = DR7Op; @@ -1314,8 +1309,7 @@ let {{ class Wrdr(RegOp): operand_types = (DbgDestOp, FoldedSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Wrdr, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) code = ''' CR4 cr4 = CR4Op; DR7 dr7 = DR7Op; @@ -1334,8 +1328,7 @@ let {{ class Rdcr(RegOp): operand_types = (FoldedDestOp, CrSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Rdcr, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) rdcrCode = ''' if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = std::make_shared(); @@ -1350,8 +1343,7 @@ let {{ class Wrcr(RegOp): operand_types = (CrDestOp, FoldedSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Wrcr, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) code = ''' if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { fault = std::make_shared(); @@ -1404,8 +1396,7 @@ let {{ abstract = True operand_types = (SegDestOp, FoldedSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(SegOp, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) class WrSegOp(SegOp): abstract = True @@ -1454,8 +1445,7 @@ let {{ class Rdval(RegOp): operand_types = (FoldedDestOp, MiscSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Rdval, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) code = ''' DestReg = MiscRegSrc1; ''' @@ -1463,8 +1453,7 @@ let {{ class Wrval(RegOp): operand_types = (MiscDestOp, FoldedSrc1Op) def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Wrval, self).__init__(dest, src1, flags=flags, - dataSize=dataSize) + super().__init__(dest, src1, flags=flags, dataSize=dataSize) code = ''' MiscRegDest = SrcReg1; ''' @@ -1473,8 +1462,7 @@ let {{ operand_types = (FoldedSrc1Op, FoldedSrc2Op, Imm8Op) def __init__(self, src1, src2, imm=0, flags=None, dataSize="env.dataSize"): - super(Chks, self).__init__(src1, src2, imm, flags=flags, - dataSize=dataSize) + super().__init__(src1, src2, imm, flags=flags, dataSize=dataSize) code = ''' // The selector is in source 1 and can be at most 16 bits. SegSelector selector = SrcReg1; @@ -1691,7 +1679,7 @@ let {{ class Wrxftw(RegOp): operand_types = (FoldedSrc1Op,) def __init__(self, src1, flags=None, dataSize="env.dataSize"): - super(Wrxftw, self).__init__(src1, flags=None, dataSize=dataSize) + super().__init__(src1, flags=None, dataSize=dataSize) code = ''' FTW = X86ISA::convX87XTagsToTags(SrcReg1); diff --git a/src/arch/x86/isa/rom.isa b/src/arch/x86/isa/rom.isa index f0153efb1a..4f97ac817a 100644 --- a/src/arch/x86/isa/rom.isa +++ b/src/arch/x86/isa/rom.isa @@ -42,7 +42,7 @@ let {{ class X86MicrocodeRom(Rom): def __init__(self, name): - super(X86MicrocodeRom, self).__init__(name) + super().__init__(name) self.directives = {} def add_microop(self, mnemonic, microop): diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index fb5cbe64b8..652a6949e8 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -302,5 +302,5 @@ class BaseCPU(ClockedObject): yield child_node def __init__(self, **kwargs): - super(BaseCPU, self).__init__(**kwargs) + super().__init__(**kwargs) self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF'] diff --git a/src/dev/IntPin.py b/src/dev/IntPin.py index 3d9f79b344..a6851cc7cb 100644 --- a/src/dev/IntPin.py +++ b/src/dev/IntPin.py @@ -33,18 +33,17 @@ Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE) # multiple sinks. class IntSourcePin(VectorPort): def __init__(self, desc): - super(IntSourcePin, self).__init__( - INT_SOURCE_ROLE, desc, is_source=True) + super().__init__(INT_SOURCE_ROLE, desc, is_source=True) # Each "physical" pin can be driven by a single source pin since there are no # provisions for resolving competing signals running to the same pin. class IntSinkPin(Port): def __init__(self, desc): - super(IntSinkPin, self).__init__(INT_SINK_ROLE, desc) + super().__init__(INT_SINK_ROLE, desc) # A vector of sink pins represents a bank of physical pins. For instance, an # interrupt controller with many numbered input interrupts could represent them # as a VectorIntSinkPin. class VectorIntSinkPin(VectorPort): def __init__(self, desc): - super(VectorIntSinkPin, self).__init__(INT_SINK_ROLE, desc) + super().__init__(INT_SINK_ROLE, desc) diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 837fe7ef44..2b86227380 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -604,7 +604,7 @@ class ParentMem(SimpleMemory): helper via the ParentMem interface. """ def __init__(self, *args, **kwargs): - super(ParentMem, self).__init__(*args, **kwargs) + super().__init__(*args, **kwargs) self._generators = [] def addSubnodeGenerator(self, gen): @@ -624,7 +624,7 @@ class ParentMem(SimpleMemory): class MmioSRAM(ParentMem): def __init__(self, *args, **kwargs): - super(MmioSRAM, self).__init__(**kwargs) + super().__init__(**kwargs) def generateDeviceTree(self, state): node = FdtNode("sram@%x" % int(self.range.start)) @@ -913,8 +913,7 @@ class VExpress_EMM(RealView): def setupBootLoader(self, cur_sys, loc, boot_loader=None): if boot_loader is None: boot_loader = loc('boot_emm.arm') - super(VExpress_EMM, self).setupBootLoader( - cur_sys, boot_loader, 0x8000000, 0x80000000) + super().setupBootLoader(cur_sys, boot_loader, 0x8000000, 0x80000000) class VExpress_EMM64(VExpress_EMM): # Three memory regions are specified totalling 512GiB @@ -1230,7 +1229,7 @@ Interrupts: ] def __init__(self, **kwargs): - super(VExpress_GEM5_Base, self).__init__(**kwargs) + super().__init__(**kwargs) self.clock32KHz.voltage_domain = self.io_voltage self.clock24MHz.voltage_domain = self.io_voltage self.system_watchdog.clk_domain = self.dcc.osc_sys @@ -1273,8 +1272,7 @@ Interrupts: self.smmu.connect(dev) def setupBootLoader(self, cur_sys, boot_loader): - super(VExpress_GEM5_Base, self).setupBootLoader( - cur_sys, boot_loader, 0x8000000, 0x80000000) + super().setupBootLoader(cur_sys, boot_loader, 0x8000000, 0x80000000) # Setup m5ops. It's technically not a part of the boot # loader, but this is the only place we can configure the @@ -1302,7 +1300,7 @@ Interrupts: def generateDeviceTree(self, state): # Generate using standard RealView function - dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) + dt = list(super().generateDeviceTree(state)) if len(dt) > 1: raise Exception("System returned too many DT nodes") node = dt[0] @@ -1344,11 +1342,10 @@ class VExpress_GEM5_V1_Base(VExpress_GEM5_Base): def setupBootLoader(self, cur_sys, loc, boot_loader=None): if boot_loader is None: boot_loader = [ loc('boot.arm64'), loc('boot.arm') ] - super(VExpress_GEM5_V1_Base, self).setupBootLoader( - cur_sys, boot_loader) + super().setupBootLoader(cur_sys, boot_loader) def _on_chip_devices(self): - return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [ + return super()._on_chip_devices() + [ self.gic, self.vgic, self.gicv2m, ] @@ -1364,9 +1361,7 @@ class VExpress_GEM5_V1_HDLcd(VExpress_GEM5_V1_Base): pio_addr=0x2b000000, interrupt=ArmSPI(num=95)) def _on_chip_devices(self): - return super(VExpress_GEM5_V1_HDLcd,self)._on_chip_devices() + [ - self.hdlcd, - ] + return super()._on_chip_devices() + [self.hdlcd,] class VExpress_GEM5_V2_Base(VExpress_GEM5_Base): gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000, @@ -1377,15 +1372,12 @@ class VExpress_GEM5_V2_Base(VExpress_GEM5_Base): gic.cpu_max = 128 def _on_chip_devices(self): - return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ - self.gic, self.gic.its - ] + return super()._on_chip_devices() + [self.gic, self.gic.its] def setupBootLoader(self, cur_sys, loc, boot_loader=None): if boot_loader is None: boot_loader = [ loc('boot_v2.arm64') ] - super(VExpress_GEM5_V2_Base, self).setupBootLoader( - cur_sys, boot_loader) + super().setupBootLoader(cur_sys, boot_loader) class VExpress_GEM5_V2(VExpress_GEM5_V2_Base): """ @@ -1399,9 +1391,7 @@ class VExpress_GEM5_V2_HDLcd(VExpress_GEM5_V2_Base): pio_addr=0x2b000000, interrupt=ArmSPI(num=95)) def _on_chip_devices(self): - return super(VExpress_GEM5_V2_HDLcd,self)._on_chip_devices() + [ - self.hdlcd, - ] + return super()._on_chip_devices() + [self.hdlcd,] class VExpress_GEM5_Foundation(VExpress_GEM5_Base): """ @@ -1439,18 +1429,12 @@ class VExpress_GEM5_Foundation(VExpress_GEM5_Base): int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) def _on_chip_devices(self): - return super(VExpress_GEM5_Foundation, self)._on_chip_devices() + [ - self.gic - ] + return super()._on_chip_devices() + [self.gic] def _off_chip_devices(self): - return super(VExpress_GEM5_Foundation, self)._off_chip_devices() + [ - self.clcd, - self.sp810_fake, - ] + return super()._off_chip_devices() + [self.clcd, self.sp810_fake,] def setupBootLoader(self, cur_sys, loc, boot_loader=None): if boot_loader is None: boot_loader = [ loc('boot_v2.arm64') ] - super(VExpress_GEM5_Foundation, self).setupBootLoader( - cur_sys, boot_loader) + super().setupBootLoader(cur_sys, boot_loader) diff --git a/src/dev/arm/VExpressFastmodel.py b/src/dev/arm/VExpressFastmodel.py index a6b9b34265..6f9a731d3a 100644 --- a/src/dev/arm/VExpressFastmodel.py +++ b/src/dev/arm/VExpressFastmodel.py @@ -57,5 +57,4 @@ class VExpressFastmodel(VExpress_GEM5_Base): def setupBootLoader(self, cur_sys, loc, boot_loader=None): if boot_loader is None: boot_loader = [ loc('boot_v2.arm64') ] - super(VExpressFastmodel, self).setupBootLoader( - cur_sys, boot_loader) + super().setupBootLoader(cur_sys, boot_loader) diff --git a/src/dev/arm/css/Scmi.py b/src/dev/arm/css/Scmi.py index 0e14cf5401..4b51fa8593 100644 --- a/src/dev/arm/css/Scmi.py +++ b/src/dev/arm/css/Scmi.py @@ -57,7 +57,7 @@ class ScmiChannel(SimObject): "This is the doorbell used to notify the SCMI platform") def __init__(self, shmem, *args, **kwargs): - super(ScmiChannel, self).__init__(**kwargs) + super().__init__(**kwargs) def shmemGenerator(state): shmem_node = FdtNode("scp-shmem@%x" % 0) diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py index 15a7fe30fe..1753d48867 100644 --- a/src/dev/net/Ethernet.py +++ b/src/dev/net/Ethernet.py @@ -47,11 +47,11 @@ Port.compat(ETHERNET_ROLE, ETHERNET_ROLE) class EtherInt(Port): def __init__(self, desc): - super(EtherInt, self).__init__(ETHERNET_ROLE, desc) + super().__init__(ETHERNET_ROLE, desc) class VectorEtherInt(VectorPort): def __init__(self, desc): - super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc) + super().__init__(ETHERNET_ROLE, desc) class EtherLink(SimObject): type = 'EtherLink' diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 62b5841f44..7d704881b4 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -85,7 +85,7 @@ class BasePrefetcher(ClockedObject): "Size of pages for virtual addresses") def __init__(self, **kwargs): - super(BasePrefetcher, self).__init__(**kwargs) + super().__init__(**kwargs) self._events = [] self._tlbs = [] diff --git a/src/mem/slicc/ast/ActionDeclAST.py b/src/mem/slicc/ast/ActionDeclAST.py index 95a8b63229..22a782dd3e 100644 --- a/src/mem/slicc/ast/ActionDeclAST.py +++ b/src/mem/slicc/ast/ActionDeclAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Action, Type, Var class ActionDeclAST(DeclAST): def __init__(self, slicc, ident, pairs, statement_list): - super(ActionDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.ident = ident self.statement_list = statement_list diff --git a/src/mem/slicc/ast/AssignStatementAST.py b/src/mem/slicc/ast/AssignStatementAST.py index d3e449d4e3..89bafbd701 100644 --- a/src/mem/slicc/ast/AssignStatementAST.py +++ b/src/mem/slicc/ast/AssignStatementAST.py @@ -29,7 +29,7 @@ from slicc.ast.StatementAST import StatementAST class AssignStatementAST(StatementAST): def __init__(self, slicc, lvalue, rvalue): - super(AssignStatementAST, self).__init__(slicc) + super().__init__(slicc) self.lvalue = lvalue self.rvalue = rvalue diff --git a/src/mem/slicc/ast/CheckAllocateStatementAST.py b/src/mem/slicc/ast/CheckAllocateStatementAST.py index 425e8053d7..8bbe906fea 100644 --- a/src/mem/slicc/ast/CheckAllocateStatementAST.py +++ b/src/mem/slicc/ast/CheckAllocateStatementAST.py @@ -29,7 +29,7 @@ from slicc.ast.StatementAST import StatementAST class CheckAllocateStatementAST(StatementAST): def __init__(self, slicc, variable): - super(StatementAST, self).__init__(slicc) + super().__init__(slicc) self.variable = variable def __repr__(self): diff --git a/src/mem/slicc/ast/CheckNextCycleAST.py b/src/mem/slicc/ast/CheckNextCycleAST.py index f3797755e8..a4db8c4a26 100644 --- a/src/mem/slicc/ast/CheckNextCycleAST.py +++ b/src/mem/slicc/ast/CheckNextCycleAST.py @@ -30,7 +30,7 @@ from slicc.ast.StatementAST import StatementAST class CheckNextCycleAST(StatementAST): def __init__(self, slicc): - super(CheckNextCycleAST, self).__init__(slicc) + super().__init__(slicc) def __repr__(self): return "[CheckNextCycleAST]" diff --git a/src/mem/slicc/ast/CheckProbeStatementAST.py b/src/mem/slicc/ast/CheckProbeStatementAST.py index 0d84bbce43..995c803762 100644 --- a/src/mem/slicc/ast/CheckProbeStatementAST.py +++ b/src/mem/slicc/ast/CheckProbeStatementAST.py @@ -30,7 +30,7 @@ from slicc.ast.StatementAST import StatementAST class CheckProbeStatementAST(StatementAST): def __init__(self, slicc, in_port, address): - super(StatementAST, self).__init__(slicc) + super().__init__(slicc) self.in_port = in_port self.address = address diff --git a/src/mem/slicc/ast/DeclAST.py b/src/mem/slicc/ast/DeclAST.py index 8b0f4ea961..ce3f252316 100644 --- a/src/mem/slicc/ast/DeclAST.py +++ b/src/mem/slicc/ast/DeclAST.py @@ -29,7 +29,7 @@ from slicc.ast.AST import AST class DeclAST(AST): def __init__(self, slicc, pairs = None): - super(DeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) def files(self, parent=None): return set() diff --git a/src/mem/slicc/ast/DeclListAST.py b/src/mem/slicc/ast/DeclListAST.py index 4ba41ed6c2..4e1538c224 100644 --- a/src/mem/slicc/ast/DeclListAST.py +++ b/src/mem/slicc/ast/DeclListAST.py @@ -29,7 +29,7 @@ from slicc.ast.AST import AST class DeclListAST(AST): def __init__(self, slicc, decls): - super(DeclListAST, self).__init__(slicc) + super().__init__(slicc) if not isinstance(decls, (list, tuple)): decls = [ decls ] diff --git a/src/mem/slicc/ast/DeferEnqueueingStatementAST.py b/src/mem/slicc/ast/DeferEnqueueingStatementAST.py index 368ac30a1e..5bd71235e4 100644 --- a/src/mem/slicc/ast/DeferEnqueueingStatementAST.py +++ b/src/mem/slicc/ast/DeferEnqueueingStatementAST.py @@ -35,7 +35,7 @@ from slicc.symbols import Var class DeferEnqueueingStatementAST(StatementAST): def __init__(self, slicc, queue_name, type_ast, statements): - super(DeferEnqueueingStatementAST, self).__init__(slicc) + super().__init__(slicc) self.queue_name = queue_name self.type_ast = type_ast diff --git a/src/mem/slicc/ast/EnqueueStatementAST.py b/src/mem/slicc/ast/EnqueueStatementAST.py index a8c157e426..ea2a45f65a 100644 --- a/src/mem/slicc/ast/EnqueueStatementAST.py +++ b/src/mem/slicc/ast/EnqueueStatementAST.py @@ -31,7 +31,7 @@ from slicc.symbols import Var class EnqueueStatementAST(StatementAST): def __init__(self, slicc, queue_name, type_ast, lexpr, statements): - super(EnqueueStatementAST, self).__init__(slicc) + super().__init__(slicc) self.queue_name = queue_name self.type_ast = type_ast diff --git a/src/mem/slicc/ast/EnumDeclAST.py b/src/mem/slicc/ast/EnumDeclAST.py index d97c134831..9694dd965c 100644 --- a/src/mem/slicc/ast/EnumDeclAST.py +++ b/src/mem/slicc/ast/EnumDeclAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Func, Type class EnumDeclAST(DeclAST): def __init__(self, slicc, type_ast, pairs, fields): - super(EnumDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.type_ast = type_ast self.fields = fields diff --git a/src/mem/slicc/ast/EnumExprAST.py b/src/mem/slicc/ast/EnumExprAST.py index 27da269e90..52e430539b 100644 --- a/src/mem/slicc/ast/EnumExprAST.py +++ b/src/mem/slicc/ast/EnumExprAST.py @@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST class EnumExprAST(ExprAST): def __init__(self, slicc, type_ast, value): - super(EnumExprAST, self).__init__(slicc) + super().__init__(slicc) assert type_ast assert value diff --git a/src/mem/slicc/ast/ExprAST.py b/src/mem/slicc/ast/ExprAST.py index 75554b2d3f..0b0a0ecca3 100644 --- a/src/mem/slicc/ast/ExprAST.py +++ b/src/mem/slicc/ast/ExprAST.py @@ -28,7 +28,7 @@ from slicc.ast.AST import AST class ExprAST(AST): def __init__(self, slicc): - super(ExprAST, self).__init__(slicc) + super().__init__(slicc) def findResources(self, resources): # The default is no resources diff --git a/src/mem/slicc/ast/ExprStatementAST.py b/src/mem/slicc/ast/ExprStatementAST.py index 7189df0401..037163eaf5 100644 --- a/src/mem/slicc/ast/ExprStatementAST.py +++ b/src/mem/slicc/ast/ExprStatementAST.py @@ -32,7 +32,7 @@ from slicc.symbols import Type class ExprStatementAST(StatementAST): def __init__(self, slicc, expr): - super(ExprStatementAST, self).__init__(slicc) + super().__init__(slicc) self.expr = expr def __repr__(self): diff --git a/src/mem/slicc/ast/FormalParamAST.py b/src/mem/slicc/ast/FormalParamAST.py index 57f5c94e3a..9f17101c5c 100644 --- a/src/mem/slicc/ast/FormalParamAST.py +++ b/src/mem/slicc/ast/FormalParamAST.py @@ -42,7 +42,7 @@ from slicc.symbols import Var class FormalParamAST(AST): def __init__(self, slicc, type_ast, ident, default = None, qualifier=""): - super(FormalParamAST, self).__init__(slicc) + super().__init__(slicc) self.type_ast = type_ast self.ident = ident self.default = default diff --git a/src/mem/slicc/ast/FuncCallExprAST.py b/src/mem/slicc/ast/FuncCallExprAST.py index d93ee04e96..e7046edab2 100644 --- a/src/mem/slicc/ast/FuncCallExprAST.py +++ b/src/mem/slicc/ast/FuncCallExprAST.py @@ -43,7 +43,7 @@ from slicc.symbols import Func, Type class FuncCallExprAST(ExprAST): def __init__(self, slicc, proc_name, exprs): - super(FuncCallExprAST, self).__init__(slicc) + super().__init__(slicc) self.proc_name = proc_name self.exprs = exprs diff --git a/src/mem/slicc/ast/FuncDeclAST.py b/src/mem/slicc/ast/FuncDeclAST.py index 675c408134..ab2a1c6b8b 100644 --- a/src/mem/slicc/ast/FuncDeclAST.py +++ b/src/mem/slicc/ast/FuncDeclAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Func, Type class FuncDeclAST(DeclAST): def __init__(self, slicc, return_type, ident, formals, pairs, statements): - super(FuncDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.return_type = return_type self.ident = ident diff --git a/src/mem/slicc/ast/IfStatementAST.py b/src/mem/slicc/ast/IfStatementAST.py index 2ddd7c0525..cbacfd3634 100644 --- a/src/mem/slicc/ast/IfStatementAST.py +++ b/src/mem/slicc/ast/IfStatementAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Type class IfStatementAST(StatementAST): def __init__(self, slicc, cond, then, else_): - super(IfStatementAST, self).__init__(slicc) + super().__init__(slicc) assert cond is not None assert then is not None diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py index 8e80b6ad1c..362a75dec3 100644 --- a/src/mem/slicc/ast/InPortDeclAST.py +++ b/src/mem/slicc/ast/InPortDeclAST.py @@ -43,7 +43,7 @@ from slicc.symbols import Func, Type, Var class InPortDeclAST(DeclAST): def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements): - super(InPortDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.ident = ident self.msg_type = msg_type diff --git a/src/mem/slicc/ast/IsValidPtrExprAST.py b/src/mem/slicc/ast/IsValidPtrExprAST.py index a7d89a9b83..d5c4c38882 100644 --- a/src/mem/slicc/ast/IsValidPtrExprAST.py +++ b/src/mem/slicc/ast/IsValidPtrExprAST.py @@ -31,7 +31,7 @@ from slicc.symbols import Type class IsValidPtrExprAST(ExprAST): def __init__(self, slicc, variable, flag): - super(IsValidPtrExprAST, self).__init__(slicc) + super().__init__(slicc) self.variable = variable self.flag = flag diff --git a/src/mem/slicc/ast/LiteralExprAST.py b/src/mem/slicc/ast/LiteralExprAST.py index 59756b173f..a5ffa20591 100644 --- a/src/mem/slicc/ast/LiteralExprAST.py +++ b/src/mem/slicc/ast/LiteralExprAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Type class LiteralExprAST(ExprAST): def __init__(self, slicc, literal, type): - super(LiteralExprAST, self).__init__(slicc) + super().__init__(slicc) self.literal = literal self.type = type diff --git a/src/mem/slicc/ast/LocalVariableAST.py b/src/mem/slicc/ast/LocalVariableAST.py index da75477c89..481c9a1b6a 100644 --- a/src/mem/slicc/ast/LocalVariableAST.py +++ b/src/mem/slicc/ast/LocalVariableAST.py @@ -32,7 +32,7 @@ from slicc.symbols import Var class LocalVariableAST(StatementAST): def __init__(self, slicc, type_ast, ident, pointer = False): - super(LocalVariableAST, self).__init__(slicc) + super().__init__(slicc) self.type_ast = type_ast self.ident = ident self.pointer = pointer diff --git a/src/mem/slicc/ast/MachineAST.py b/src/mem/slicc/ast/MachineAST.py index c67d0e6953..7434d6bbcf 100644 --- a/src/mem/slicc/ast/MachineAST.py +++ b/src/mem/slicc/ast/MachineAST.py @@ -30,7 +30,7 @@ from slicc.symbols import StateMachine, Type class MachineAST(DeclAST): def __init__(self, slicc, mtype, pairs_ast, config_parameters, decls): - super(MachineAST, self).__init__(slicc, pairs_ast) + super().__init__(slicc, pairs_ast) self.ident = mtype.value self.pairs_ast = pairs_ast diff --git a/src/mem/slicc/ast/MemberExprAST.py b/src/mem/slicc/ast/MemberExprAST.py index 50151bd0a2..a6e359175a 100644 --- a/src/mem/slicc/ast/MemberExprAST.py +++ b/src/mem/slicc/ast/MemberExprAST.py @@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST class MemberExprAST(ExprAST): def __init__(self, slicc, expr_ast, field): - super(MemberExprAST, self).__init__(slicc) + super().__init__(slicc) self.expr_ast = expr_ast self.field = field diff --git a/src/mem/slicc/ast/MethodCallExprAST.py b/src/mem/slicc/ast/MethodCallExprAST.py index 9908fc815c..e08cc053d1 100644 --- a/src/mem/slicc/ast/MethodCallExprAST.py +++ b/src/mem/slicc/ast/MethodCallExprAST.py @@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST class MethodCallExprAST(ExprAST): def __init__(self, slicc, proc_name, expr_ast_vec): - super(MethodCallExprAST, self).__init__(slicc) + super().__init__(slicc) self.proc_name = proc_name self.expr_ast_vec = expr_ast_vec @@ -67,7 +67,7 @@ class MethodCallExprAST(ExprAST): class MemberMethodCallExprAST(MethodCallExprAST): def __init__(self, slicc, obj_expr_ast, func_call): - s = super(MemberMethodCallExprAST, self) + s = super() s.__init__(slicc, func_call.proc_name, func_call.exprs) self.obj_expr_ast = obj_expr_ast @@ -157,7 +157,7 @@ class MemberMethodCallExprAST(MethodCallExprAST): class ClassMethodCallExprAST(MethodCallExprAST): def __init__(self, slicc, type_ast, proc_name, expr_ast_vec): - s = super(ClassMethodCallExprAST, self) + s = super() s.__init__(slicc, proc_name, expr_ast_vec) self.type_ast = type_ast diff --git a/src/mem/slicc/ast/NewExprAST.py b/src/mem/slicc/ast/NewExprAST.py index 2f33bfac35..b0967147f5 100644 --- a/src/mem/slicc/ast/NewExprAST.py +++ b/src/mem/slicc/ast/NewExprAST.py @@ -29,7 +29,7 @@ from slicc.ast.ExprAST import ExprAST class NewExprAST(ExprAST): def __init__(self, slicc, type_ast): - super(NewExprAST, self).__init__(slicc) + super().__init__(slicc) self.type_ast = type_ast def __repr__(self): diff --git a/src/mem/slicc/ast/ObjDeclAST.py b/src/mem/slicc/ast/ObjDeclAST.py index 523a491abc..2ab956298e 100644 --- a/src/mem/slicc/ast/ObjDeclAST.py +++ b/src/mem/slicc/ast/ObjDeclAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Var class ObjDeclAST(DeclAST): def __init__(self, slicc, type_ast, ident, pairs, rvalue, pointer): - super(ObjDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.type_ast = type_ast self.ident = ident diff --git a/src/mem/slicc/ast/OodAST.py b/src/mem/slicc/ast/OodAST.py index 173a1566e2..1de0c14265 100644 --- a/src/mem/slicc/ast/OodAST.py +++ b/src/mem/slicc/ast/OodAST.py @@ -30,7 +30,7 @@ from slicc.ast.ExprAST import ExprAST class OodAST(ExprAST): def __init__(self, slicc): - super(OodAST, self).__init__(slicc) + super().__init__(slicc) def __repr__(self): return "[Ood:]" diff --git a/src/mem/slicc/ast/OperatorExprAST.py b/src/mem/slicc/ast/OperatorExprAST.py index 5c5ea834f0..a75568e6cc 100644 --- a/src/mem/slicc/ast/OperatorExprAST.py +++ b/src/mem/slicc/ast/OperatorExprAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Type class InfixOperatorExprAST(ExprAST): def __init__(self, slicc, left, op, right): - super(InfixOperatorExprAST, self).__init__(slicc) + super().__init__(slicc) self.left = left self.op = op @@ -96,7 +96,7 @@ class InfixOperatorExprAST(ExprAST): class PrefixOperatorExprAST(ExprAST): def __init__(self, slicc, op, operand): - super(PrefixOperatorExprAST, self).__init__(slicc) + super().__init__(slicc) self.op = op self.operand = operand diff --git a/src/mem/slicc/ast/OutPortDeclAST.py b/src/mem/slicc/ast/OutPortDeclAST.py index 39795ef7ee..d84f9e8604 100644 --- a/src/mem/slicc/ast/OutPortDeclAST.py +++ b/src/mem/slicc/ast/OutPortDeclAST.py @@ -32,7 +32,7 @@ from slicc.symbols import Type class OutPortDeclAST(DeclAST): def __init__(self, slicc, ident, msg_type, var_expr, pairs): - super(OutPortDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.ident = ident self.msg_type = msg_type diff --git a/src/mem/slicc/ast/PairAST.py b/src/mem/slicc/ast/PairAST.py index 347f4d361c..fa56a686c3 100644 --- a/src/mem/slicc/ast/PairAST.py +++ b/src/mem/slicc/ast/PairAST.py @@ -28,7 +28,7 @@ from slicc.ast.AST import AST class PairAST(AST): def __init__(self, slicc, key, value): - super(PairAST, self).__init__(slicc) + super().__init__(slicc) self.key = key self.value = value diff --git a/src/mem/slicc/ast/PairListAST.py b/src/mem/slicc/ast/PairListAST.py index 6afe3f4fae..d195ea2088 100644 --- a/src/mem/slicc/ast/PairListAST.py +++ b/src/mem/slicc/ast/PairListAST.py @@ -28,7 +28,7 @@ from slicc.ast.AST import AST class PairListAST(AST): def __init__(self, slicc): - super(PairListAST, self).__init__(slicc) + super().__init__(slicc) def __repr__(self): return "[PairListAST] %r" % self.pairs diff --git a/src/mem/slicc/ast/PeekStatementAST.py b/src/mem/slicc/ast/PeekStatementAST.py index 68a346261e..d0fa306e61 100644 --- a/src/mem/slicc/ast/PeekStatementAST.py +++ b/src/mem/slicc/ast/PeekStatementAST.py @@ -31,7 +31,7 @@ from slicc.symbols import Var class PeekStatementAST(StatementAST): def __init__(self, slicc, queue_name, type_ast, pairs, statements, method): - super(PeekStatementAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.queue_name = queue_name self.type_ast = type_ast diff --git a/src/mem/slicc/ast/ReturnStatementAST.py b/src/mem/slicc/ast/ReturnStatementAST.py index 415d442c7d..320a53a2a7 100644 --- a/src/mem/slicc/ast/ReturnStatementAST.py +++ b/src/mem/slicc/ast/ReturnStatementAST.py @@ -29,7 +29,7 @@ from slicc.ast.StatementAST import StatementAST class ReturnStatementAST(StatementAST): def __init__(self, slicc, expr_ast): - super(ReturnStatementAST, self).__init__(slicc) + super().__init__(slicc) self.expr_ast = expr_ast diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py index 04d9e20ed0..eb0d3e38d5 100644 --- a/src/mem/slicc/ast/StallAndWaitStatementAST.py +++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py @@ -30,7 +30,7 @@ from slicc.ast.StatementAST import StatementAST class StallAndWaitStatementAST(StatementAST): def __init__(self, slicc, in_port, address): - super(StatementAST, self).__init__(slicc) + super().__init__(slicc) self.in_port = in_port self.address = address diff --git a/src/mem/slicc/ast/StateDeclAST.py b/src/mem/slicc/ast/StateDeclAST.py index f0a0b97d37..300080eb61 100644 --- a/src/mem/slicc/ast/StateDeclAST.py +++ b/src/mem/slicc/ast/StateDeclAST.py @@ -29,7 +29,7 @@ from slicc.symbols import Func, Type class StateDeclAST(DeclAST): def __init__(self, slicc, type_ast, pairs, states): - super(StateDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.type_ast = type_ast self.states = states diff --git a/src/mem/slicc/ast/StatementAST.py b/src/mem/slicc/ast/StatementAST.py index 017b2b1ede..8999204d58 100644 --- a/src/mem/slicc/ast/StatementAST.py +++ b/src/mem/slicc/ast/StatementAST.py @@ -28,7 +28,7 @@ from slicc.ast.AST import AST class StatementAST(AST): def __init__(self, slicc, pairs=None): - super(StatementAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) def findResources(self, resources): pass diff --git a/src/mem/slicc/ast/StatementListAST.py b/src/mem/slicc/ast/StatementListAST.py index 9d74e66dc3..5f7bc549c9 100644 --- a/src/mem/slicc/ast/StatementListAST.py +++ b/src/mem/slicc/ast/StatementListAST.py @@ -29,7 +29,7 @@ from slicc.ast.AST import AST class StatementListAST(AST): def __init__(self, slicc, statements): - super(StatementListAST, self).__init__(slicc) + super().__init__(slicc) if not isinstance(statements, (list, tuple)): statements = [ statements ] self.statements = statements diff --git a/src/mem/slicc/ast/StaticCastAST.py b/src/mem/slicc/ast/StaticCastAST.py index 4c664865a1..4e2d580a71 100644 --- a/src/mem/slicc/ast/StaticCastAST.py +++ b/src/mem/slicc/ast/StaticCastAST.py @@ -28,7 +28,7 @@ from slicc.ast.ExprAST import ExprAST class StaticCastAST(ExprAST): def __init__(self, slicc, type_ast, type_modifier, expr_ast): - super(StaticCastAST, self).__init__(slicc) + super().__init__(slicc) self.type_ast = type_ast self.expr_ast = expr_ast diff --git a/src/mem/slicc/ast/TransitionDeclAST.py b/src/mem/slicc/ast/TransitionDeclAST.py index 2de7079405..18c1b80b73 100644 --- a/src/mem/slicc/ast/TransitionDeclAST.py +++ b/src/mem/slicc/ast/TransitionDeclAST.py @@ -31,7 +31,7 @@ from slicc.symbols import Transition class TransitionDeclAST(DeclAST): def __init__(self, slicc, request_types, states, events, next_state, actions): - super(TransitionDeclAST, self).__init__(slicc) + super().__init__(slicc) self.request_types = request_types self.states = states diff --git a/src/mem/slicc/ast/TypeAST.py b/src/mem/slicc/ast/TypeAST.py index 209859b8d8..fccff9c20b 100644 --- a/src/mem/slicc/ast/TypeAST.py +++ b/src/mem/slicc/ast/TypeAST.py @@ -31,7 +31,7 @@ from slicc.symbols import Type class TypeAST(AST): def __init__(self, slicc, ident): - super(TypeAST, self).__init__(slicc) + super().__init__(slicc) self.ident = ident diff --git a/src/mem/slicc/ast/TypeDeclAST.py b/src/mem/slicc/ast/TypeDeclAST.py index 8a58853ac6..f4c4c8e1c7 100644 --- a/src/mem/slicc/ast/TypeDeclAST.py +++ b/src/mem/slicc/ast/TypeDeclAST.py @@ -30,7 +30,7 @@ from slicc.symbols.Type import Type class TypeDeclAST(DeclAST): def __init__(self, slicc, type_ast, pairs, field_asts): - super(TypeDeclAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) self.type_ast = type_ast self.field_asts = field_asts diff --git a/src/mem/slicc/ast/TypeFieldAST.py b/src/mem/slicc/ast/TypeFieldAST.py index 7dd4c74aa7..18d1513bc4 100644 --- a/src/mem/slicc/ast/TypeFieldAST.py +++ b/src/mem/slicc/ast/TypeFieldAST.py @@ -29,4 +29,4 @@ from slicc.ast.AST import AST class TypeFieldAST(AST): def __init__(self, slicc, pairs): - super(TypeFieldAST, self).__init__(slicc, pairs) + super().__init__(slicc, pairs) diff --git a/src/mem/slicc/ast/TypeFieldEnumAST.py b/src/mem/slicc/ast/TypeFieldEnumAST.py index f554990579..293bca8962 100644 --- a/src/mem/slicc/ast/TypeFieldEnumAST.py +++ b/src/mem/slicc/ast/TypeFieldEnumAST.py @@ -30,7 +30,7 @@ from slicc.symbols import Event, State, RequestType class TypeFieldEnumAST(TypeFieldAST): def __init__(self, slicc, field_id, pairs_ast): - super(TypeFieldEnumAST, self).__init__(slicc, pairs_ast) + super().__init__(slicc, pairs_ast) self.field_id = field_id self.pairs_ast = pairs_ast diff --git a/src/mem/slicc/ast/TypeFieldStateAST.py b/src/mem/slicc/ast/TypeFieldStateAST.py index ff1ae9720a..61e0b28aa0 100644 --- a/src/mem/slicc/ast/TypeFieldStateAST.py +++ b/src/mem/slicc/ast/TypeFieldStateAST.py @@ -29,7 +29,7 @@ from slicc.symbols import Event, State class TypeFieldStateAST(TypeFieldAST): def __init__(self, slicc, field_id, perm_ast, pairs_ast): - super(TypeFieldStateAST, self).__init__(slicc, pairs_ast) + super().__init__(slicc, pairs_ast) self.field_id = field_id self.perm_ast = perm_ast diff --git a/src/mem/slicc/ast/VarExprAST.py b/src/mem/slicc/ast/VarExprAST.py index f555c72d14..f9f3eb1fc8 100644 --- a/src/mem/slicc/ast/VarExprAST.py +++ b/src/mem/slicc/ast/VarExprAST.py @@ -31,7 +31,7 @@ from slicc.symbols import Type, Var class VarExprAST(ExprAST): def __init__(self, slicc, var): - super(VarExprAST, self).__init__(slicc) + super().__init__(slicc) self._var = var def __repr__(self): diff --git a/src/mem/slicc/ast/WakeupPortStatementAST.py b/src/mem/slicc/ast/WakeupPortStatementAST.py index cea3d32a11..293d5a3a09 100644 --- a/src/mem/slicc/ast/WakeupPortStatementAST.py +++ b/src/mem/slicc/ast/WakeupPortStatementAST.py @@ -37,7 +37,7 @@ from slicc.ast.StatementAST import StatementAST class WakeupPortStatementAST(StatementAST): def __init__(self, slicc, in_port, address): - super(StatementAST, self).__init__(slicc) + super().__init__(slicc) self.in_port = in_port self.address = address diff --git a/src/mem/slicc/symbols/Action.py b/src/mem/slicc/symbols/Action.py index 880fab15ac..3c7f70c0e2 100644 --- a/src/mem/slicc/symbols/Action.py +++ b/src/mem/slicc/symbols/Action.py @@ -29,7 +29,7 @@ from slicc.symbols.Symbol import Symbol class Action(Symbol): def __init__(self, table, ident, resources, location, pairs): - super(Action, self).__init__(table, ident, location, pairs) + super().__init__(table, ident, location, pairs) self.resources = resources def __repr__(self): diff --git a/src/mem/slicc/symbols/Func.py b/src/mem/slicc/symbols/Func.py index 6da74002a8..8a73a5c800 100644 --- a/src/mem/slicc/symbols/Func.py +++ b/src/mem/slicc/symbols/Func.py @@ -31,7 +31,7 @@ from slicc.symbols.Type import Type class Func(Symbol): def __init__(self, table, ident, name, location, return_type, param_types, param_strings, body, pairs): - super(Func, self).__init__(table, ident, location, pairs) + super().__init__(table, ident, location, pairs) self.return_type = return_type self.param_types = param_types self.param_strings = param_strings diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index c71d7eac6b..5d315e98bf 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -68,7 +68,7 @@ python_class_map = { class StateMachine(Symbol): def __init__(self, symtab, ident, location, pairs, config_parameters): - super(StateMachine, self).__init__(symtab, ident, location, pairs) + super().__init__(symtab, ident, location, pairs) self.table = None # Data members in the State Machine that have been declared before diff --git a/src/mem/slicc/symbols/Symbol.py b/src/mem/slicc/symbols/Symbol.py index b394fda44a..268ec0420e 100644 --- a/src/mem/slicc/symbols/Symbol.py +++ b/src/mem/slicc/symbols/Symbol.py @@ -29,7 +29,7 @@ from slicc.util import PairContainer class Symbol(PairContainer): def __init__(self, symtab, ident, location, pairs=None): - super(Symbol, self).__init__() + super().__init__() from slicc.util import Location from slicc.symbols import SymbolTable @@ -56,7 +56,7 @@ class Symbol(PairContainer): if key in self.pairs: self.warning("Pair key '%s' re-defined. new: '%s' old: '%s'", key, value, self.pairs[key]) - super(Symbol, self).__setitem__(key, value) + super().__setitem__(key, value) @property def short(self): diff --git a/src/mem/slicc/symbols/Transition.py b/src/mem/slicc/symbols/Transition.py index 8c02094548..bfa721c120 100644 --- a/src/mem/slicc/symbols/Transition.py +++ b/src/mem/slicc/symbols/Transition.py @@ -32,7 +32,7 @@ class Transition(Symbol): def __init__(self, table, machine, state, event, nextState, actions, request_types, location): ident = "%s|%s" % (state, event) - super(Transition, self).__init__(table, ident, location) + super().__init__(table, ident, location) self.state = machine.states[state] self.event = machine.events[event] diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index 93eeaf7c3b..a87e6b51d0 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -46,8 +46,7 @@ from slicc.symbols.Var import Var class DataMember(Var): def __init__(self, symtab, ident, location, type, code, pairs, machine, init_code): - super(DataMember, self).__init__(symtab, ident, location, type, - code, pairs, machine) + super().__init__(symtab, ident, location, type, code, pairs, machine) self.init_code = init_code self.real_c_type = self.type.c_ident if "template" in pairs: @@ -55,13 +54,13 @@ class DataMember(Var): class Enumeration(PairContainer): def __init__(self, ident, pairs): - super(Enumeration, self).__init__(pairs) + super().__init__(pairs) self.ident = ident self.primary = False class Type(Symbol): def __init__(self, table, ident, location, pairs, machine=None): - super(Type, self).__init__(table, ident, location, pairs) + super().__init__(table, ident, location, pairs) self.c_ident = ident self.abstract_ident = "" if machine: diff --git a/src/mem/slicc/symbols/Var.py b/src/mem/slicc/symbols/Var.py index 2a4ef23db3..6d9a2cf9d8 100644 --- a/src/mem/slicc/symbols/Var.py +++ b/src/mem/slicc/symbols/Var.py @@ -30,7 +30,7 @@ from slicc.symbols.Symbol import Symbol class Var(Symbol): def __init__(self, symtab, ident, location, type, code, pairs, machine=None): - super(Var, self).__init__(symtab, ident, location, pairs) + super().__init__(symtab, ident, location, pairs) self.machine = machine self.type = type diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index 51555d057f..9bfac8f4f5 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -68,7 +68,7 @@ class AbstractBoard(System): memory: "AbstractMemory", cache_hierarchy: "AbstractCacheHierarchy", ) -> None: - super(AbstractBoard, self).__init__() + super().__init__() """ :param clk_freq: The clock frequency for this board. :param processor: The processor for this board. diff --git a/src/python/gem5/components/boards/simple_board.py b/src/python/gem5/components/boards/simple_board.py index 3242cf06e2..c01113252f 100644 --- a/src/python/gem5/components/boards/simple_board.py +++ b/src/python/gem5/components/boards/simple_board.py @@ -58,7 +58,7 @@ class SimpleBoard(AbstractBoard, SEBinaryWorkload): memory: AbstractMemorySystem, cache_hierarchy: AbstractCacheHierarchy, ) -> None: - super(SimpleBoard, self).__init__( + super().__init__( clk_freq=clk_freq, processor=processor, memory=memory, @@ -110,4 +110,4 @@ class SimpleBoard(AbstractBoard, SEBinaryWorkload): # The simple board just has one memory range that is the size of the # memory. self.mem_ranges = [AddrRange(memory.get_size())] - memory.set_memory_range(self.mem_ranges) \ No newline at end of file + memory.set_memory_range(self.mem_ranges) diff --git a/src/python/gem5/components/boards/test_board.py b/src/python/gem5/components/boards/test_board.py index 9010843fad..3d5b3040eb 100644 --- a/src/python/gem5/components/boards/test_board.py +++ b/src/python/gem5/components/boards/test_board.py @@ -56,7 +56,7 @@ class TestBoard(AbstractBoard): memory: AbstractMemorySystem, cache_hierarchy: AbstractCacheHierarchy, ): - super(TestBoard, self).__init__( + super().__init__( clk_freq=clk_freq, processor=processor, memory=memory, diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py index a673cbe83f..3b5effab28 100644 --- a/src/python/gem5/components/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -78,7 +78,7 @@ class X86Board(AbstractBoard, KernelDiskWorkload): memory: AbstractMemorySystem, cache_hierarchy: AbstractCacheHierarchy, ) -> None: - super(X86Board, self).__init__( + super().__init__( clk_freq=clk_freq, processor=processor, memory=memory, diff --git a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py index f71ea5d938..5f6096e8ff 100644 --- a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py @@ -35,7 +35,7 @@ class AbstractCacheHierarchy(SubSystem): __metaclass__ = ABCMeta def __init__(self): - super(AbstractCacheHierarchy, self).__init__() + super().__init__() """ A Cache Hierarchy incorporates any system components which manages diff --git a/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py index c492bfd438..3423c9ca9a 100644 --- a/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py @@ -39,7 +39,7 @@ class AbstractClassicCacheHierarchy(AbstractCacheHierarchy): """ def __init__(self): - super(AbstractClassicCacheHierarchy, self).__init__() + super().__init__() @overrides(AbstractCacheHierarchy) def is_ruby(self) -> bool: diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py index c80032b198..003a56b4fe 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py @@ -48,7 +48,7 @@ class L1DCache(Cache): writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): - super(L1DCache, self).__init__() + super().__init__() self.size = size self.assoc = assoc self.tag_latency = tag_latency diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py index 8e4ba0946f..a83df10312 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py @@ -48,7 +48,7 @@ class L1ICache(Cache): writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): - super(L1ICache, self).__init__() + super().__init__() self.size = size self.assoc = assoc self.tag_latency = tag_latency diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py index b32625527d..43c18718de 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py @@ -48,7 +48,7 @@ class L2Cache(Cache): writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): - super(L2Cache, self).__init__() + super().__init__() self.size = size self.assoc = assoc self.tag_latency = tag_latency diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py index 2048782d8b..7f65e73251 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py @@ -44,7 +44,7 @@ class MMUCache(Cache): tgts_per_mshr: int = 12, writeback_clean: bool = True, ): - super(MMUCache, self).__init__() + super().__init__() self.size = size self.assoc = assoc self.tag_latency = tag_latency diff --git a/src/python/gem5/components/cachehierarchies/classic/no_cache.py b/src/python/gem5/components/cachehierarchies/classic/no_cache.py index 11f6420bee..e57e7134ae 100644 --- a/src/python/gem5/components/cachehierarchies/classic/no_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py @@ -82,7 +82,7 @@ class NoCache(AbstractClassicCacheHierarchy): :type membus: BaseXBar """ - super(NoCache, self).__init__() + super().__init__() self.membus = membus @overrides(AbstractClassicCacheHierarchy) diff --git a/src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py index 2648a01bc2..3528b74495 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py @@ -35,7 +35,7 @@ class AbstractRubyCacheHierarchy(AbstractCacheHierarchy): """ def __init__(self): - super(AbstractRubyCacheHierarchy, self).__init__() + super().__init__() @overrides(AbstractCacheHierarchy) def is_ruby(self) -> bool: diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py index ae3a1b0c77..e39a38ccc9 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py @@ -40,7 +40,7 @@ class AbstractDirectory(Directory_Controller): def __init__(self, network, cache_line_size): """ """ - super(AbstractDirectory, self).__init__() + super().__init__() self.version = self.versionCount() self._cache_line_size = cache_line_size self.connectQueues(network) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py index 122ba08b40..8d36736017 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py @@ -39,7 +39,7 @@ class AbstractDMAController(DMA_Controller): return cls._version - 1 def __init__(self, network, cache_line_size): - super(AbstractDMAController, self).__init__() + super().__init__() self.version = self.versionCount() self._cache_line_size = cache_line_size self.connectQueues(network) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py index ea1995e6b5..7f014dc382 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py @@ -47,7 +47,7 @@ class AbstractL1Cache(L1Cache_Controller): # However, we need some way to set the index bits def __init__(self, network, cache_line_size): """ """ - super(AbstractL1Cache, self).__init__() + super().__init__() self.version = self.versionCount() self._cache_line_size = cache_line_size diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py index aab6799e5b..88b41228c4 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py @@ -39,7 +39,7 @@ class AbstractL2Cache(L2Cache_Controller): return cls._version - 1 def __init__(self, network, cache_line_size): - super(AbstractL2Cache, self).__init__() + super().__init__() self.version = self.versionCount() self._cache_line_size = cache_line_size diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py index cb10fbc7bf..990b0bf66a 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py @@ -36,7 +36,7 @@ from m5.objects import ( class Directory(AbstractDirectory): def __init__(self, network, cache_line_size, mem_range, port): - super(Directory, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) self.addr_ranges = [mem_range] self.directory = RubyDirectoryMemory() # Connect this directory to the memory side. diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py index 0f8a7b03bd..ab76d4cb5e 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py @@ -32,7 +32,7 @@ from m5.objects import MessageBuffer class DMAController(AbstractDMAController): def __init__(self, network, cache_line_size): - super(DMAController, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) @overrides(AbstractDMAController) def connectQueues(self, network): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py index fce222b927..7f6269d7e0 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py @@ -56,7 +56,7 @@ class L1Cache(AbstractL1Cache): """Creating L1 cache controller. Consist of both instruction and data cache. """ - super(L1Cache, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) # This is the cache memory object that stores the cache data and tags self.L1Icache = RubyCache( diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py index 323ea523a6..56cb5b2ec1 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py @@ -36,7 +36,7 @@ class L2Cache(AbstractL2Cache): def __init__( self, l2_size, l2_assoc, network, num_l2Caches, cache_line_size ): - super(L2Cache, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) # This is the cache memory object that stores the cache data and tags self.L2cache = RubyCache( diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py index 5cb819b567..23216ec887 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py @@ -41,7 +41,7 @@ class Directory(AbstractDirectory): def __init__(self, network, cache_line_size, mem_range, port): - super(Directory, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) self.addr_ranges = [mem_range] self.directory = RubyDirectoryMemory() # Connect this directory to the memory side. diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py index 14b89253eb..fb6895f4f8 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py @@ -37,7 +37,7 @@ class DMAController(AbstractDMAController): class DMAController(AbstractDMAController): def __init__(self, network, cache_line_size): - super(DMAController, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) @overrides(AbstractDMAController) def connectQueues(self, network): diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py index ffd5425636..62adfb7917 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py @@ -47,7 +47,7 @@ class L1Cache(AbstractL1Cache): target_isa: ISA, clk_domain: ClockDomain, ): - super(L1Cache, self).__init__(network, cache_line_size) + super().__init__(network, cache_line_size) self.cacheMemory = RubyCache( size=size, assoc=assoc, start_index_bit=self.getBlockSizeBits() diff --git a/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py b/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py index 4b99879209..649f027d72 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py +++ b/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py @@ -31,7 +31,7 @@ class SimplePt2Pt(SimpleNetwork): """A simple point-to-point network. This doesn't not use garnet.""" def __init__(self, ruby_system): - super(SimplePt2Pt, self).__init__() + super().__init__() self.netifs = [] # TODO: These should be in a base class diff --git a/src/python/gem5/components/memory/abstract_memory_system.py b/src/python/gem5/components/memory/abstract_memory_system.py index 22a8c51dbe..27bc152304 100644 --- a/src/python/gem5/components/memory/abstract_memory_system.py +++ b/src/python/gem5/components/memory/abstract_memory_system.py @@ -37,7 +37,7 @@ class AbstractMemorySystem(SubSystem): __metaclass__ = ABCMeta def __init__(self) -> None: - super(AbstractMemorySystem, self).__init__() + super().__init__() @abstractmethod def incorporate_memory(self, board: AbstractBoard) -> None: diff --git a/src/python/gem5/components/memory/dramsim_3.py b/src/python/gem5/components/memory/dramsim_3.py index 5e7ec12c65..b7eba919fc 100644 --- a/src/python/gem5/components/memory/dramsim_3.py +++ b/src/python/gem5/components/memory/dramsim_3.py @@ -78,7 +78,7 @@ class DRAMSim3MemCtrl(DRAMsim3): :param mem_name: The name of the type of memory to be configured. :param num_chnls: The number of channels. """ - super(DRAMSim3MemCtrl, self).__init__() + super().__init__() ini_path, outdir = config_ds3(mem_name, num_chnls) self.configFile = ini_path self.filePath = outdir @@ -94,7 +94,7 @@ class SingleChannel(AbstractMemorySystem): :param mem_name: The name of the type of memory to be configured. :param num_chnls: The number of channels. """ - super(SingleChannel, self).__init__() + super().__init__() self.mem_ctrl = DRAMSim3MemCtrl(mem_type, 1) self._size = toMemorySize(size) if not size: diff --git a/src/python/gem5/components/processors/abstract_core.py b/src/python/gem5/components/processors/abstract_core.py index 0a58fdf9c9..a16196fb0f 100644 --- a/src/python/gem5/components/processors/abstract_core.py +++ b/src/python/gem5/components/processors/abstract_core.py @@ -36,7 +36,7 @@ class AbstractCore(SubSystem): __metaclass__ = ABCMeta def __init__(self, cpu_type: CPUTypes): - super(AbstractCore, self).__init__() + super().__init__() if cpu_type == CPUTypes.KVM: requires(kvm_required=True) self._cpu_type = cpu_type diff --git a/src/python/gem5/components/processors/abstract_generator_core.py b/src/python/gem5/components/processors/abstract_generator_core.py index 8bde5a5284..5caed383cd 100644 --- a/src/python/gem5/components/processors/abstract_generator_core.py +++ b/src/python/gem5/components/processors/abstract_generator_core.py @@ -51,7 +51,7 @@ class AbstractGeneratorCore(AbstractCore): """ # TODO: Remove the CPU Type parameter. This not needed. # Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031 - super(AbstractGeneratorCore, self).__init__(CPUTypes.TIMING) + super().__init__(CPUTypes.TIMING) self.port_end = PortTerminator() @overrides(AbstractCore) diff --git a/src/python/gem5/components/processors/abstract_processor.py b/src/python/gem5/components/processors/abstract_processor.py index 42ee194109..07ddcdbb41 100644 --- a/src/python/gem5/components/processors/abstract_processor.py +++ b/src/python/gem5/components/processors/abstract_processor.py @@ -38,7 +38,7 @@ class AbstractProcessor(SubSystem): __metaclass__ = ABCMeta def __init__(self, cores: List[AbstractCore]) -> None: - super(AbstractProcessor, self).__init__() + super().__init__() assert len(cores) > 0 self.cores = cores diff --git a/src/python/gem5/components/processors/complex_generator.py b/src/python/gem5/components/processors/complex_generator.py index 418375c1a2..2101e23ee3 100644 --- a/src/python/gem5/components/processors/complex_generator.py +++ b/src/python/gem5/components/processors/complex_generator.py @@ -34,7 +34,7 @@ from ..boards.abstract_board import AbstractBoard class ComplexGenerator(AbstractProcessor): def __init__(self, num_cores: int = 1) -> None: - super(ComplexGenerator, self).__init__( + super().__init__( cores=[ComplexGeneratorCore() for i in range(num_cores)] ) """The complex generator diff --git a/src/python/gem5/components/processors/complex_generator_core.py b/src/python/gem5/components/processors/complex_generator_core.py index 190631f7d4..583b318341 100644 --- a/src/python/gem5/components/processors/complex_generator_core.py +++ b/src/python/gem5/components/processors/complex_generator_core.py @@ -82,7 +82,7 @@ class ComplexGeneratorCore(AbstractGeneratorCore): to create more complex traffics that consist of linear and random traffic in different phases. """ - super(ComplexGeneratorCore, self).__init__() + super().__init__() self.generator = PyTrafficGen() self._traffic_params = [] self._traffic = [] diff --git a/src/python/gem5/components/processors/gups_generator.py b/src/python/gem5/components/processors/gups_generator.py index 11b2e7149d..191be6b725 100644 --- a/src/python/gem5/components/processors/gups_generator.py +++ b/src/python/gem5/components/processors/gups_generator.py @@ -57,7 +57,7 @@ class GUPSGenerator(AbstractProcessor): simulation. Pass zero to run the benchmark to completion (The amount of time it takes to simulate depends on ) """ - super(GUPSGenerator, self).__init__( + super().__init__( cores=[ GUPSGeneratorCore( start_addr=start_addr, diff --git a/src/python/gem5/components/processors/gups_generator_core.py b/src/python/gem5/components/processors/gups_generator_core.py index ed8493bd0c..8ce921ee04 100644 --- a/src/python/gem5/components/processors/gups_generator_core.py +++ b/src/python/gem5/components/processors/gups_generator_core.py @@ -40,7 +40,7 @@ class GUPSGeneratorCore(AbstractGeneratorCore): """ Create a GUPSGeneratorCore as the main generator. """ - super(GUPSGeneratorCore, self).__init__() + super().__init__() self.generator = GUPSGen( start_addr=start_addr, mem_size=mem_size, update_limit=update_limit ) diff --git a/src/python/gem5/components/processors/gups_generator_ep.py b/src/python/gem5/components/processors/gups_generator_ep.py index 5ab0682f8d..203a88c7f7 100644 --- a/src/python/gem5/components/processors/gups_generator_ep.py +++ b/src/python/gem5/components/processors/gups_generator_ep.py @@ -58,7 +58,7 @@ class GUPSGeneratorEP(AbstractProcessor): simulation. Pass zero to run the benchmark to completion (The amount of time it takes to simulate depends on ) """ - super(GUPSGeneratorEP, self).__init__( + super().__init__( cores=self._create_cores( num_cores=num_cores, start_addr=start_addr, diff --git a/src/python/gem5/components/processors/gups_generator_par.py b/src/python/gem5/components/processors/gups_generator_par.py index 942100dd7c..aad360abdc 100644 --- a/src/python/gem5/components/processors/gups_generator_par.py +++ b/src/python/gem5/components/processors/gups_generator_par.py @@ -57,7 +57,7 @@ class GUPSGeneratorPAR(AbstractProcessor): simulation. Pass zero to run the benchmark to completion (The amount of time it takes to simulate depends on ) """ - super(GUPSGeneratorPAR, self).__init__( + super().__init__( cores=self._create_cores( num_cores=num_cores, start_addr=start_addr, diff --git a/src/python/gem5/components/processors/linear_generator.py b/src/python/gem5/components/processors/linear_generator.py index d220450cbe..7bdc5ed1af 100644 --- a/src/python/gem5/components/processors/linear_generator.py +++ b/src/python/gem5/components/processors/linear_generator.py @@ -46,7 +46,7 @@ class LinearGenerator(AbstractProcessor): rd_perc: int = 100, data_limit: int = 0, ) -> None: - super(LinearGenerator, self).__init__( + super().__init__( cores=self._create_cores( num_cores=num_cores, duration=duration, diff --git a/src/python/gem5/components/processors/linear_generator_core.py b/src/python/gem5/components/processors/linear_generator_core.py index 8769c77908..e6bf441015 100644 --- a/src/python/gem5/components/processors/linear_generator_core.py +++ b/src/python/gem5/components/processors/linear_generator_core.py @@ -47,7 +47,7 @@ class LinearGeneratorCore(AbstractGeneratorCore): rd_perc: int, data_limit: int, ) -> None: - super(LinearGeneratorCore, self).__init__() + super().__init__() """ The linear generator core interface. This class defines the interface for a generator core that will create diff --git a/src/python/gem5/components/processors/random_generator.py b/src/python/gem5/components/processors/random_generator.py index df70f2c7f1..17c3ce3c17 100644 --- a/src/python/gem5/components/processors/random_generator.py +++ b/src/python/gem5/components/processors/random_generator.py @@ -46,7 +46,7 @@ class RandomGenerator(AbstractProcessor): rd_perc: int = 100, data_limit: int = 0, ) -> None: - super(RandomGenerator, self).__init__( + super().__init__( cores=self._create_cores( num_cores=num_cores, duration=duration, diff --git a/src/python/gem5/components/processors/random_generator_core.py b/src/python/gem5/components/processors/random_generator_core.py index e5865fc271..219040c864 100644 --- a/src/python/gem5/components/processors/random_generator_core.py +++ b/src/python/gem5/components/processors/random_generator_core.py @@ -47,7 +47,7 @@ class RandomGeneratorCore(AbstractGeneratorCore): rd_perc: int, data_limit: int, ) -> None: - super(RandomGeneratorCore, self).__init__() + super().__init__() """ The random generator core interface. This class defines the interface for a generator core that will create diff --git a/src/python/gem5/components/processors/simple_core.py b/src/python/gem5/components/processors/simple_core.py index 6c0d6a5ce4..89c78d0b64 100644 --- a/src/python/gem5/components/processors/simple_core.py +++ b/src/python/gem5/components/processors/simple_core.py @@ -45,7 +45,7 @@ from m5.objects import ( class SimpleCore(AbstractCore): def __init__(self, cpu_type: CPUTypes, core_id: int): - super(SimpleCore, self).__init__(cpu_type=cpu_type) + super().__init__(cpu_type=cpu_type) if cpu_type == CPUTypes.ATOMIC: self.core = AtomicSimpleCPU(cpu_id=core_id) diff --git a/src/python/gem5/components/processors/simple_processor.py b/src/python/gem5/components/processors/simple_processor.py index 4f602edcb0..8f32cf1683 100644 --- a/src/python/gem5/components/processors/simple_processor.py +++ b/src/python/gem5/components/processors/simple_processor.py @@ -42,7 +42,7 @@ class SimpleProcessor(AbstractProcessor): """ def __init__(self, cpu_type: CPUTypes, num_cores: int) -> None: - super(SimpleProcessor, self).__init__( + super().__init__( cores=self._create_cores( cpu_type=cpu_type, num_cores=num_cores, diff --git a/src/python/gem5/components/processors/simple_switchable_processor.py b/src/python/gem5/components/processors/simple_switchable_processor.py index 4cc4cfb01d..f13bb221e1 100644 --- a/src/python/gem5/components/processors/simple_switchable_processor.py +++ b/src/python/gem5/components/processors/simple_switchable_processor.py @@ -75,7 +75,7 @@ class SimpleSwitchableProcessor(SwitchableProcessor): ], } - super(SimpleSwitchableProcessor, self).__init__( + super().__init__( switchable_cores=switchable_cores, starting_cores=self._start_key, ) diff --git a/src/python/gem5/components/processors/switchable_processor.py b/src/python/gem5/components/processors/switchable_processor.py index dea281540a..4be3c74e71 100644 --- a/src/python/gem5/components/processors/switchable_processor.py +++ b/src/python/gem5/components/processors/switchable_processor.py @@ -82,7 +82,7 @@ class SwitchableProcessor(AbstractProcessor): self.kvm_vm = KvmVM() - super(SwitchableProcessor, self).__init__(cores=all_cores) + super().__init__(cores=all_cores) @overrides(AbstractProcessor) def incorporate_processor(self, board: AbstractBoard) -> None: diff --git a/src/python/gem5/resources/resource.py b/src/python/gem5/resources/resource.py index 0db8dfbb91..32031911d9 100644 --- a/src/python/gem5/resources/resource.py +++ b/src/python/gem5/resources/resource.py @@ -127,7 +127,7 @@ class Resource(AbstractResource): to_path = os.path.join(resource_directory, resource_name) - super(Resource, self).__init__( + super().__init__( local_path=to_path, metadata=get_resources_json_obj(resource_name)) get_resource( diff --git a/src/python/importer.py b/src/python/importer.py index 7fa1641ec6..baeae2113c 100644 --- a/src/python/importer.py +++ b/src/python/importer.py @@ -31,7 +31,7 @@ import os class ByteCodeLoader(importlib.abc.Loader): def __init__(self, code): - super(ByteCodeLoader, self).__init__() + super().__init__() self.code = code def exec_module(self, module): diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 25bb003e39..b07d90f7b8 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -450,7 +450,7 @@ class MetaSimObject(type): if 'cxx_template_params' not in value_dict: value_dict['cxx_template_params'] = [] cls_dict['_value_dict'] = value_dict - cls = super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict) + cls = super().__new__(mcls, name, bases, cls_dict) if 'type' in value_dict: allClasses[name] = cls return cls @@ -459,7 +459,7 @@ class MetaSimObject(type): def __init__(cls, name, bases, dict): # calls type.__init__()... I think that's a no-op, but leave # it here just in case it's not. - super(MetaSimObject, cls).__init__(name, bases, dict) + super().__init__(name, bases, dict) # initialize required attributes @@ -1147,7 +1147,7 @@ class ParamInfo(object): class SimObjectCliWrapperException(Exception): def __init__(self, message): - super(Exception, self).__init__(message) + super().__init__(message) class SimObjectCliWrapper(object): """ diff --git a/src/python/m5/event.py b/src/python/m5/event.py index f0230cffb2..67c9fc627c 100644 --- a/src/python/m5/event.py +++ b/src/python/m5/event.py @@ -51,7 +51,7 @@ class EventWrapper(Event): """Helper class to wrap callable objects in an Event base class""" def __init__(self, func, **kwargs): - super(EventWrapper, self).__init__(**kwargs) + super().__init__(**kwargs) if not callable(func): raise RuntimeError("Can't wrap '%s', object is not callable" % \ @@ -68,7 +68,7 @@ class EventWrapper(Event): class ProgressEvent(Event): def __init__(self, eventq, period): - super(ProgressEvent, self).__init__() + super().__init__() self.period = int(period) self.eventq = eventq self.eventq.schedule(self, m5.curTick() + self.period) diff --git a/src/python/m5/ext/pystats/group.py b/src/python/m5/ext/pystats/group.py index cc9fcd317e..366061fd0e 100644 --- a/src/python/m5/ext/pystats/group.py +++ b/src/python/m5/ext/pystats/group.py @@ -133,8 +133,4 @@ class Vector(Group): https://gem5.atlassian.net/browse/GEM5-867. """ def __init__(self, scalar_map: Mapping[str,Scalar]): - super(Vector, self).__init__( - type="Vector", - time_conversion=None, - **scalar_map, - ) + super().__init__(type="Vector", time_conversion=None, **scalar_map) diff --git a/src/python/m5/ext/pystats/jsonloader.py b/src/python/m5/ext/pystats/jsonloader.py index 35873e4f7b..ffe87f748a 100644 --- a/src/python/m5/ext/pystats/jsonloader.py +++ b/src/python/m5/ext/pystats/jsonloader.py @@ -47,9 +47,7 @@ class JsonLoader(json.JSONDecoder): """ def __init__(self): - super(JsonLoader, self).__init__(self, - object_hook=self.__json_to_simstat - ) + super().__init__(self, object_hook=self.__json_to_simstat) def __json_to_simstat(self, d: dict) -> Union[SimStat,Statistic,Group]: if 'type' in d: diff --git a/src/python/m5/ext/pystats/statistic.py b/src/python/m5/ext/pystats/statistic.py index 15490a01ad..d078a164e2 100644 --- a/src/python/m5/ext/pystats/statistic.py +++ b/src/python/m5/ext/pystats/statistic.py @@ -62,13 +62,8 @@ class Scalar(Statistic): unit: Optional[str] = None, description: Optional[str] = None, datatype: Optional[StorageType] = None): - super(Scalar, self).__init__( - value=value, - type="Scalar", - unit=unit, - description=description, - datatype=datatype, - ) + super().__init__(value=value, type="Scalar", unit=unit, + description=description, datatype=datatype) class BaseScalarVector(Statistic): """ @@ -81,13 +76,8 @@ class BaseScalarVector(Statistic): unit: Optional[str] = None, description: Optional[str] = None, datatype: Optional[StorageType] = None): - super(BaseScalarVector, self).__init__( - value=list(value), - type=type, - unit=unit, - description=description, - datatype=datatype, - ) + super().__init__(value=list(value), type=type, unit=unit, + description=description, datatype=datatype) def mean(self) -> float: """ @@ -150,13 +140,8 @@ class Distribution(BaseScalarVector): unit: Optional[str] = None, description: Optional[str] = None, datatype: Optional[StorageType] = None): - super(Distribution, self).__init__( - value=value, - type="Distribution", - unit=unit, - description=description, - datatype=datatype, - ) + super().__init__(value=value, type="Distribution", unit=unit, + description=description, datatype=datatype) self.min = min self.max = max @@ -190,13 +175,8 @@ class Accumulator(BaseScalarVector): unit: Optional[str] = None, description: Optional[str] = None, datatype: Optional[StorageType] = None): - super(Accumulator, self).__init__( - value=value, - type="Accumulator", - unit=unit, - description=description, - datatype=datatype, - ) + super().__init__(value=value, type="Accumulator", unit=unit, + description=description, datatype=datatype) self._count = count self.min = min diff --git a/src/python/m5/options.py b/src/python/m5/options.py index a580160102..56c1a29a11 100644 --- a/src/python/m5/options.py +++ b/src/python/m5/options.py @@ -106,23 +106,23 @@ class OptionParser(dict): def __getattr__(self, attr): if attr.startswith('_'): - return super(OptionParser, self).__getattribute__(attr) + return super().__getattribute__(attr) if attr in self: return self[attr] - return super(OptionParser, self).__getattribute__(attr) + return super().__getattribute__(attr) def __setattr__(self, attr, value): if attr.startswith('_'): - super(OptionParser, self).__setattr__(attr, value) + super().__setattr__(attr, value) elif attr in self._allopts: defaults = { attr : value } self.set_defaults(**defaults) if attr in self: self[attr] = value else: - super(OptionParser, self).__setattr__(attr, value) + super().__setattr__(attr, value) def parse_args(self): opts,args = self._optparse.parse_args() diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 49f5a56abc..39137c5496 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -81,7 +81,7 @@ allParams = {} class MetaParamValue(type): def __new__(mcls, name, bases, dct): - cls = super(MetaParamValue, mcls).__new__(mcls, name, bases, dct) + cls = super().__new__(mcls, name, bases, dct) if name in allParams: warn("%s already exists in allParams. This may be caused by the " \ "Python 2.7 compatibility layer." % (name, )) @@ -301,7 +301,7 @@ class SimObjectVector(VectorParamValue): warn("SimObject %s already has a parent" % value.get_name() +\ " that is being overwritten by a SimObjectVector") value.set_parent(val.get_parent(), val._name) - super(SimObjectVector, self).__setitem__(key, value) + super().__setitem__(key, value) # Enumerate the params of each member of the SimObject vector. Creates # strings that will allow indexing into the vector by the python code and @@ -347,7 +347,7 @@ class VectorParamDesc(ParamDesc): # how to set this vector parameter in the absence of a default # value. def example_str(self): - s = super(VectorParamDesc, self).example_str() + s = super().example_str() help_str = "[" + s + "," + s + ", ...]" return help_str @@ -548,7 +548,7 @@ class NumericParamValue(ParamValue): # Metaclass for bounds-checked integer parameters. See CheckedInt. class CheckedIntType(MetaParamValue): def __init__(cls, name, bases, dict): - super(CheckedIntType, cls).__init__(name, bases, dict) + super().__init__(name, bases, dict) # CheckedInt is an abstract base class, so we actually don't # want to do any processing on it... the rest of this code is @@ -1094,7 +1094,7 @@ class IpNetmask(IpAddress): return value def __str__(self): - return "%s/%d" % (super(IpNetmask, self).__str__(), self.netmask) + return "%s/%d" % (super().__str__(), self.netmask) def __eq__(self, other): if isinstance(other, IpNetmask): @@ -1168,7 +1168,7 @@ class IpWithPort(IpAddress): return value def __str__(self): - return "%s:%d" % (super(IpWithPort, self).__str__(), self.port) + return "%s:%d" % (super().__str__(), self.port) def __eq__(self, other): if isinstance(other, IpWithPort): @@ -1287,7 +1287,7 @@ allEnums = {} class MetaEnum(MetaParamValue): def __new__(mcls, name, bases, dict): - cls = super(MetaEnum, mcls).__new__(mcls, name, bases, dict) + cls = super().__new__(mcls, name, bases, dict) allEnums[name] = cls return cls @@ -1316,7 +1316,7 @@ class MetaEnum(MetaParamValue): else: cls.cxx_type = 'enums::%s' % name - super(MetaEnum, cls).__init__(name, bases, init_dict) + super().__init__(name, bases, init_dict) # Generate C++ class declaration for this enum type. # Note that we wrap the enum in a class/struct to act as a namespace, @@ -1694,33 +1694,33 @@ class Voltage(Float): def __new__(cls, value): value = convert.toVoltage(value) - return super(cls, Voltage).__new__(cls, value) + return super().__new__(cls, value) def __init__(self, value): value = convert.toVoltage(value) - super(Voltage, self).__init__(value) + super().__init__(value) class Current(Float): ex_str = "1mA" def __new__(cls, value): value = convert.toCurrent(value) - return super(cls, Current).__new__(cls, value) + return super().__new__(cls, value) def __init__(self, value): value = convert.toCurrent(value) - super(Current, self).__init__(value) + super().__init__(value) class Energy(Float): ex_str = "1pJ" def __new__(cls, value): value = convert.toEnergy(value) - return super(cls, Energy).__new__(cls, value) + return super().__new__(cls, value) def __init__(self, value): value = convert.toEnergy(value) - super(Energy, self).__init__(value) + super().__init__(value) class Temperature(ParamValue): cxx_type = 'Temperature' @@ -1770,7 +1770,7 @@ class NetworkBandwidth(float,ParamValue): def __new__(cls, value): # convert to bits per second val = convert.toNetworkBandwidth(value) - return super(cls, NetworkBandwidth).__new__(cls, val) + return super().__new__(cls, val) def __str__(self): return str(self.val) @@ -1809,7 +1809,7 @@ class MemoryBandwidth(float,ParamValue): def __new__(cls, value): # convert to bytes per second val = convert.toMemoryBandwidth(value) - return super(cls, MemoryBandwidth).__new__(cls, val) + return super().__new__(cls, val) def __call__(self, value): val = convert.toMemoryBandwidth(value) @@ -2180,13 +2180,12 @@ Port.compat('GEM5 REQUESTOR', 'GEM5 RESPONDER') class RequestPort(Port): # RequestPort("description") def __init__(self, desc): - super(RequestPort, self).__init__( - 'GEM5 REQUESTOR', desc, is_source=True) + super().__init__('GEM5 REQUESTOR', desc, is_source=True) class ResponsePort(Port): # ResponsePort("description") def __init__(self, desc): - super(ResponsePort, self).__init__('GEM5 RESPONDER', desc) + super().__init__('GEM5 RESPONDER', desc) # VectorPort description object. Like Port, but represents a vector # of connections (e.g., as on a XBar). @@ -2197,13 +2196,12 @@ class VectorPort(Port): class VectorRequestPort(VectorPort): # VectorRequestPort("description") def __init__(self, desc): - super(VectorRequestPort, self).__init__( - 'GEM5 REQUESTOR', desc, is_source=True) + super().__init__('GEM5 REQUESTOR', desc, is_source=True) class VectorResponsePort(VectorPort): # VectorResponsePort("description") def __init__(self, desc): - super(VectorResponsePort, self).__init__('GEM5 RESPONDER', desc) + super().__init__('GEM5 RESPONDER', desc) # Old names, maintained for compatibility. MasterPort = RequestPort diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py index 2de0ee73fd..b4e9bbe47c 100644 --- a/src/python/m5/proxy.py +++ b/src/python/m5/proxy.py @@ -63,7 +63,7 @@ class BaseProxy(object): if not attr.startswith('_'): raise AttributeError( "cannot set attribute '%s' on proxy object" % attr) - super(BaseProxy, self).__setattr__(attr, value) + super().__setattr__(attr, value) def _gen_op(operation): def op(self, operand): @@ -163,14 +163,14 @@ class BaseProxy(object): class AttrProxy(BaseProxy): def __init__(self, search_self, search_up, attr): - super(AttrProxy, self).__init__(search_self, search_up) + super().__init__(search_self, search_up) self._attr = attr self._modifiers = [] def __getattr__(self, attr): # python uses __bases__ internally for inheritance if attr.startswith('_'): - return super(AttrProxy, self).__getattr__(self, attr) + return super().__getattr__(self, attr) if hasattr(self, '_pdesc'): raise AttributeError("Attribute reference on bound proxy " f"({self}.{attr})") diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py index 71621e7fb6..a63fa810d5 100644 --- a/src/python/m5/util/__init__.py +++ b/src/python/m5/util/__init__.py @@ -76,7 +76,7 @@ class Singleton(type): if hasattr(cls, '_instance'): return cls._instance - cls._instance = super(Singleton, cls).__call__(*args, **kwargs) + cls._instance = super().__call__(*args, **kwargs) return cls._instance def addToPath(path): diff --git a/src/python/m5/util/attrdict.py b/src/python/m5/util/attrdict.py index a072783dc1..d953e8c666 100644 --- a/src/python/m5/util/attrdict.py +++ b/src/python/m5/util/attrdict.py @@ -31,17 +31,17 @@ class attrdict(dict): def __getattr__(self, attr): if attr in self: return self.__getitem__(attr) - return super(attrdict, self).__getattribute__(attr) + return super().__getattribute__(attr) def __setattr__(self, attr, value): if attr in dir(self) or attr.startswith('_'): - return super(attrdict, self).__setattr__(attr, value) + return super().__setattr__(attr, value) return self.__setitem__(attr, value) def __delattr__(self, attr): if attr in self: return self.__delitem__(attr) - return super(attrdict, self).__delattr__(attr) + return super().__delattr__(attr) def __getstate__(self): return dict(self) @@ -54,7 +54,7 @@ class multiattrdict(attrdict): nested dictionaries.""" def __getattr__(self, attr): try: - return super(multiattrdict, self).__getattr__(attr) + return super().__getattr__(attr) except AttributeError: if attr.startswith('_'): raise @@ -67,7 +67,7 @@ class optiondict(attrdict): """Modify attrdict so that a missing attribute just returns None""" def __getattr__(self, attr): try: - return super(optiondict, self).__getattr__(attr) + return super().__getattr__(attr) except AttributeError: return None diff --git a/src/python/m5/util/fdthelper.py b/src/python/m5/util/fdthelper.py index d9dec11962..8c90b1aa44 100644 --- a/src/python/m5/util/fdthelper.py +++ b/src/python/m5/util/fdthelper.py @@ -53,7 +53,7 @@ class FdtPropertyWords(pyfdt.FdtPropertyWords): # Make sure all values are ints (use automatic base detection if the # type is str) words = [int(w, base=0) if type(w) == str else int(w) for w in words] - super(FdtPropertyWords, self).__init__(name, words) + super().__init__(name, words) class FdtPropertyStrings(pyfdt.FdtPropertyStrings): """Create a property with string values.""" @@ -62,7 +62,7 @@ class FdtPropertyStrings(pyfdt.FdtPropertyStrings): if type(strings) == str: strings = [strings] strings = [str(string) for string in strings] # Make all values strings - super(FdtPropertyStrings, self).__init__(name, strings) + super().__init__(name, strings) class FdtPropertyBytes(pyfdt.FdtPropertyBytes): """Create a property with integer (8-bit signed) values.""" @@ -74,7 +74,7 @@ class FdtPropertyBytes(pyfdt.FdtPropertyBytes): # type is str) values = [int(v, base=0) if isinstance(v, str) else int(v) for v in values] - super(FdtPropertyBytes, self).__init__(name, values) + super().__init__(name, values) class FdtState(object): """Class for maintaining state while recursively generating a flattened @@ -172,7 +172,7 @@ class FdtNode(pyfdt.FdtNode): def __init__(self, name, obj=None): """Create a new node and immediately set the phandle property, if obj is supplied""" - super(FdtNode, self).__init__(name) + super().__init__(name) if obj != None: self.appendPhandle(obj) @@ -198,7 +198,7 @@ class FdtNode(pyfdt.FdtNode): item.merge(subnode) subnode = item - super(FdtNode, self).append(subnode) + super().append(subnode) def appendList(self, subnode_list): """Append all properties/nodes in the iterable.""" @@ -245,7 +245,7 @@ class Fdt(pyfdt.Fdt): def add_rootnode(self, rootnode, prenops=None, postnops=None): """First sort the device tree, so that properties are before nodes.""" rootnode = self.sortNodes(rootnode) - super(Fdt, self).add_rootnode(rootnode, prenops, postnops) + super().add_rootnode(rootnode, prenops, postnops) def writeDtbFile(self, filename): """Convert the device tree to DTB and write to a file.""" diff --git a/src/sim/Workload.py b/src/sim/Workload.py index 62aa04783a..74d2306122 100644 --- a/src/sim/Workload.py +++ b/src/sim/Workload.py @@ -59,7 +59,7 @@ class KernelWorkload(Workload): class SEWorkloadMeta(type(Workload)): all_se_workload_classes = [] def __new__(mcls, name, bases, dct): - cls = super(SEWorkloadMeta, mcls).__new__(mcls, name, bases, dct) + cls = super().__new__(mcls, name, bases, dct) SEWorkloadMeta.all_se_workload_classes.append(cls) return cls diff --git a/src/systemc/Tlm.py b/src/systemc/Tlm.py index 16f0b000c5..4ca6f72ba9 100644 --- a/src/systemc/Tlm.py +++ b/src/systemc/Tlm.py @@ -37,7 +37,7 @@ class TlmTargetSocket(Port): peer_role = TLM_INITIATOR_ROLE(width) Port.compat(my_role, peer_role) - super(TlmTargetSocket, self).__init__(my_role, desc) + super().__init__(my_role, desc) class VectorTlmTargetSocket(VectorPort): def __init__(self, width, desc): @@ -45,7 +45,7 @@ class VectorTlmTargetSocket(VectorPort): peer_role = TLM_INITIATOR_ROLE(width) Port.compat(my_role, peer_role) - super(VectorTlmTargetSocket, self).__init__(my_role, desc) + super().__init__(my_role, desc) class TlmInitiatorSocket(Port): def __init__(self, width, desc): @@ -53,7 +53,7 @@ class TlmInitiatorSocket(Port): peer_role = TLM_TARGET_ROLE(width) Port.compat(my_role, peer_role) - super(TlmInitiatorSocket, self).__init__(my_role, desc, is_source=True) + super().__init__(my_role, desc, is_source=True) class VectorTlmInitiatorSocket(VectorPort): def __init__(self, width, desc): @@ -61,5 +61,4 @@ class VectorTlmInitiatorSocket(VectorPort): peer_role = TLM_TARGET_ROLE(width) Port.compat(my_role, peer_role) - super(VectorTlmInitiatorSocket, self).__init__( - my_role, desc, is_source=True) + super().__init__(my_role, desc, is_source=True) diff --git a/src/systemc/tests/SConscript b/src/systemc/tests/SConscript index de330cbee1..7d544f2dd9 100644 --- a/src/systemc/tests/SConscript +++ b/src/systemc/tests/SConscript @@ -63,7 +63,7 @@ if env['USE_SYSTEMC'] and GetOption('with_systemc_tests'): test_dir = Dir('.') class SystemCTestBin(Executable): def __init__(self, test): - super(SystemCTestBin, self).__init__(test.target, *test.sources) + super().__init__(test.target, *test.sources) self.reldir = test.reldir self.test_deps = test.deps @@ -82,7 +82,7 @@ if env['USE_SYSTEMC'] and GetOption('with_systemc_tests'): sl_dir, sl_base = os.path.split(shared_lib_path) env.Append(LIBPATH=[sl_dir], LIBS=[sl_base]) - super(SystemCTestBin, cls).declare_all(env) + super().declare_all(env) def declare(self, env): env = env.Clone() @@ -97,7 +97,7 @@ if env['USE_SYSTEMC'] and GetOption('with_systemc_tests'): env.Append(LINKFLAGS=Split('-z origin')) env.Append(RPATH=[ env.Literal(os.path.join('\\$$ORIGIN', relpath))]) - test_bin = super(SystemCTestBin, self).declare(env, objs) + test_bin = super().declare(env, objs) test_dir = self.dir.Dir(self.reldir) for dep in self.test_deps: env.Depends(test_bin, test_dir.File(dep)) diff --git a/src/systemc/tests/verify.py b/src/systemc/tests/verify.py index 076d1d51cb..54b463380d 100755 --- a/src/systemc/tests/verify.py +++ b/src/systemc/tests/verify.py @@ -105,7 +105,7 @@ class TestPhaseMeta(type): if not d.pop('abstract', False): test_phase_classes[d['name']] = cls - super(TestPhaseMeta, cls).__init__(name, bases, d) + super().__init__(name, bases, d) class TestPhaseBase(metaclass=TestPhaseMeta): abstract = True @@ -212,7 +212,7 @@ def info_filt(num): class DiffingChecker(Checker): def __init__(self, ref, test, tag, out_dir): - super(DiffingChecker, self).__init__(ref, test, tag) + super().__init__(ref, test, tag) self.out_dir = out_dir def is_bytes_mode(self):