Matthias Jung
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793cf882fe
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Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
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2014-07-15 22:49:33 +02:00 |
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Matthias Jung
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8b4e3fa4bf
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Integrated LibDRAMPower. Before you start you have to run the install_prerequisites.sh
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2014-07-15 22:47:02 +02:00 |
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Janik Schlemminger
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dc9d1b4b1f
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address decoder simplified
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2014-07-15 14:35:13 +02:00 |
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Janik Schlemminger
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c135d7c31b
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Traceplayer has a clock now
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2014-07-15 00:10:49 +02:00 |
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Robert Gernhardt
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c77048ac93
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renamed some stuff
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2014-07-14 23:17:18 +02:00 |
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Robert Gernhardt
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2b427ecb6e
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also shows clks now in tooltip in analyzer
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2014-07-11 09:22:34 +02:00 |
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robert
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b8febb434f
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minor refactoring
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2014-07-06 10:34:46 +02:00 |
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robert
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e128263833
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minor refactoring
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2014-07-01 13:58:55 +02:00 |
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robert
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37c147ba2f
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added debug message capabilities to scheduler
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2014-07-01 11:01:52 +02:00 |
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robert
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2b062b86ff
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changed scheduler interface. Fixed bug with terminateSimulation
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2014-06-20 15:49:07 +02:00 |
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robert
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5ec15f0ccf
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merged
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2014-06-16 17:43:22 +02:00 |
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robert
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4760ec4a5b
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adressmappings
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2014-06-16 17:41:47 +02:00 |
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Matthias Jung
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8ed200dfa3
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New metric script that plots a histogram, prerequisites install script added
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2014-05-28 14:35:45 +02:00 |
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robert
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c74b544f3e
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...
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2014-05-10 13:02:55 +02:00 |
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robert
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c5512389da
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changed project structure to qtcreator, added timed out powerdown
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2014-05-07 17:22:20 +02:00 |
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Matthias Jung
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00f95b1587
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timeout pdn (state: not runnning yet)
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2014-05-05 23:24:36 +02:00 |
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robert
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cb16bd3a8a
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changed simulation recorder to record filenames of memspec and memconfig
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2014-05-05 10:37:59 +02:00 |
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robert
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9b5ed54138
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addressmappings tested
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2014-04-21 09:55:37 +02:00 |
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robert
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dc456385cc
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new memconfigs
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2014-04-20 22:26:08 +02:00 |
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robert
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b75366edda
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addressmapping for ddr4
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2014-04-20 22:16:32 +02:00 |
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robert
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354c871047
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changed metrics
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2014-04-20 17:28:05 +02:00 |
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robert
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c501985573
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fixed bug in testscript
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2014-04-19 14:26:50 +02:00 |
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robert
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b074e3777d
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simulation config can now be passed as a argument to the console program
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2014-04-16 10:52:00 +02:00 |
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robert
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afc218b2b0
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all test are running for real now. And its only 3 am
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2014-04-14 03:10:54 +02:00 |
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robert
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522eededc2
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all tests are running
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2014-04-14 03:01:11 +02:00 |
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robert
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0a7829d0ad
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Changed constraints in all checkers to be generic for wideIO and ddr4
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2014-04-14 02:41:04 +02:00 |
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Janik Schlemminger
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6583a661d2
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tlm protocol, record in interface methods
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2014-04-13 14:38:17 +02:00 |
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robert
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856db2fde8
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merged
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2014-04-13 11:54:01 +02:00 |
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robert
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e354fb5652
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added recording of memconfig, memspec. Tests use the memconfig in a trace for the timing
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2014-04-13 11:01:21 +02:00 |
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Janik Schlemminger
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2c0f2c95a3
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simulation bug fix -> stop after termination delta cycle
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2014-04-13 02:17:05 +02:00 |
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Janik Schlemminger
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8d07af4431
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simulation manager extended to 4 player, refactoring, porno progress bar
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2014-04-13 01:30:38 +02:00 |
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Janik Schlemminger
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e9633c1b30
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cool simulation manager
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2014-04-12 20:43:10 +02:00 |
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Janik Schlemminger
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a1444a4d7b
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PowerDownChecker and release build setting added
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2014-04-12 11:44:27 +02:00 |
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Janik Schlemminger
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3914f4678b
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refactored refresh manager and powerdown
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2014-04-11 23:08:15 +02:00 |
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robert
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5c899dabe3
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merged
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2014-04-11 12:44:17 +02:00 |
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robert
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8bc3293dcb
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relocated getBankgroup function
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2014-04-11 12:42:49 +02:00 |
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Janik Schlemminger
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d313afa84a
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merge
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2014-04-11 12:26:43 +02:00 |
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Janik Schlemminger
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53d37036bc
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memconfig.xml changes ignored
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2014-04-11 12:16:10 +02:00 |
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Janik Schlemminger
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3ba934b45f
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refresh manager changed vector to map
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2014-04-10 10:22:16 +02:00 |
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robert
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a433ad6fcf
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bankgroup is now recorded
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2014-04-10 10:14:20 +02:00 |
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robert
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27e00659fa
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changed simulation manager
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2014-04-10 01:06:04 +02:00 |
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robert
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7c31ee8ee1
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resolved conflict
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2014-04-10 00:05:25 +02:00 |
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robert
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76ebfb2dd8
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added par_bs
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2014-04-10 00:04:38 +02:00 |
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Janik Schlemminger
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d6825125e1
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bankgroup in dram extension
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2014-04-09 21:22:42 +02:00 |
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Janik Schlemminger
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93bc1edb82
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length on data strobe different for double data rate and single data rate
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2014-04-09 20:15:03 +02:00 |
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robert
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abb3694391
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recording data strobe information now
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2014-04-09 16:53:11 +02:00 |
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Janik Schlemminger
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486a8dd78b
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Merge branch 'master' of https://git.rhrk.uni-kl.de/schlemmi/dram
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2014-04-09 13:56:28 +02:00 |
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Janik Schlemminger
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3bbf81584c
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first ddr4 changes
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2014-04-09 13:56:24 +02:00 |
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robert
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e51deb97ec
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changed stuff, refresh aware
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2014-04-09 13:54:37 +02:00 |
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Janik Schlemminger
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339dfbbdbb
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config xml extended
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2014-04-09 12:36:02 +02:00 |
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