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timeout pdn (state: not runnning yet)

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This commit is contained in:
Matthias Jung
2014-05-05 23:24:36 +02:00
parent cb16bd3a8a
commit 00f95b1587
24 changed files with 399 additions and 100 deletions
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4
dram/.settings/language.settings.xml
View File

@@ -4,7 +4,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-60060699001507781" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-236546927659285406" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
@@ -14,7 +14,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-60060699001507781" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-236546927659285406" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

6
dram/resources/configs/memconfigs/memconfig.xml
View File

@@ -1,11 +1,13 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="1" />
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
<parameter id="powerDownMode" type="string" value="TimeoutPDN" />
<parameter id="powerDownTimeout" type="uint" value="7" />
</memconfig>
</memspec>
</memspec>

7
dram/resources/scripts/metrics.py
View File

@@ -1,6 +1,5 @@
import sys
import sqlite3
import pystaggrelite3
metrics = []
threadMetrics = []
@@ -248,8 +247,8 @@ def passRatio(connection):
def calculateMetrics(pathToTrace):
connection = sqlite3.connect(pathToTrace)
connection.create_aggregate("median", 1, pystaggrelite3.median)
connection.create_aggregate("stdev", 1, pystaggrelite3.stdev)
#connection.create_aggregate("median", 1, pystaggrelite3.median)
#connection.create_aggregate("stdev", 1, pystaggrelite3.stdev)
calculatedMetrics = []
@@ -281,4 +280,4 @@ def calculateMetrics(pathToTrace):
if __name__ == "__main__":
path = sys.argv[1]
calculateMetrics(path)

124
dram/resources/scripts/tests.py
View File

@@ -1,12 +1,11 @@
import sys
import traceback
import sqlite3
import math
import os
import xml.etree.ElementTree as ET
from sets import Set
def getPathToConfigs():
return os.path.dirname(__file__).replace("/scripts","/configs")
return os.path.dirname(os.path.abspath(__file__).replace("/scripts","/configs"))
def getValueFromConfigXML(root, id):
return root.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value']
@@ -192,33 +191,33 @@ def commands_are_clockaligned(connection):
cursor = connection.cursor()
query = "select ID,PhaseBegin,PhaseEnd from phases where phaseName NOT IN ('REQ','RESP') AND (phaseBegin%:clk!=0 OR phaseEnd%:clk!=0)"
cursor.execute(query, {"clk": dramconfig.clk})
cursor.execute(query, {"clk": dramconfig.clk})
result = cursor.fetchone()
if(result != None):
return TestFailed("Command with PhaseID {0} starts at {1} and ends at. One of those times. is not aligned to system clock ({2})"
.format(result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk)))
result = cursor.fetchone()
if(result != None):
return TestFailed("Command with PhaseID {0} starts at {1} and ends at. One of those times. is not aligned to system clock ({2})"
.format(result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk)))
return TestSuceeded()
@test
def commandbus_slots_are_used_once(connection):
"""Checks that no two phases on the command bus start at the same time"""
cursor = connection.cursor()
if dramconfig.bankwiseLogic:
excludedPhases = "('REQ','RESP','PRE_ALL')"
else:
excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF','AUTO_REFRESH')"
query = """SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count
if dramconfig.bankwiseLogic:
excludedPhases = "('REQ','RESP','PRE_ALL')"
else:
excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF','AUTO_REFRESH')"
query = """SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count
FROM Phases WHERE PhaseName NOT IN """ + excludedPhases + """ AND phasebegin>0 GROUP BY phaseBegin) WHERE count>1"""
cursor.execute(query)
result = cursor.fetchone()
result = cursor.fetchone()
if(result != None):
return TestFailed("Slot on commandbus at time {0} is used multiple times".format(formatTime(result[0])))
return TestFailed("Slot on commandbus at time {0} is used multiple times".format(formatTime(result[0])))
return TestSuceeded()
@@ -230,42 +229,42 @@ def phase_transitions_are_valid(connection):
validTransitions = {}
if(dramconfig.bankwiseLogic):
validTransitions['PRE'] = Set(['ACT', 'AUTO_REFRESH'])
validTransitions['ACT'] = Set(['RD', 'RDA', 'WR', 'WRA'])
validTransitions['PRE'] = set(['ACT', 'AUTO_REFRESH'])
validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA'])
validTransitions['RD'] = Set(['PRE','RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['WR'] = Set(['PRE', 'RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['RDA'] = Set(['ACT', 'AUTO_REFRESH', 'PDNP'])
validTransitions['WRA'] = Set(['ACT', 'AUTO_REFRESH', 'PDNP'])
validTransitions['RD'] = set(['PRE','RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['WR'] = set(['PRE', 'RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['RDA'] = set(['ACT', 'AUTO_REFRESH', 'PDNP'])
validTransitions['WRA'] = set(['ACT', 'AUTO_REFRESH', 'PDNP'])
validTransitions['AUTO_REFRESH'] = Set(['ACT', 'PDNP', 'SREF'])
validTransitions['AUTO_REFRESH'] = set(['ACT', 'PDNP', 'SREF'])
validTransitions['PDNA'] = Set(['PRE', 'RD','RDA', 'WR', 'WRA', 'AUTO_REFRESH'])
validTransitions['PDNP'] = Set(['ACT', 'AUTO_REFRESH'])
validTransitions['SREF'] = Set(['ACT'])
validTransitions['PDNA'] = set(['PRE', 'RD','RDA', 'WR', 'WRA', 'AUTO_REFRESH'])
validTransitions['PDNP'] = set(['ACT', 'AUTO_REFRESH'])
validTransitions['SREF'] = set(['ACT'])
else:
validTransitions['PRE'] = Set(['ACT'])
validTransitions['PRE_ALL'] = Set(['AUTO_REFRESH'])
validTransitions['ACT'] = Set(['RD', 'RDA', 'WR', 'WRA'])
validTransitions['PRE'] = set(['ACT'])
validTransitions['PRE_ALL'] = set(['AUTO_REFRESH'])
validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA'])
validTransitions['RD'] = Set(['PRE', 'PRE_ALL','RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['WR'] = Set(['PRE', 'PRE_ALL','RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['RDA'] = Set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['WRA'] = Set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['RD'] = set(['PRE', 'PRE_ALL','RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['WR'] = set(['PRE', 'PRE_ALL','RD','RDA', 'WR', 'WRA', 'PDNA'])
validTransitions['RDA'] = set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['WRA'] = set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['AUTO_REFRESH'] = Set(['PRE_ALL', 'ACT','AUTO_REFRESH', 'PDNA', 'PDNP', 'SREF'])
validTransitions['AUTO_REFRESH'] = set(['PRE_ALL', 'ACT','AUTO_REFRESH', 'PDNA', 'PDNP', 'SREF'])
validTransitions['PDNA'] = Set(['PRE','PRE_ALL','ACT', 'RD', 'RDA', 'WR', 'WRA', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['PDNP'] = Set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['SREF'] = Set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['PDNA'] = set(['PRE','PRE_ALL','ACT', 'RD', 'RDA', 'WR', 'WRA', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['PDNP'] = set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
validTransitions['SREF'] = set(['PRE_ALL', 'ACT', 'AUTO_REFRESH', 'PDNA', 'PDNP'])
query = """SELECT PhaseName, phases.ID FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE TBank=:bank
AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin"""
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query, {"bank": bankNumber})
lastRow = cursor.fetchone()
cursor.execute(query, {"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
currentPhase = currentRow[0]
lastPhase = lastRow[0]
@@ -337,8 +336,8 @@ def timing_constraits_on_the_same_bank_hold(connection):
AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin"""
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query, {"bank": bankNumber})
lastRow = cursor.fetchone()
cursor.execute(query, {"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
constraint = timing_constraint(lastRow,currentRow)
@@ -367,7 +366,7 @@ def row_buffer_is_used_correctly(connection):
idlePhases = set(['ACT', 'PDNP', 'AUTO_REFRESH', 'SREF'])
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
cursor.execute(query,{"bank": bankNumber})
rowBufferIsClosed = True
@@ -417,9 +416,9 @@ def activate_to_activate_on_same_bank_holds(connection):
cursor = connection.cursor()
query = "SELECT Phases.ID,PhaseBegin from Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID WHERE PhaseName = 'ACT' AND TBANK = :bank ORDER BY PhaseBegin"
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
timeBetweenActivates = currentRow[1] - lastRow[1];
@@ -502,9 +501,9 @@ def write_to_read_and_read_to_write_hold(connection):
for currentRow in cursor:
if(currentRow[2] in ["RD","RDA"] and lastRow[2] in ["WR","WRA"]):
#write to read
if (currentRow[3] == lastRow[3]):
if(currentRow[2] in ["RD","RDA"] and lastRow[2] in ["WR","WRA"]):
#write to read
if (currentRow[3] == lastRow[3]):
tWTR = dramconfig.tWTR_L
else:
tWTR = dramconfig.tWTR_S
@@ -512,19 +511,19 @@ def write_to_read_and_read_to_write_hold(connection):
minWriteToRead = dramconfig.tWL + dramconfig.getWriteAccessTime() + tWTR
writeToRead = currentRow[1] - lastRow[1]
if(writeToRead < minWriteToRead ):
return TestFailed("Read {0} starts {1} after start of write {2}. Minimum time is {3}".
if(writeToRead < minWriteToRead ):
return TestFailed("Read {0} starts {1} after start of write {2}. Minimum time is {3}".
format(currentRow[0],formatTime(writeToRead),lastRow[0], formatTime(minWriteToRead)))
elif(currentRow[2] in ["WR","WRA"] and lastRow[2] in ["RD","RDA"]):
elif(currentRow[2] in ["WR","WRA"] and lastRow[2] in ["RD","RDA"]):
#read to write
minReadToWrite = dramconfig.tRL + dramconfig.getReadAccessTime() - dramconfig.tWL + dramconfig.clk * 2
readToWrite = currentRow[1] - lastRow[1]
if(readToWrite < minReadToWrite ):
return TestFailed("Write {0} starts {1} after start of read {2}. Minimum time is {3}".
format(currentRow[0],formatTime(readToWrite),lastRow[0], formatTime(minWriteToRead)))
lastRow = currentRow
format(currentRow[0],formatTime(readToWrite),lastRow[0], formatTime(minWriteToRead)))
lastRow = currentRow
return TestSuceeded()
@@ -542,9 +541,9 @@ def read_holds_dll_constraint_after_sref(connection):
cursor.execute(query,{"bank": bankNumber})
lastRow = cursor.fetchone()
for currentRow in cursor:
if(currentRow[2] in ["RD","RDA"] and lastRow[2] == 'SREF'):
if(currentRow[2] in ["RD","RDA"] and lastRow[2] == 'SREF'):
srefEndToRead = currentRow[1] - (lastRow[1] - dramconfig.clk)
if(srefEndToRead < dramconfig.tXSRDLL ):
if(srefEndToRead < dramconfig.tXSRDLL ):
return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}".
format(currentRow[0],formatTime(srefEndToRead),lastRow[0], formatTime(dramconfig.tXSRDLL)))
lastRow = currentRow
@@ -608,10 +607,11 @@ def runTests(pathToTrace):
print("================================")
connection.close()
return testResults
if __name__ == "__main__":
sys.stdout = os.fdopen(sys.stdout.fileno(), 'w', 0)
for i in range(1,len(sys.argv)):
runTests(sys.argv[i])
sys.stdout = os.fdopen(sys.stdout.fileno(), 'w')
for i in range(1,len(sys.argv)):
runTests(sys.argv[i])

6
dram/resources/simulations/sim-batch.xml
View File

@@ -6,15 +6,13 @@
<!-- <addressmapping>am_lowPara.xml</addressmapping>
-->
<addressmapping>am_lowHits.xml</addressmapping>
<addressmapping>am_lowPara.xml</addressmapping>
<memconfigs>
<memconfig>fr_fcfs.xml</memconfig>
<memconfig>fifo.xml</memconfig>
<memconfig>memconfig.xml</memconfig>
</memconfigs>
<trace-setups>
<trace-setup id="13">
<device >mediabench-fractal_32.stl</device>
<device >chstone-jpeg_32.stl</device>
</trace-setup>
</trace-setups>

4
dram/src/common/protocol.h
View File

@@ -42,7 +42,9 @@ DECLARE_EXTENDED_PHASE(END_SREF);
//Triggers
DECLARE_EXTENDED_PHASE(REFRESH_TRIGGER);
DECLARE_EXTENDED_PHASE(REF_TRIGGER);
DECLARE_EXTENDED_PHASE(PDN_TRIGGER);
#endif

10
dram/src/core/ControllerCore.cpp
View File

@@ -19,6 +19,7 @@
#include "../common/dramExtension.h"
#include "../common/Utils.h"
#include "powerdown/PowerDownManager.h"
#include "powerdown/PowerDownManagerTimeout.h"
#include "powerdown/PowerDownManagerBankwise.h"
#include "../common/DebugManager.h"
@@ -55,7 +56,14 @@ ControllerCore::ControllerCore(IWrapperConnector& wrapperConnector, std::map<Ban
else
{
refreshManager = new RefreshManager(*this);
powerDownManager = new PowerDownManager(*this);
if(config.powerDownMode == PowerDownMode::Staggered)
{
powerDownManager = new PowerDownManager(*this);
}
else // TimeoutPDN or TimeoutSREF
{
powerDownManager = new PowerDownManagerTimeout(*this);
}
}
}

17
dram/src/core/ControllerState.cpp
View File

@@ -29,6 +29,23 @@ const ScheduledCommand ControllerState::getLastCommand(Command command)
return max;
}
const ScheduledCommand ControllerState::getLastScheduledCommand()
{
ScheduledCommand lastCommand;
for(Command cmd : getAllCommands())
{
for(Bank bank : Configuration::getInstance().getBanks())
{
ScheduledCommand& current = lastCommandsOnBus[cmd][bank];
if (current.getStart() > lastCommand.getStart())
lastCommand = current;
}
}
return lastCommand;
}
const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank)
{
ScheduledCommand lastCommand;

1
dram/src/core/ControllerState.h
View File

@@ -33,6 +33,7 @@ public:
const ScheduledCommand getLastCommand(Command command, Bank bank);
const ScheduledCommand getLastCommand(Command command);
const ScheduledCommand getLastScheduledCommand(Bank bank);
const ScheduledCommand getLastScheduledCommand();
void change(const ScheduledCommand& scheduledCommand);
void cleanUp(sc_time time);

15
dram/src/core/configuration/Configuration.cpp
View File

@@ -21,5 +21,20 @@ Configuration::Configuration()
loader.loadConfiguration(*this, Configuration::memspecUri, Configuration::memconfigUri);
}
const std::vector<Bank>& Configuration::getBanks() const
{
static std::vector<Bank> banks;
if (banks.size() == 0)
{
for (unsigned int i = 0; i < NumberOfBanks; i++)
{
banks.push_back(Bank(i));
}
}
return banks;
}
} /* namespace core */

11
dram/src/core/configuration/Configuration.h
View File

@@ -15,6 +15,9 @@
namespace core{
enum class PowerDownMode{Staggered, TimeoutPDN, TimeoutSREF};
struct Configuration
{
static std::string memspecUri;
@@ -37,6 +40,10 @@ struct Configuration
unsigned int DataRate;
unsigned int NumberOfRows;
// Powerdown Mode
sc_time powerDownTimeout;
PowerDownMode powerDownMode;
//MemTimings
TimingConfiguration Timings;
@@ -49,6 +56,10 @@ struct Configuration
std::string Scheduler;
unsigned int Capsize;
const std::vector<Bank>& getBanks() const;
private:
Configuration();
};

22
dram/src/core/configuration/MemSpecLoader.cpp
View File

@@ -53,6 +53,22 @@ void MemSpecLoader::loadConfig(Configuration& config, XMLElement* memspec)
config.MaxNrOfTransactions = queryUIntParameter(configuration, "maxNrOfTransactionsInDram");
config.Scheduler = queryStringParameter(configuration, "scheduler");
config.Capsize = queryUIntParameter(configuration, "capsize");
string mode = queryStringParameter(configuration, "powerDownMode");
if (mode.compare("Staggered") == 0)
{
config.powerDownMode = PowerDownMode::Staggered;
}
else if (mode.compare("TimeoutPDN") == 0)
{
config.powerDownMode = PowerDownMode::TimeoutPDN;
}
else if (mode.compare("TimeoutSREF") == 0)
{
config.powerDownMode = PowerDownMode::TimeoutSREF;
}
config.powerDownTimeout = queryUIntParameter(configuration, "powerDownTimeout") * config.Timings.clk;
}
void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
@@ -101,8 +117,7 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
{
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC,
config.Timings.tREFI);
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, config.Timings.tREFI);
}
}
@@ -152,8 +167,7 @@ void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec)
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
{
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC,
config.Timings.tREFI);
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, config.Timings.tREFI);
}
}

7
dram/src/core/powerdown/IPowerDownManager.h
View File

@@ -8,7 +8,10 @@
#ifndef IPOWERDOWNMANAGER_H_
#define IPOWERDOWNMANAGER_H_
#include <systemc>
#include <systemc.h>
#include "../../common/dramExtension.h"
#include "../Command.h"
namespace core {
@@ -23,6 +26,8 @@ public:
virtual ~IPowerDownManager() {}
virtual void sleep(Bank bank, sc_time time) = 0;
virtual void triggerSleep(Bank bank, sc_time time) = 0;
virtual void wakeUp(Bank bank, sc_time time) = 0;
virtual void wakeUpForRefresh(Bank bank, sc_time time) = 0;

6
dram/src/core/powerdown/PowerDownManager.cpp
View File

@@ -156,5 +156,11 @@ bool PowerDownManager::isAwakeForRefresh()
return powerDownState == PowerDownState::AwakeForRefresh;
}
void PowerDownManager::triggerSleep(Bank bank, sc_time time)
{
sleep(bank, time);
}
} /* namespace core */

1
dram/src/core/powerdown/PowerDownManager.h
View File

@@ -20,6 +20,7 @@ public:
PowerDownManager(ControllerCore& controller);
virtual ~PowerDownManager();
virtual void triggerSleep(Bank bank, sc_time time) override;
virtual void sleep(Bank bank, sc_time time) override;
virtual void wakeUp(Bank bank, sc_time time) override;
virtual void wakeUpForRefresh(Bank bank, sc_time time) override;

6
dram/src/core/powerdown/PowerDownManagerBankwise.cpp
View File

@@ -143,5 +143,11 @@ bool PowerDownManagerBankwise::canSleep(Bank bank)
return controller.numberOfPayloads[bank] == 0;
}
void PowerDownManagerBankwise::triggerSleep(Bank bank, sc_time time)
{
sleep(bank, time);
}
}/* namespace core */

1
dram/src/core/powerdown/PowerDownManagerBankwise.h
View File

@@ -28,6 +28,7 @@ public:
virtual ~PowerDownManagerBankwise()
{
}
virtual void triggerSleep(Bank bank, sc_time time) override;
virtual void sleep(Bank bank, sc_time time) override;
virtual void wakeUp(Bank bank, sc_time time) override;
virtual void wakeUpForRefresh(Bank bank, sc_time time) override;

140
dram/src/core/powerdown/PowerDownManagerTimeout.cpp Normal file
View File

@@ -0,0 +1,140 @@
/*
* PowerDownManagerTimeout.cpp
*
* Created on: May 5, 2014
* Author: jungma
*/
#include "PowerDownManagerTimeout.h"
#include "../ControllerCore.h"
#include "../../common/Utils.h"
using namespace tlm;
namespace core {
PowerDownManagerTimeout::PowerDownManagerTimeout(ControllerCore& controller): controller(controller)
{
for (Bank bank : controller.getBanks())
{
setUpDummy(powerDownPayloads[bank], bank);
}
}
PowerDownManagerTimeout::~PowerDownManagerTimeout()
{
// TODO Auto-generated destructor stub
}
void PowerDownManagerTimeout::sleep(Bank bank, sc_time time)
{
if(canSleep() && (time - controller.state.getLastScheduledCommand().getEnd()) >= Configuration::getInstance().powerDownTimeout)
{
PowerDownState state;
if(Configuration::getInstance().powerDownMode == PowerDownMode::TimeoutPDN)
{
state = controller.state.bankStates.allRowBuffersAreClosed() ? PowerDownState::PDNPrecharge : PowerDownState::PDNActive;
}
else
{
state = PowerDownState::PDNSelfRefresh;
}
Command cmd = IPowerDownManager::getSleepCommand(powerDownState);
ScheduledCommand pdn(cmd, time, getMinimalExecutionTime(cmd, powerDownPayloads[bank]),
DramExtension::getExtension(powerDownPayloads[bank]));
controller.getCommandChecker(cmd).delayToSatisfyConstraints(pdn);
if (controller.refreshManager->hasCollision(pdn))
{
return;
}
else
{
setPowerDownState(state);
sendPowerDownPayloads(pdn);
}
}
}
bool PowerDownManagerTimeout::isInPowerDown()
{
return (powerDownState == PowerDownState::PDNActive || powerDownState == PowerDownState::PDNPrecharge
|| powerDownState == PowerDownState::PDNSelfRefresh);
}
void PowerDownManagerTimeout::setPowerDownState(PowerDownState state)
{
powerDownState = state;
DebugManager::getInstance().printDebugMessage(PowerDownManagerBankwise::senderName,
"Is now in state " + powerDownStateToString(powerDownState) + " on all banks");
}
void PowerDownManagerTimeout::wakeUp(Bank bank, sc_time time)
{
if (isInPowerDown()) //Request wakes up power down
{
Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState);
ScheduledCommand pdn(cmd, time, getExecutionTime(cmd, powerDownPayloads[bank]),
DramExtension::getExtension(powerDownPayloads[bank]));
controller.getCommandChecker(cmd).delayToSatisfyConstraints(pdn);
if (cmd == Command::SREFX)
controller.refreshManager->reInitialize(bank, pdn.getEnd());
setPowerDownState(PowerDownState::Awake);
sendPowerDownPayloads(pdn);
}
}
void PowerDownManagerTimeout::wakeUpForRefresh(Bank bank, sc_time time)
{
if (isInPowerDown())
{
Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState);
ScheduledCommand pdn(cmd, time, getExecutionTime(cmd, powerDownPayloads[bank]),
DramExtension::getExtension(powerDownPayloads[bank]));
setPowerDownState(PowerDownState::AwakeForRefresh);
sendPowerDownPayloads(pdn);
}
}
void PowerDownManagerTimeout::triggerSleep(Bank bank, sc_time time)
{
if(canSleep())
{
controller.wrapper.send(REFTrigger, time + controller.config.powerDownTimeout, pdn_trigger);
}
}
bool PowerDownManagerTimeout::isInSelfRefresh(Bank bank)
{
return powerDownState == PowerDownState::PDNSelfRefresh;
}
bool PowerDownManagerTimeout::canSleep()
{
for (Bank bank : controller.getBanks())
{
if (!controller.numberOfPayloads[bank] == 0)
return false;
}
return true;
}
void PowerDownManagerTimeout::sendPowerDownPayloads(ScheduledCommand& cmd)
{
controller.state.bus.moveCommandToNextFreeSlot(cmd);
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payloadToSend = powerDownPayloads[bank];
ScheduledCommand pdnToSend(cmd.getCommand(), cmd.getStart(), cmd.getExecutionTime(),
DramExtension::getExtension(payloadToSend));
controller.state.change(pdnToSend);
controller.wrapper.send(pdnToSend, payloadToSend);
}
}
}

51
dram/src/core/powerdown/PowerDownManagerTimeout.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* PowerDownManagerTimeout.h
*
* Created on: May 5, 2014
* Author: jungma
*/
#ifndef POWERDOWNMANAGERTIMEOUT_H_
#define POWERDOWNMANAGERTIMEOUT_H_
#include "IPowerDownManager.h"
#include <systemc.h>
#include "../../common/dramExtension.h"
#include <map>
#include "../scheduling/ScheduledCommand.h"
namespace core {
class ControllerCore;
class PowerDownManagerTimeout: public core::IPowerDownManager
{
public:
PowerDownManagerTimeout(ControllerCore& controller);
virtual ~PowerDownManagerTimeout();
virtual void triggerSleep(Bank bank, sc_time time);
virtual void sleep(Bank bank, sc_time time);
virtual void wakeUp(Bank bank, sc_time time);
virtual void wakeUpForRefresh(Bank bank, sc_time time);
virtual bool isInSelfRefresh(Bank bank);
private:
bool canSleep();
ControllerCore& controller;
tlm::tlm_generic_payload pdn_trigger;
std::map<Bank, tlm::tlm_generic_payload> powerDownPayloads;
void sendPowerDownPayloads(ScheduledCommand& cmd);
PowerDownState powerDownState;
void setPowerDownState(PowerDownState state);
bool isInPowerDown();
};
}
#endif /* POWERDOWNMANAGERTIMEOUT_H_ */

2
dram/src/core/refresh/RefreshManager.cpp
View File

@@ -76,7 +76,7 @@ void RefreshManager::sendToAllBanks(ScheduledCommand& command)
void RefreshManager::planNextRefresh()
{
nextPlannedRefresh += timing.tREFI;
controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads[Bank(0)]);
controller.wrapper.send(REFTrigger, nextPlannedRefresh, refreshPayloads[Bank(0)]);
}
void RefreshManager::reInitialize(Bank bank, sc_time time)

2
dram/src/core/refresh/RefreshManagerBankwise.cpp
View File

@@ -70,7 +70,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload,
void RefreshManagerBankwise::planNextRefresh(Bank bank)
{
nextPlannedRefreshs[bank] += Configuration::getInstance().Timings.refreshTimings[bank].tREFI;
controller.wrapper.send(RefreshTrigger, nextPlannedRefreshs[bank], refreshPayloads[bank]);
controller.wrapper.send(REFTrigger, nextPlannedRefreshs[bank], refreshPayloads[bank]);
}
void RefreshManagerBankwise::reInitialize(Bank bank, sc_time time)

2
dram/src/core/scheduling/Trigger.h
View File

@@ -10,7 +10,7 @@
namespace core {
enum Trigger {RefreshTrigger, WakeUpTrigger};
enum Trigger {REFTrigger, PDNTrigger};
} /* namespace controller */

51
dram/src/simulation/Controller.h
View File

@@ -8,25 +8,40 @@
#ifndef CONTROLLERWRAPPER_H_
#define CONTROLLERWRAPPER_H_
#include <tlm.h>
#include <systemc.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <iostream>
//#include <systemc.h>
//#include <tlm_utils/peq_with_cb_and_phase.h>
//#include <tlm_utils/simple_initiator_socket.h>
//#include <tlm_utils/simple_target_socket.h>
//#include <iostream>
#include <map>
#include <string>
#include <vector>
#include "../common/Utils.h"
//#include <tlm.h>
#include "/opt/systemc-2.3.0/include/systemc"
#include "/opt/systemc-2.3.0/include/tlm"
#include "/opt/systemc-2.3.0/include/tlm_utils/peq_with_cb_and_phase.h"
#include "/opt/systemc-2.3.0/include/tlm_utils/simple_initiator_socket.h"
#include "/opt/systemc-2.3.0/include/tlm_utils/simple_target_socket.h"
#include "../common/dramExtension.h"
#include "../common/DebugManager.h"
#include "../common/protocol.h"
#include "../common/TlmRecorder.h"
#include "../common/DebugManager.h"
#include "../core/IWrapperConnector.h"
#include "../common/Utils.h"
#include "../core/configuration/Configuration.h"
#include "../core/configuration/TimingConfiguration.h"
#include "../core/Command.h"
#include "../core/ControllerCore.h"
#include "../scheduler/Scheduler.h"
#include "../core/ControllerState.h"
#include "../core/IWrapperConnector.h"
#include "../core/powerdown/IPowerDownManager.h"
#include "../core/scheduling/ScheduledCommand.h"
#include "../core/scheduling/Trigger.h"
#include "../core/TimingCalculation.h"
#include "../scheduler/Fifo.h"
#include "../scheduler/Fr_Fcfs.h"
#include "../scheduler/PARBS.h"
//#include "../scheduler/Scheduler.h"
using namespace std;
using namespace tlm;
@@ -156,9 +171,13 @@ public:
sc_assert(time >= sc_time_stamp());
sc_time delay = time - sc_time_stamp();
if (trigger == Trigger::RefreshTrigger)
if (trigger == Trigger::REFTrigger)
{
controllerCorePEQ.notify(payload, REFRESH_TRIGGER, delay);
controllerCorePEQ.notify(payload, REF_TRIGGER, delay);
}
else if (trigger == Trigger::PDNTrigger)
{
controllerCorePEQ.notify(payload, PDN_TRIGGER, delay);
}
else
{
@@ -168,10 +187,14 @@ public:
void controllerCorePEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
{
if (phase == REFRESH_TRIGGER)
if (phase == REF_TRIGGER)
{
controller->triggerRefresh(payload, sc_time_stamp());
}
else if (phase == PDN_TRIGGER)
{
controller->powerDownManager->sleep(DramExtension::getExtension(payload).getBank(),sc_time_stamp());
}
else
{
Bank bank = DramExtension::getExtension(payload).getBank();
@@ -277,7 +300,7 @@ private:
printDebugMessage(
"Payload left system on bank " + to_string(bank.ID()) + ". Total number of payloads in Controller: "
+ to_string(getTotalNumberOfPayloadsInSystem()));
controller->powerDownManager->sleep(bank, sc_time_stamp());
controller->powerDownManager->triggerSleep(bank, sc_time_stamp());
}

3
dram/src/simulation/main.cpp
View File

@@ -40,13 +40,12 @@ int sc_main(int argc, char **argv)
if(argc > 1)
simulationToRun = argv[1];
else
simulationToRun = "first.xml";
simulationToRun = "sim-batch.xml";
SimulationManager manager(resources);
manager.loadSimulationsFromXML(resources + "/simulations/" + simulationToRun);
manager.silent = false;
manager.runSimulations();
manager.startTraceAnalyzer();
return 0;
}