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changed simulation recorder to record filenames of memspec and memconfig

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This commit is contained in:
robert
2014-05-05 10:37:59 +02:00
parent 9b5ed54138
commit cb16bd3a8a
14 changed files with 115 additions and 180 deletions
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11
dram/resources/configs/memconfigs/fifo_n100.xml
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@@ -1,11 +0,0 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="100" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

11
dram/resources/configs/memconfigs/fifo_n1000.xml
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@@ -1,11 +0,0 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="1000" />
<parameter id="scheduler" type="string" value="FIFO" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

11
dram/resources/configs/memconfigs/fifo_n20.xml
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@@ -1,11 +0,0 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="20" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

11
dram/resources/configs/memconfigs/fifo_n5.xml
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@@ -1,11 +0,0 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="5" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

11
dram/resources/configs/memconfigs/fifo_n50.xml
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@@ -1,11 +0,0 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

11
dram/resources/configs/memconfigs/par_bs.xml
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@@ -1,11 +0,0 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="PAR_BS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

5
dram/resources/configs/memspecs/DDR4.xml
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@@ -1,6 +1,5 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
@@ -15,9 +14,7 @@
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1200" />
<!-- <parameter id="REFI" type="uint" value="4680" />
-->
<parameter id="REFI" type="uint" value="1000" />
<parameter id="REFI" type="uint" value="4680" />
<parameter id="RFC" type="uint" value="313" />
<parameter id="RL" type="uint" value="16" />
<parameter id="WL" type="uint" value="16" />

7
dram/resources/configs/memspecs/WideIO.xml
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@@ -5,7 +5,6 @@
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<!-- <parameter id="nbrOfRanks" type="uint" value="1" />-->
<parameter id="nbrOfColumns" type="uint" value="128" />-
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="1" />
@@ -20,16 +19,12 @@
<parameter id="RFC" type="uint" value="22" />
<parameter id="RAS" type="uint" value="6" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<!--<parameter id="DQSCK" type="uint" value="1" />-->
<parameter id="AL" type="uint" value="0" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<!--<parameter id="XPDLL" type="uint" value="2" />-->
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<!--<parameter id="XSDLL" type="uint" value="20" />-->
<parameter id="REFI" type="uint" value="1300" />
<!--<parameter id="CL" type="uint" value="3" />-->
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />

117
dram/resources/scripts/metrics.py
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@@ -42,6 +42,53 @@ def average_response_latency_in_ns(connection):
result = cursor.fetchone()
return round(result[0],1)
def refreshMissDecision(connection,calculatedMetrics):
cursor = connection.cursor()
cursor.execute("""SELECT phases.ID,PhaseBegin,PhaseEnd,TBank FROM Phases INNER JOIN transactions on transactions.id = phases.transact WHERE PhaseName='AUTO_REFRESH' """)
queryMinREQ = """SELECT id,min(PhaseBegin) FROM (SELECT transactions.id, PhaseBegin FROM transactions
inner join ranges on ranges.id = transactions.range inner join phases on phases.transact = transactions.id
where tthread != 0 and tbank = :bank and PhaseName = "REQ" and ranges.begin<:begin and ranges.end>:end)"""
queryMinRESP = """SELECT id,min(PhaseBegin) FROM (SELECT transactions.id, PhaseBegin FROM transactions
inner join ranges on ranges.id = transactions.range inner join phases on phases.transact = transactions.id
where tthread != 0 and tbank = :bank and PhaseName = "RESP" and ranges.begin<:begin and ranges.end>:end) """
missDecisions = 0
totalDecisios = 0
for refresh in cursor:
id = refresh[0]
begin = refresh[1]
end = refresh[2]
bank = refresh[3]
#print('Refresh: {0} {1} {2} {3}'.format(id,begin,end,bank))
cursorMinREQ = connection.cursor()
cursorMinRESP = connection.cursor()
cursorMinREQ.execute(queryMinREQ, {"bank":bank, "begin":begin, "end":end})
cursorMinRESP.execute(queryMinRESP, {"bank":bank, "begin":begin, "end":end})
earliestReq = cursorMinREQ.fetchone()
earliestResp = cursorMinRESP.fetchone()
if(earliestReq[0] != None):
totalDecisios = totalDecisios + 1
if(earliestReq[0] != earliestResp[0]):
missDecisions = missDecisions + 1
print("earliest Req: {0}| earliest Res: {1}".format(earliestReq[0], earliestResp[0]))
end
if(totalDecisios != 0):
calculatedMetrics.append(("Total Missdecisions", missDecisions))
calculatedMetrics.append(("Relative Missdecisions", 1.0*missDecisions/totalDecisios))
else:
calculatedMetrics.append(("Total Missdecisions", 0))
calculatedMetrics.append(("Relative Missdecisions", 0))
# @metric
# def median_response_latency_in_ns(connection):
# cursor = connection.cursor()
@@ -75,15 +122,15 @@ def average_response_latency_in_ns(connection):
# return round(result[0],1)
# @threadMetric
# def average_response_latency_in_ns(connection, thread):
# cursor = connection.cursor()
# query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """
@threadMetric
def average_response_latency_in_ns(connection, thread):
cursor = connection.cursor()
query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """
# cursor.execute(query, {"Thread": thread})
# result = cursor.fetchone()
# return round(result[0],1)
cursor.execute(query, {"Thread": thread})
result = cursor.fetchone()
return round(result[0],1)
# @threadMetric
# def median_response_latency_in_ns(connection, thread):
@@ -95,26 +142,26 @@ def average_response_latency_in_ns(connection):
# result = cursor.fetchone()
# return round(result[0],1)
@metric
def number_of_activates(connection):
cursor = connection.cursor()
cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName = 'ACT'")
result = cursor.fetchone()
return result[0]
# @metric
# def number_of_activates(connection):
# cursor = connection.cursor()
# cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName = 'ACT'")
# result = cursor.fetchone()
# return result[0]
@metric
def number_of_precharges(connection):
cursor = connection.cursor()
cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName IN ('PRE','PRE_ALL','RDA','WRA')")
result = cursor.fetchone()
return result[0]
# @metric
# def number_of_precharges(connection):
# cursor = connection.cursor()
# cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName IN ('PRE','PRE_ALL','RDA','WRA')")
# result = cursor.fetchone()
# return result[0]
@metric
def accesses_per_activate(connection):
cursor = connection.cursor()
cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName IN ('REQ')")
result = cursor.fetchone()
return round(result[0]*1.0/number_of_activates(connection),1)
# @metric
# def accesses_per_activate(connection):
# cursor = connection.cursor()
# cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName IN ('REQ')")
# result = cursor.fetchone()
# return round(result[0]*1.0/number_of_activates(connection),1)
def timeInPowerStates(connection):
totalTimeAllBanks = getTraceLength(connection)*getNumberOfBanks(connection)
@@ -215,15 +262,19 @@ def calculateMetrics(pathToTrace):
print("{0}: {1}".format(res[0],res[1]))
calculatedMetrics.append(res)
# for thread in getThreads(connection):
# for metric in threadMetrics:
# res = ("Thread " + str(thread) + " " + metric.__name__.replace("_"," "), metric(connection, thread))
# print("{0}: {1}".format(res[0],res[1]))
# calculatedMetrics.append(res)
for thread in getThreads(connection):
for metric in threadMetrics:
res = ("Thread " + str(thread) + " " + metric.__name__.replace("_"," "), metric(connection, thread))
print("{0}: {1}".format(res[0],res[1]))
calculatedMetrics.append(res)
calculatedMetrics.extend(passRatio(connection))
calculatedMetrics.append(("test",0))
#calculatedMetrics.extend(passRatio(connection))
#calculatedMetrics.extend(timeInPowerStates(connection))
refreshMissDecision(connection, calculatedMetrics)
print(calculatedMetrics[-1])
print(calculatedMetrics[-2])
connection.close()
return calculatedMetrics

24
dram/resources/simulations/datasizes.xml
View File

@@ -2,29 +2,21 @@
<memspec>JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml</memspec>
<addressmapping>am_wideioFourBanks.xml</addressmapping>
<memconfigs>
<memconfig>fr_fcfs_bankwise.xml</memconfig>
<memconfig>fr_fcfs_unaware.xml</memconfig>
</memconfigs>
<trace-setups>
<trace-setup id="1">
<device >chstone-aes_32.stl</device>
<device >chstone-motion_32.stl</device>
</trace-setup>
<trace-setup id="2">
<device >chstone-motion_32.stl</device>
<device >chstone-jpeg_32.stl</device>
</trace-setup>
<trace-setup id="3">
<device >mediabench-gsmdecode_32.stl</device>
</trace-setup>
<trace-setup id="4">
<device >mediabench-fractal_32.stl</device>
</trace-setup>
<trace-setup id="5">
<device >mediabench-epic_32.stl</device>
</trace-setup>
<trace-setup id="6">
<device >mediabench-mpeg2encode_32.stl</device>
</trace-setup>
<trace-setup id="7">
<device >mediabench-h263encode_32.stl</device>
</trace-setup>
</trace-setups>
</simulation>

33
dram/resources/simulations/first.xml
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@@ -1,33 +0,0 @@
<simulation id = "firstchstone">
<memspec>DDR4.xml</memspec>
<!-- <addressmapping>am_lowPara.xml</addressmapping> -->
<addressmapping>am_highPara.xml</addressmapping>
<!-- <addressmapping>am_lowHits.xml</addressmapping> -->
<!-- <addressmapping>am_highHits.xml</addressmapping> -->
<memconfigs>
<memconfig>fr_fcfs.xml</memconfig>
<memconfig>fr_fcfs_unaware.xml</memconfig>
<!-- <memconfig>fifo.xml</memconfig>
--> <!-- <memconfig>par_bs.xml</memconfig> -->
<!-- <memconfig>fr_fcfs_bankwise.xml</memconfig>
--> </memconfigs>
<trace-setups>
<trace-setup id="1">
<device >chstone-sha_32.stl</device>
<device >chstone-aes_32.stl</device>
</trace-setup>
<trace-setup id="2">
<device >mediabench-h263decode_32.stl</device>
<device >mediabench-g721encode_32.stl</device>
</trace-setup>
<trace-setup id="3">
<device >mediabench-fractal_32.stl</device>
<device >chstone-aes_32.stl</device>
</trace-setup>
<trace-setup id="4">
<device >mediabench-h263decode_32.stl</device>
<device >chstone-aes_32.stl</device>
</trace-setup>
</trace-setups>
</simulation>

37
dram/resources/simulations/sim-batch.xml
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@@ -1,28 +1,23 @@
<simulation id="wideio">
<memspec>JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml</memspec>
<addressmapping>am_wideioFourBanks.xml</addressmapping>
<simulation id = "simbatch">
<memspec>DDR4.xml</memspec>
<!-- <addressmapping>am_highHits.xml</addressmapping>
<addressmapping>am_highPara.xml</addressmapping> -->
<!-- <addressmapping>am_lowPara.xml</addressmapping>
-->
<addressmapping>am_lowHits.xml</addressmapping>
<addressmapping>am_lowPara.xml</addressmapping>
<memconfigs>
<memconfig>fr_fcfs.xml</memconfig>
<memconfig>fr_fcfs_bankwise.xml</memconfig>
<memconfig>fifo.xml</memconfig>
</memconfigs>
<trace-setups>
<trace-setup id="1">
<device >chstone-sha_32.stl</device>
<device >chstone-aes_32.stl</device>
<trace-setup id="13">
<device >mediabench-fractal_32.stl</device>
</trace-setup>
</trace-setups>
</simulation>
<!--
<simulation id="dd4">
<memspec>MICRON_4Gb_DDR4-1866_8bit_A.xml</memspec>
<addressmapping>am_ddr4.xml</addressmapping>
<memconfigs>
<memconfig>fr_fcfs.xml</memconfig>
<memconfig>fr_fcfs_bankwise.xml</memconfig>
</memconfigs>
<trace-setups>
<trace-setup id="1">
<device >mediabench-c-ray-1.1_32.stl</device>
</trace-setup>
</trace-setups>
</simulation> -->

4
dram/src/core/scheduling/checker/RefreshChecker.cpp
View File

@@ -35,6 +35,10 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXP);
}
else if (lastCommandOnBank.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXSR);
}
else if (lastCommandOnBank.getCommand() == Command::AutoRefresh)
{
}

2
dram/src/simulation/SimulationManager.cpp
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@@ -68,7 +68,7 @@ void SimulationManager::runSimulations()
for (auto& traceSetup : batch.traceSetups)
{
runSimulation(
exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + addressmappig + "-" +
exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + memspec + "-" +
memconfig + ".tdb", dramSetup, traceSetup.second);
}
}