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addressmappings tested

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This commit is contained in:
robert
2014-04-21 09:55:37 +02:00
parent dc456385cc
commit 9b5ed54138
5 changed files with 7 additions and 7 deletions
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2
dram/resources/configs/amconfigs/am_highHits.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- highest hit rate -->
<!-- should have highest hit rate, since a (row, bank) bank pair changes infrequently -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />

3
dram/resources/configs/amconfigs/am_highPara.xml
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@@ -1,5 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- highest bank parallelism - high hits -->
<!-- should have high bank parallelism with good row hit rate, since bank bits have the
highest entropy and row bits the lowest -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />

3
dram/resources/configs/amconfigs/am_lowHits.xml
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@@ -1,7 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- highest bank parallism - low hits
-->
<!-- should have high bank parallelism with a low hit rate -->
<dramconfig>
<addressmap length="32">
<colum from="24" to="31" />

2
dram/resources/configs/amconfigs/am_lowPara.xml
View File

@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- low bank parallelism - high hits -->
<!-- should have low bank parallelism and a high hit rate -->
<dramconfig>
<addressmap length="32">
<bank from="30" to="31" />

4
dram/src/simulation/SimulationManager.cpp
View File

@@ -68,8 +68,8 @@ void SimulationManager::runSimulations()
for (auto& traceSetup : batch.traceSetups)
{
runSimulation(
exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + memconfig + "-" + memspec + "-" +
addressmappig + ".tdb", dramSetup, traceSetup.second);
exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + addressmappig + "-" +
memconfig + ".tdb", dramSetup, traceSetup.second);
}
}
}