refresh manager changed vector to map

2014-04-10 10:22:16 +02:00
parent 4ef7c7ad78
commit 3ba934b45f
13 changed files with 64 additions and 47 deletions
--- a/dram/.cproject
+++ b/dram/.cproject
@@ -19,7 +19,7 @@
 							<builder autoBuildTarget="all" buildPath="${workspace_loc:/dram}/build-simulation" cleanBuildTarget="clean" enableAutoBuild="false" id="org.eclipse.cdt.build.core.internal.builder.1698165306" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.internal.builder"/>
 							<tool id="cdt.managedbuild.tool.gnu.archiver.base.1509734096" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
 							<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.789860529" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
-								<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.2041174282" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
+								<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.2041174282" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.most" valueType="enumerated"/>
 								<option id="gnu.cpp.compiler.exe.debug.option.debugging.level.2092267417" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
 								<option id="gnu.cpp.compiler.option.include.paths.1823643375" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
 									<listOptionValue builtIn="false" value="/opt/systemc-2.3.0/include"/>
@@ -96,24 +96,24 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="unit_test"/>
 		<configuration configurationName="Release">
 			<resource resourceType="PROJECT" workspacePath="/DRAM-Model"/>
 		</configuration>
+		<configuration configurationName="unit_test"/>
 		<configuration configurationName="platformArchitect">
 			<resource resourceType="PROJECT" workspacePath="/DRAM"/>
 		</configuration>
 		<configuration configurationName="build-simulation"/>
 		<configuration configurationName="testing"/>
-		<configuration configurationName="simulation-build">
-			<resource resourceType="PROJECT" workspacePath="/dram"/>
-		</configuration>
 		<configuration configurationName="Debug">
 			<resource resourceType="PROJECT" workspacePath="/DRAM-Model"/>
 		</configuration>
+		<configuration configurationName="simulation-build">
+			<resource resourceType="PROJECT" workspacePath="/dram"/>
+		</configuration>
 		<configuration configurationName="standalone"/>
-		<configuration configurationName="simulation"/>
 		<configuration configurationName="build-testing"/>
+		<configuration configurationName="simulation"/>
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings">
 		<doc-comment-owner id="org.eclipse.cdt.internal.ui.text.doctools.NullDocCommentOwner">
--- a/dram/.gitignore
+++ b/dram/.gitignore
@@ -1,4 +1,5 @@
 /build-simulation
 *.tdb
 *.tdb-journal
-*.out
+*.out
+*.txt
--- a/dram/clean
+++ b/dram/clean
@@ -1,7 +1,7 @@
 echo "Cleaning Up:"
 echo "  -->remove *.txt"
 rm *.txt
-echo "  -->remove *.tdb-journal"
+echo "  -->remove *.tdb"
 rm *.tdb
 echo "  -->remove *.tdb-journal"
 rm *.tdb-journal
--- a/dram/resources/configs/memconfigs/memconfig.xml
+++ b/dram/resources/configs/memconfigs/memconfig.xml
@@ -3,7 +3,7 @@
    <parameter id="bankwiseLogic" type="bool" value="0" />
    <parameter id="openPagePolicy" type="bool" value="1" />
    <parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
-    <parameter id="refreshAwareScheduling" type="bool" value="0" />
+    <parameter id="refreshAwareScheduling" type="bool" value="1" />
    <parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
    <parameter id="scheduler" type="string" value="FR_FCFS" />
    <parameter id="capsize" type="uint" value="5" />
--- a/dram/resources/configs/memspecs/MatzesWideIO.xml
+++ b/dram/resources/configs/memspecs/MatzesWideIO.xml
@@ -28,7 +28,7 @@
      <!--<parameter id="XPDLL" type="uint" value="2" />-->
      <parameter id="XS" type="uint" value="2" /><!--tRFC+2clk-->
      <!--<parameter id="XSDLL" type="uint" value="20" />-->
-      <parameter id="REFI" type="uint" value="1300" />
+      <parameter id="REFI" type="uint" value="300" />
      <!--<parameter id="CL" type="uint" value="3" />-->
      <parameter id="TAW" type="uint" value="10" />
      <parameter id="RRD" type="uint" value="2" />
--- a/dram/src/core/configuration/MemSpecLoader.cpp
+++ b/dram/src/core/configuration/MemSpecLoader.cpp
@@ -99,8 +99,8 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
 	config.Timings.refreshTimings.clear();
 	for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
 	{
-		config.Timings.refreshTimings.push_back(
-				RefreshTiming(config.Timings.tRFC, config.Timings.tREFI));
+		config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC,
+				config.Timings.tREFI);
 	}
 }

@@ -148,8 +148,8 @@ void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec)
 	config.Timings.refreshTimings.clear();
 	for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
 	{
-		config.Timings.refreshTimings.push_back(
-				RefreshTiming(config.Timings.tRFC, config.Timings.tREFI));
+		config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC,
+				config.Timings.tREFI);
 	}

 }
--- a/dram/src/core/configuration/TimingConfiguration.h
+++ b/dram/src/core/configuration/TimingConfiguration.h
@@ -10,12 +10,14 @@

 #include <systemc.h>
 #include "../utils/Utils.h"
+#include <map>

 namespace core{

 struct RefreshTiming
 {
-	RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
+	RefreshTiming() {};
+	RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {};
 	sc_time tRFC;
 	sc_time tREFI;
 };
@@ -51,7 +53,7 @@ struct TimingConfiguration
 	sc_time tRFC;		//min ref->act delay
 	sc_time tREFI;		//auto refresh must be issued at an average periodic interval tREFI

-	std::vector<RefreshTiming> refreshTimings;
+	std::map<Bank, RefreshTiming> refreshTimings;//ensure that map is populated completely in memspecloader

 	//act and read/write commands remain for this timespan in history
 	sc_time tActHistory(){return tNAW;}
--- a/dram/src/core/refresh/RefreshManager.cpp
+++ b/dram/src/core/refresh/RefreshManager.cpp
@@ -13,8 +13,8 @@ using namespace tlm;
 namespace core {

 RefreshManager::RefreshManager(ControllerCore& controller) :
-		controller(controller), timing(controller.config.Timings.refreshTimings.at(0)), nextPlannedRefresh(
-				SC_ZERO_TIME), refreshPayloads(controller.config.NumberOfBanks)
+		controller(controller), timing(controller.config.Timings.refreshTimings[Bank(0)]), nextPlannedRefresh(
+				SC_ZERO_TIME)
 {
 	setupTransactions();
 	planNextRefresh();
@@ -34,18 +34,19 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time
 	sc_assert(!isInvalidated(payload, time));

 	ScheduledCommand nextRefresh(Command::AutoRefresh, time, timing.tRFC,
-			DramExtension::getExtension(refreshPayloads.at(0)));
+			DramExtension::getExtension(refreshPayloads[Bank(0)]));

 	if (!controller.state.bankStates.allRowBuffersAreClosed())
 	{
 		ScheduledCommand precharge(Command::PrechargeAll, time, controller.config.Timings.tRP,
-				DramExtension::getExtension(refreshPayloads.at(0)));
+				DramExtension::getExtension(refreshPayloads[Bank(0)]));

 		controller.getCommandChecker(Command::PrechargeAll).delayToSatisfyConstraints(precharge);
 		nextRefresh.setStart(precharge.getEnd());

-		for (tlm::tlm_generic_payload& payload : refreshPayloads)
+		for (Bank bank : controller.getBanks())
 		{
+			tlm_generic_payload& payload = refreshPayloads[bank];
 			ScheduledCommand prechargeToSend(Command::PrechargeAll, precharge.getStart(),
 					controller.config.Timings.tRP, DramExtension::getExtension(payload));
 			controller.state.change(prechargeToSend);
@@ -57,8 +58,9 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time
 		//no precharge all
 		controller.state.bus.moveCommandToNextFreeSlot(nextRefresh);
 	}
-	for (tlm::tlm_generic_payload& payload : refreshPayloads)
+	for (Bank bank : controller.getBanks())
 	{
+		tlm_generic_payload& payload = refreshPayloads[bank];
 		Row currentrow = DramExtension::getExtension(payload).getRow();
 		DramExtension::getExtension(payload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks));
 		ScheduledCommand refreshToSend(Command::AutoRefresh, nextRefresh.getStart(), timing.tRFC,
@@ -75,7 +77,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time
 void RefreshManager::planNextRefresh()
 {
 	nextPlannedRefresh += timing.tREFI;
-	controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads.at(0));
+	controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads[Bank(0)]);
 }

 void RefreshManager::reInitialize(tlm::tlm_generic_payload& payload, sc_time time)
@@ -93,7 +95,7 @@ void RefreshManager::setupTransactions()
 {
 	for (Bank bank : controller.getBanks())
 	{
-		setUpDummy(refreshPayloads.at(bank.ID()), bank);
+		setUpDummy(refreshPayloads[bank], bank);
 	}
 }

--- a/dram/src/core/refresh/RefreshManager.h
+++ b/dram/src/core/refresh/RefreshManager.h
@@ -32,7 +32,7 @@ private:
 	ControllerCore& controller;
 	RefreshTiming& timing;
 	sc_time nextPlannedRefresh;
-	std::vector<tlm::tlm_generic_payload> refreshPayloads;
+	std::map<Bank, tlm::tlm_generic_payload> refreshPayloads;

 	void planNextRefresh();
 	void setupTransactions();
--- a/dram/src/core/refresh/RefreshManagerBankwise.cpp
+++ b/dram/src/core/refresh/RefreshManagerBankwise.cpp
@@ -20,35 +20,35 @@ RefreshManagerBankwise::RefreshManagerBankwise(ControllerCore& controller) :

 	for (Bank bank : controller.getBanks())
 	{
-		refreshManagerForBanks.push_back(new RefreshManagerForBank(controller, bank));
+		refreshManagerForBanks[bank] = new RefreshManagerForBank(controller, bank);
 	}
 }

 RefreshManagerBankwise::~RefreshManagerBankwise()
 {
-	for (RefreshManagerForBank* manager : refreshManagerForBanks)
+	for (Bank bank : controller.getBanks())
 	{
-		delete manager;
+		delete refreshManagerForBanks[bank];
 	}
 }

 bool RefreshManagerBankwise::hasCollision(const CommandSchedule& schedule)
 {
-	RefreshManagerForBank& manager = *refreshManagerForBanks.at(schedule.getBank().ID());
+	RefreshManagerForBank& manager = *refreshManagerForBanks[schedule.getBank()];
 	return manager.hasCollision(schedule);
 }

 void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time)
 {
 	sc_assert(!isInvalidated(payload, time));
-	RefreshManagerForBank& manager = *refreshManagerForBanks.at(
-			DramExtension::getExtension(payload).getBank().ID());
+	RefreshManagerForBank& manager =
+			*refreshManagerForBanks[DramExtension::getExtension(payload).getBank()];
 	manager.scheduleRefresh(time);
 }

 RefreshManagerBankwise::RefreshManagerForBank::RefreshManagerForBank(ControllerCore& controller,
 		Bank bank) :
-		controller(controller), timing(controller.config.Timings.refreshTimings.at(bank.ID())), bank(
+		controller(controller), timing(controller.config.Timings.refreshTimings[bank]), bank(
 				bank), nextPlannedRefresh(SC_ZERO_TIME)
 {
 	setupTransaction();
@@ -89,7 +89,8 @@ void RefreshManagerBankwise::RefreshManagerForBank::scheduleRefresh(sc_time time
 	controller.state.bus.moveCommandToNextFreeSlot(nextRefresh);
 	controller.state.change(nextRefresh);
 	Row currentrow = DramExtension::getExtension(refreshPayload).getRow();
-	DramExtension::getExtension(refreshPayload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks));
+	DramExtension::getExtension(refreshPayload).setRow(
+			Row((currentrow.ID() + 1) % Configuration::getInstance().NumberOfBanks));
 	controller.wrapper.send(nextRefresh, refreshPayload);

 	planNextRefresh();
@@ -121,14 +122,14 @@ void RefreshManagerBankwise::RefreshManagerForBank::setupTransaction()
 void RefreshManagerBankwise::reInitialize(tlm::tlm_generic_payload& payload, sc_time time)
 {

-	refreshManagerForBanks.at(DramExtension::getExtension(payload).getBank().ID())->reInitialize(
-			payload, time);
+	refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]->reInitialize(payload,
+			time);
 }

 bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload& payload, sc_time time)
 {
-	RefreshManagerForBank& manager = *refreshManagerForBanks.at(
-			DramExtension::getExtension(payload).getBank().ID());
+	RefreshManagerForBank& manager =
+			*refreshManagerForBanks[DramExtension::getExtension(payload).getBank()];
 	return manager.isInvalidated(time);
 }

--- a/dram/src/core/refresh/RefreshManagerBankwise.h
+++ b/dram/src/core/refresh/RefreshManagerBankwise.h
@@ -57,7 +57,7 @@ private:
 	};

 	ControllerCore& controller;
-	std::vector<RefreshManagerForBank*> refreshManagerForBanks;
+	std::map<Bank, RefreshManagerForBank*> refreshManagerForBanks;


 };
--- a/dram/src/simulation/SimulationManager.cpp
+++ b/dram/src/simulation/SimulationManager.cpp
@@ -17,8 +17,8 @@ using namespace std;

 namespace simulation {

-Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
-		std::vector<Device> devices, bool silent) :
+Simulation::Simulation(sc_module_name name, string pathToResources, string traceName,
+		DramSetup setup, std::vector<Device> devices, bool silent) :
 		traceName(traceName)

 {
@@ -36,9 +36,9 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace
 	controller = new Controller<>("controller");

 	//setup devices
-	for(auto& d : devices)
+	for (auto& d : devices)
 	{
-		if(d.burstLength == 0)
+		if (d.burstLength == 0)
 			d.burstLength = 8;
 	}

@@ -67,6 +67,11 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace
 	auto& dbg = DebugManager::getInstance();
 	dbg.addToWhiteList(whiteList);
 	dbg.setDebugFile(traceName + ".txt");
+	if (silent)
+	{
+		dbg.writeToConsole = false;
+		dbg.writeToFile = false;
+	}
 }

 Simulation::~Simulation()
@@ -81,9 +86,9 @@ Simulation::~Simulation()
 void Simulation::startSimulation()
 {

-
 	clock_t begin = clock();

+	cout<<"Starting simulation"<<endl;
 	DebugManager::getInstance().printDebugMessage(name(), "Starting simulation");
 	player1->start();
 	player2->start();
@@ -93,6 +98,7 @@ void Simulation::startSimulation()
 	double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
 	DebugManager::getInstance().printDebugMessage(name(),
 			"Simulation took " + to_string(elapsed_secs) + " seconds");
+	cout<<"took "<<(elapsed_secs)<<endl;
 }

 void Simulation::tracePlayerFinishedCallback(string name)
--- a/dram/src/simulation/main.cpp
+++ b/dram/src/simulation/main.cpp
@@ -40,7 +40,7 @@ bool runSimulation(string resources, string traceName, DramSetup setup, vector<D
 	int status = 0;
 	if (pid == 0)
 	{
-		Simulation simulation("sim", resources, traceName, setup, devices);
+		Simulation simulation("sim", resources, traceName, setup, devices, true);
 		simulation.startSimulation();
 		return true;
 	}
@@ -80,8 +80,8 @@ int sc_main(int argc, char **argv)

 		DramSetup setup;
 		setup.memconfig = "memconfig.xml";
-		//setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
 		setup.memspec = "MatzesWideIO.xml";
+		//setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";

 		DramSetup setup2;
 		setup2.memconfig = "memconfig.xml";
@@ -91,9 +91,14 @@ int sc_main(int argc, char **argv)
 	vector<pair<string, string>> tracePairs;
 	tracePairs.push_back(pair<string, string>("trace.stl", "empty.stl"));
 	tracePairs.push_back(pair<string, string>("trace2.stl", "empty.stl"));
-	//batchTraces(setup, tracePairs);
-batchSetups(tracePairs[0], {setup, setup2});

+	//batchTraces(setup, tracePairs);
+	//batchSetups(tracePairs[0], {setup});
+
+	string traceName = "mediabench-h263encode_32.tdb";
+
+	if(runSimulation(resources, traceName, setup, { Device("mediabench-h263encode_32.stl"), Device("empty.stl") }))
+		startTraceAnalyzer(traceName);
 	return 0;
 }