diff --git a/dram/.cproject b/dram/.cproject index 362fbe05..bb76d239 100644 --- a/dram/.cproject +++ b/dram/.cproject @@ -19,7 +19,7 @@ - + @@ -96,24 +96,24 @@ - + - - - + + + - + diff --git a/dram/.gitignore b/dram/.gitignore index c1bea3e6..3f6fb6f0 100644 --- a/dram/.gitignore +++ b/dram/.gitignore @@ -1,4 +1,5 @@ /build-simulation *.tdb *.tdb-journal -*.out \ No newline at end of file +*.out +*.txt \ No newline at end of file diff --git a/dram/clean b/dram/clean index 66fe384d..0e2d6764 100755 --- a/dram/clean +++ b/dram/clean @@ -1,7 +1,7 @@ echo "Cleaning Up:" echo " -->remove *.txt" rm *.txt -echo " -->remove *.tdb-journal" +echo " -->remove *.tdb" rm *.tdb echo " -->remove *.tdb-journal" rm *.tdb-journal \ No newline at end of file diff --git a/dram/resources/configs/memconfigs/memconfig.xml b/dram/resources/configs/memconfigs/memconfig.xml index 1da98872..ad54f1e4 100644 --- a/dram/resources/configs/memconfigs/memconfig.xml +++ b/dram/resources/configs/memconfigs/memconfig.xml @@ -3,7 +3,7 @@ - + diff --git a/dram/resources/configs/memspecs/MatzesWideIO.xml b/dram/resources/configs/memspecs/MatzesWideIO.xml index 57599053..1fde1e2c 100644 --- a/dram/resources/configs/memspecs/MatzesWideIO.xml +++ b/dram/resources/configs/memspecs/MatzesWideIO.xml @@ -28,7 +28,7 @@ - + diff --git a/dram/src/core/configuration/MemSpecLoader.cpp b/dram/src/core/configuration/MemSpecLoader.cpp index effa1eef..3f931833 100644 --- a/dram/src/core/configuration/MemSpecLoader.cpp +++ b/dram/src/core/configuration/MemSpecLoader.cpp @@ -99,8 +99,8 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.Timings.refreshTimings.clear(); for (unsigned int i = 0; i < config.NumberOfBanks; ++i) { - config.Timings.refreshTimings.push_back( - RefreshTiming(config.Timings.tRFC, config.Timings.tREFI)); + config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, + config.Timings.tREFI); } } @@ -148,8 +148,8 @@ void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec) config.Timings.refreshTimings.clear(); for (unsigned int i = 0; i < config.NumberOfBanks; ++i) { - config.Timings.refreshTimings.push_back( - RefreshTiming(config.Timings.tRFC, config.Timings.tREFI)); + config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, + config.Timings.tREFI); } } diff --git a/dram/src/core/configuration/TimingConfiguration.h b/dram/src/core/configuration/TimingConfiguration.h index 79ea3574..61ab2571 100644 --- a/dram/src/core/configuration/TimingConfiguration.h +++ b/dram/src/core/configuration/TimingConfiguration.h @@ -10,12 +10,14 @@ #include #include "../utils/Utils.h" +#include namespace core{ struct RefreshTiming { - RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {} + RefreshTiming() {}; + RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}; sc_time tRFC; sc_time tREFI; }; @@ -51,7 +53,7 @@ struct TimingConfiguration sc_time tRFC; //min ref->act delay sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI - std::vector refreshTimings; + std::map refreshTimings;//ensure that map is populated completely in memspecloader //act and read/write commands remain for this timespan in history sc_time tActHistory(){return tNAW;} diff --git a/dram/src/core/refresh/RefreshManager.cpp b/dram/src/core/refresh/RefreshManager.cpp index d421d257..7e784289 100644 --- a/dram/src/core/refresh/RefreshManager.cpp +++ b/dram/src/core/refresh/RefreshManager.cpp @@ -13,8 +13,8 @@ using namespace tlm; namespace core { RefreshManager::RefreshManager(ControllerCore& controller) : - controller(controller), timing(controller.config.Timings.refreshTimings.at(0)), nextPlannedRefresh( - SC_ZERO_TIME), refreshPayloads(controller.config.NumberOfBanks) + controller(controller), timing(controller.config.Timings.refreshTimings[Bank(0)]), nextPlannedRefresh( + SC_ZERO_TIME) { setupTransactions(); planNextRefresh(); @@ -34,18 +34,19 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time sc_assert(!isInvalidated(payload, time)); ScheduledCommand nextRefresh(Command::AutoRefresh, time, timing.tRFC, - DramExtension::getExtension(refreshPayloads.at(0))); + DramExtension::getExtension(refreshPayloads[Bank(0)])); if (!controller.state.bankStates.allRowBuffersAreClosed()) { ScheduledCommand precharge(Command::PrechargeAll, time, controller.config.Timings.tRP, - DramExtension::getExtension(refreshPayloads.at(0))); + DramExtension::getExtension(refreshPayloads[Bank(0)])); controller.getCommandChecker(Command::PrechargeAll).delayToSatisfyConstraints(precharge); nextRefresh.setStart(precharge.getEnd()); - for (tlm::tlm_generic_payload& payload : refreshPayloads) + for (Bank bank : controller.getBanks()) { + tlm_generic_payload& payload = refreshPayloads[bank]; ScheduledCommand prechargeToSend(Command::PrechargeAll, precharge.getStart(), controller.config.Timings.tRP, DramExtension::getExtension(payload)); controller.state.change(prechargeToSend); @@ -57,8 +58,9 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time //no precharge all controller.state.bus.moveCommandToNextFreeSlot(nextRefresh); } - for (tlm::tlm_generic_payload& payload : refreshPayloads) + for (Bank bank : controller.getBanks()) { + tlm_generic_payload& payload = refreshPayloads[bank]; Row currentrow = DramExtension::getExtension(payload).getRow(); DramExtension::getExtension(payload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks)); ScheduledCommand refreshToSend(Command::AutoRefresh, nextRefresh.getStart(), timing.tRFC, @@ -75,7 +77,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time void RefreshManager::planNextRefresh() { nextPlannedRefresh += timing.tREFI; - controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads.at(0)); + controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads[Bank(0)]); } void RefreshManager::reInitialize(tlm::tlm_generic_payload& payload, sc_time time) @@ -93,7 +95,7 @@ void RefreshManager::setupTransactions() { for (Bank bank : controller.getBanks()) { - setUpDummy(refreshPayloads.at(bank.ID()), bank); + setUpDummy(refreshPayloads[bank], bank); } } diff --git a/dram/src/core/refresh/RefreshManager.h b/dram/src/core/refresh/RefreshManager.h index e7896da2..46d5a33f 100644 --- a/dram/src/core/refresh/RefreshManager.h +++ b/dram/src/core/refresh/RefreshManager.h @@ -32,7 +32,7 @@ private: ControllerCore& controller; RefreshTiming& timing; sc_time nextPlannedRefresh; - std::vector refreshPayloads; + std::map refreshPayloads; void planNextRefresh(); void setupTransactions(); diff --git a/dram/src/core/refresh/RefreshManagerBankwise.cpp b/dram/src/core/refresh/RefreshManagerBankwise.cpp index 10b99668..cde123b7 100644 --- a/dram/src/core/refresh/RefreshManagerBankwise.cpp +++ b/dram/src/core/refresh/RefreshManagerBankwise.cpp @@ -20,35 +20,35 @@ RefreshManagerBankwise::RefreshManagerBankwise(ControllerCore& controller) : for (Bank bank : controller.getBanks()) { - refreshManagerForBanks.push_back(new RefreshManagerForBank(controller, bank)); + refreshManagerForBanks[bank] = new RefreshManagerForBank(controller, bank); } } RefreshManagerBankwise::~RefreshManagerBankwise() { - for (RefreshManagerForBank* manager : refreshManagerForBanks) + for (Bank bank : controller.getBanks()) { - delete manager; + delete refreshManagerForBanks[bank]; } } bool RefreshManagerBankwise::hasCollision(const CommandSchedule& schedule) { - RefreshManagerForBank& manager = *refreshManagerForBanks.at(schedule.getBank().ID()); + RefreshManagerForBank& manager = *refreshManagerForBanks[schedule.getBank()]; return manager.hasCollision(schedule); } void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time) { sc_assert(!isInvalidated(payload, time)); - RefreshManagerForBank& manager = *refreshManagerForBanks.at( - DramExtension::getExtension(payload).getBank().ID()); + RefreshManagerForBank& manager = + *refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]; manager.scheduleRefresh(time); } RefreshManagerBankwise::RefreshManagerForBank::RefreshManagerForBank(ControllerCore& controller, Bank bank) : - controller(controller), timing(controller.config.Timings.refreshTimings.at(bank.ID())), bank( + controller(controller), timing(controller.config.Timings.refreshTimings[bank]), bank( bank), nextPlannedRefresh(SC_ZERO_TIME) { setupTransaction(); @@ -89,7 +89,8 @@ void RefreshManagerBankwise::RefreshManagerForBank::scheduleRefresh(sc_time time controller.state.bus.moveCommandToNextFreeSlot(nextRefresh); controller.state.change(nextRefresh); Row currentrow = DramExtension::getExtension(refreshPayload).getRow(); - DramExtension::getExtension(refreshPayload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks)); + DramExtension::getExtension(refreshPayload).setRow( + Row((currentrow.ID() + 1) % Configuration::getInstance().NumberOfBanks)); controller.wrapper.send(nextRefresh, refreshPayload); planNextRefresh(); @@ -121,14 +122,14 @@ void RefreshManagerBankwise::RefreshManagerForBank::setupTransaction() void RefreshManagerBankwise::reInitialize(tlm::tlm_generic_payload& payload, sc_time time) { - refreshManagerForBanks.at(DramExtension::getExtension(payload).getBank().ID())->reInitialize( - payload, time); + refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]->reInitialize(payload, + time); } bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload& payload, sc_time time) { - RefreshManagerForBank& manager = *refreshManagerForBanks.at( - DramExtension::getExtension(payload).getBank().ID()); + RefreshManagerForBank& manager = + *refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]; return manager.isInvalidated(time); } diff --git a/dram/src/core/refresh/RefreshManagerBankwise.h b/dram/src/core/refresh/RefreshManagerBankwise.h index 48b5f29f..34eac9ed 100644 --- a/dram/src/core/refresh/RefreshManagerBankwise.h +++ b/dram/src/core/refresh/RefreshManagerBankwise.h @@ -57,7 +57,7 @@ private: }; ControllerCore& controller; - std::vector refreshManagerForBanks; + std::map refreshManagerForBanks; }; diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index 230c1c13..6e44f8c9 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -17,8 +17,8 @@ using namespace std; namespace simulation { -Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup, - std::vector devices, bool silent) : +Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, + DramSetup setup, std::vector devices, bool silent) : traceName(traceName) { @@ -36,9 +36,9 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace controller = new Controller<>("controller"); //setup devices - for(auto& d : devices) + for (auto& d : devices) { - if(d.burstLength == 0) + if (d.burstLength == 0) d.burstLength = 8; } @@ -67,6 +67,11 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace auto& dbg = DebugManager::getInstance(); dbg.addToWhiteList(whiteList); dbg.setDebugFile(traceName + ".txt"); + if (silent) + { + dbg.writeToConsole = false; + dbg.writeToFile = false; + } } Simulation::~Simulation() @@ -81,9 +86,9 @@ Simulation::~Simulation() void Simulation::startSimulation() { - clock_t begin = clock(); + cout<<"Starting simulation"<start(); player2->start(); @@ -93,6 +98,7 @@ void Simulation::startSimulation() double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC; DebugManager::getInstance().printDebugMessage(name(), "Simulation took " + to_string(elapsed_secs) + " seconds"); + cout<<"took "<<(elapsed_secs)<> tracePairs; tracePairs.push_back(pair("trace.stl", "empty.stl")); tracePairs.push_back(pair("trace2.stl", "empty.stl")); - //batchTraces(setup, tracePairs); -batchSetups(tracePairs[0], {setup, setup2}); + //batchTraces(setup, tracePairs); + //batchSetups(tracePairs[0], {setup}); + + string traceName = "mediabench-h263encode_32.tdb"; + + if(runSimulation(resources, traceName, setup, { Device("mediabench-h263encode_32.stl"), Device("empty.stl") })) + startTraceAnalyzer(traceName); return 0; }