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relocated getBankgroup function

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This commit is contained in:
robert
2014-04-11 12:42:49 +02:00
parent 569949cfa6
commit 8bc3293dcb
18 changed files with 116 additions and 112 deletions
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2
dram/.settings/language.settings.xml
View File

@@ -4,7 +4,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1219188953996516293" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-60060699001507781" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

2
dram/resources/configs/memconfigs/memconfig.xml
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@@ -1,6 +1,6 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="bankwiseLogic" type="bool" value="1" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />

65
dram/resources/configs/memspecs/MatzesWideIO-short.xml Normal file
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@@ -0,0 +1,65 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-200_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<!-- <parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />-->
<parameter id="nbrOfRows" type="uint" value="2048" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="166" />
<parameter id="RC" type="uint" value="9" /><!--tRP+tRAS-->
<parameter id="RCD" type="uint" value="3" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="3" />
<parameter id="RFC" type="uint" value="22" />
<parameter id="RAS" type="uint" value="6" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<!--<parameter id="DQSCK" type="uint" value="1" />
<parameter id="RTP" type="uint" value="4" />-->
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<!--<parameter id="XPDLL" type="uint" value="2" />-->
<parameter id="XS" type="uint" value="2" /><!--tRFC+2clk-->
<!--<parameter id="XSDLL" type="uint" value="20" />-->
<parameter id="REFI" type="uint" value="300" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<!-- <parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />-->
</mempowerspec>
</memspec>

5
dram/resources/configs/memspecs/MatzesWideIO.xml
View File

@@ -26,10 +26,9 @@
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<!--<parameter id="XPDLL" type="uint" value="2" />-->
<parameter id="XS" type="uint" value="2" /><!--tRFC+2clk-->
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<!--<parameter id="XSDLL" type="uint" value="20" />-->
<parameter id="REFI" type="uint" value="300" /> <!-- 1300 -->
<!--<parameter id="CL" type="uint" value="3" />-->
<parameter id="REFI" type="uint" value="1300" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />

2
dram/resources/scripts/tests.py
View File

@@ -190,7 +190,7 @@ def phases_on_bank_are_sequential(connection):
return TestSuceeded()
@test
#@test
def phase_lengths_are_correct(connection):
query = """SELECT phases.ID,PhaseName, PhaseEnd-PhaseBegin,Burstlength FROM Phases INNER JOIN transactions ON transactions.ID = phases.transact """
cursor = connection.cursor()

19
dram/src/common/dramExtension.cpp
View File

@@ -1,5 +1,7 @@
#include "dramExtension.h"
#include <assert.h>
#include "../core/configuration/Configuration.h"
#include "map"
using namespace tlm;
@@ -45,6 +47,22 @@ bool operator !=(const Channel& lhs, const Channel& rhs)
return !(lhs == rhs);
}
BankGroup Bank::getBankGroup()
{
static std::map<Bank, BankGroup> bankgroups;
if (bankgroups.size() == 0)
{
SC_ASSERT_(config.NumberOfBanks % config.NumberOfBankGroups == 0, "Number of banks must be a multiple of number of bankgroups");
for (unsigned int bank = 0; bank < core::Configuration::getInstance().NumberOfBanks; bank++)
{
unsigned int group = bank % core::Configuration::getInstance().NumberOfBankGroups;
bankgroups.insert(std::pair<Bank, BankGroup>(Bank(bank), BankGroup(group)));
}
}
return bankgroups.at(*this);
}
bool operator ==(const Bank& lhs, const Bank& rhs)
{
return lhs.ID() == rhs.ID();
@@ -95,3 +113,4 @@ bool operator !=(const Column& lhs, const Column& rhs)
return !(lhs == rhs);
}

8
dram/src/common/dramExtension.h
View File

@@ -68,6 +68,14 @@ public:
{
return id;
}
unsigned int getStartAddress()
{
return 0;
}
BankGroup getBankGroup();
private:
unsigned int id;
};

1
dram/src/core/ControllerState.h
View File

@@ -10,7 +10,6 @@
#include <systemc.h>
#include "BankStates.h"
#include "utils/RingBuffer.h"
#include "scheduling/ScheduledCommand.h"
#include "Slots.h"
#include "configuration/Configuration.h"

2
dram/src/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -76,7 +76,7 @@ bool ActivateChecker::satsfies_activateToActivate_differentBank(ScheduledCommand
{
sc_time time = act.first;
sc_time tRRD =
(command.getBankGroup() == getBankGroup(act.second)) ?
(command.getBankGroup() == act.second.getBankGroup()) ?
config.Timings.tRRD_L : config.Timings.tRRD_S;
if ((time < command.getStart() && command.getStart() - time < tRRD)

1
dram/src/core/scheduling/checker/ActivateChecker.h
View File

@@ -11,7 +11,6 @@
#include <map>
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../utils/RingBuffer.h"
#include "../../ControllerState.h"
namespace core {

4
dram/src/core/scheduling/checker/WriteChecker.cpp
View File

@@ -84,7 +84,7 @@ bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand& write,
bool collision = write.collidesOnDataStrobe(strobeCommand);
sc_time tCCD =
(getBankGroup(write.getBank()) == getBankGroup(strobeCommand.getBank())) ?
(write.getBank().getBankGroup() == strobeCommand.getBank().getBankGroup()) ?
config.Timings.tCCD_L : config.Timings.tCCD_S;
bool casToCas = (getDistance(write.getStart(), strobeCommand.getStart()) < tCCD) ? true : false;
@@ -97,7 +97,7 @@ bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand& write,
if (strobeCommand.getStart() >= write.getStart())
{
sc_time tWTR =
(getBankGroup(write.getBank()) == getBankGroup(strobeCommand.getBank())) ?
(write.getBank().getBankGroup() == strobeCommand.getBank().getBankGroup()) ?
config.Timings.tWTR_L : config.Timings.tWTR_S;
return strobeCommand.getStart()

66
dram/src/core/utils/RingBuffer.h
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@@ -1,66 +0,0 @@
/*
* RingBuffer.h
*
* Created on: Mar 13, 2014
* Author: jonny
*/
#ifndef RINGBUFFER_H_
#define RINGBUFFER_H_
#include <systemc.h>
#include <vector>
template<typename T>
class RingBuffer
{
public:
RingBuffer(unsigned int maxSize) : maxSize(maxSize) {}
void put(T t)
{
buffer.push_back(t);
if(getSize() > maxSize)
buffer.erase(buffer.begin());
}
T getOldest() const
{
assert(!isEmpty());
return buffer.front();
}
T getNewest() const
{
assert(!isEmpty());
return buffer.back();
}
bool isFull() const
{
return getSize() == maxSize;
}
bool isEmpty() const
{
return buffer.empty();
}
unsigned int getSize() const
{
return buffer.size();
}
const T get(unsigned int i) const
{
assert(i<getSize());
return buffer[i];
}
private:
std::vector<T> buffer;
unsigned int maxSize;
};
#endif /* RINGBUFFER_H_ */

32
dram/src/core/utils/Utils.cpp
View File

@@ -13,10 +13,6 @@
namespace core {
unsigned int getStartAddress(const Bank& bank)
{
return 0;
}
sc_time getDistance(sc_time a, sc_time b)
{
@@ -58,25 +54,7 @@ bool TimeInterval::intersects(TimeInterval other)
return other.timeIsInInterval(this->start) || this->timeIsInInterval(other.start);
}
BankGroup getBankGroup(Bank bank)
{
static std::map<Bank, BankGroup> bankgroups;
if (bankgroups.size() == 0)
{
SC_ASSERT_(config.NumberOfBanks % config.NumberOfBankGroups == 0, "Number of banks must be a multiple of number of bankgroups");
for (unsigned int bank = 0; bank < Configuration::getInstance().NumberOfBanks; bank++)
{
unsigned int group = bank % Configuration::getInstance().NumberOfBankGroups;
bankgroups.insert(std::pair<Bank, BankGroup>(Bank(bank), BankGroup(group)));
}
}
return bankgroups.at(bank);
}
}
sc_time core::getBurstLengthOnDataStrobe(unsigned int burstlength)
sc_time getBurstLengthOnDataStrobe(unsigned int burstlength)
{
Configuration& config = Configuration::getInstance();
sc_assert((burstlength / config.DataRate) > 0);
@@ -84,14 +62,16 @@ sc_time core::getBurstLengthOnDataStrobe(unsigned int burstlength)
return config.Timings.clk * (burstlength / config.DataRate);
}
void core::setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank)
void setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank)
{
payload.set_address(getStartAddress(bank));
payload.set_address(bank.getStartAddress());
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(0), bank, getBankGroup(bank), Row(0), Column(0))); //payload takes ownership
payload.set_extension(new DramExtension(Thread(0), bank, bank.getBankGroup(), Row(0), Column(0))); //payload takes ownership
}
}

4
dram/src/core/utils/Utils.h
View File

@@ -15,8 +15,8 @@
namespace core
{
unsigned int getStartAddress(const Bank& bank);
sc_time getDistance(sc_time a, sc_time b);
sc_time getDistance(sc_time a, sc_time b);
struct TimeInterval
{
sc_time start,end;
@@ -37,8 +37,6 @@ enum Alignment {UP, DOWN};
const sc_time clkAlign(sc_time time, Alignment alignment = UP);
bool isClkAligned(sc_time time, sc_time clk);
BankGroup getBankGroup(Bank bank);
void setUpDummy(tlm::tlm_generic_payload& payload, Bank& bank);
};

3
dram/src/simulation/Arbiter.h
View File

@@ -136,7 +136,8 @@ private:
unsigned int burstlength = payload.get_streaming_width();
node n;
xmlAddressDecoder::getInstance().getNode(static_cast<unsigned int>(payload.get_address()), &n);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), core::getBankGroup(Bank(n.bank)), Row(n.row), Column(n.colum),burstlength);
Bank bank(n.bank);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), bank, bank.getBankGroup(), Row(n.row), Column(n.colum),burstlength);
payload.set_auto_extension(extension);
}
};

8
dram/src/simulation/Controller.h
View File

@@ -65,10 +65,10 @@ public:
if (selectedScheduler == "FR_FCFS")
{
if(Configuration::getInstance().RefreshAwareScheduling)
cout << "Building refresh aware scheduler" << std::endl;
else
cout << "Building refresh un-aware scheduler" << std::endl;
// if(Configuration::getInstance().RefreshAwareScheduling)
// cout << "Building refresh aware scheduler" << std::endl;
// else
// cout << "Building refresh un-aware scheduler" << std::endl;
scheduler = new FR_FCFS(controller->state.bankStates,
Configuration::getInstance().RefreshAwareScheduling,

2
dram/src/simulation/SimulationManager.h
View File

@@ -29,7 +29,7 @@ struct DramSetup
struct Device
{
Device():trace("empty.stl"), burstLength(0){}
Device(std::string trace, unsigned int burstLength = 4) : trace(trace), burstLength(burstLength)
Device(std::string trace, unsigned int burstLength = 8) : trace(trace), burstLength(burstLength)
{
}
std::string trace;

2
dram/src/simulation/main.cpp
View File

@@ -57,6 +57,7 @@ bool batchTraces(DramSetup setup, vector<pair<string, string>> tracePairs)
if (runSimulation(traceName, setup, { Device(pair.first), Device(pair.second) }))
return true; //kill child
}
return false;
}
bool batchSetups(pair<string, string> tracePair, vector<DramSetup> setups)
@@ -70,6 +71,7 @@ bool batchSetups(pair<string, string> tracePair, vector<DramSetup> setups)
{ Device(tracePair.first), Device(tracePair.second) }))
return true; //kill child
}
return false;
}
int sc_main(int argc, char **argv)
{