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This commit is contained in:
robert
2014-04-11 12:44:17 +02:00
parent 8bc3293dcb d313afa84a
commit 5c899dabe3
12 changed files with 109 additions and 240 deletions
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196
dram/.cproject
View File

@@ -1,169 +1,27 @@
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<name>dram</name>
<comment></comment>
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2
dram/clean
View File

@@ -1,7 +1,7 @@
echo "Cleaning Up:"
echo " -->remove *.txt"
rm *.txt
echo " -->remove *.tdb-journal"
echo " -->remove *.tdb"
rm *.tdb
echo " -->remove *.tdb-journal"
rm *.tdb-journal

1
dram/resources/configs/memconfigs/.gitignore vendored Normal file
View File

@@ -0,0 +1 @@
memconfig.xml

3
dram/resources/configs/memspecs/MatzesWideIO.xml
View File

@@ -28,7 +28,8 @@
<!--<parameter id="XPDLL" type="uint" value="2" />-->
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<!--<parameter id="XSDLL" type="uint" value="20" />-->
<parameter id="REFI" type="uint" value="1300" />
<parameter id="REFI" type="uint" value="1300" />
<!--<parameter id="CL" type="uint" value="3" />-->
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />

8
dram/src/core/configuration/MemSpecLoader.cpp
View File

@@ -99,8 +99,8 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
{
config.Timings.refreshTimings.push_back(
RefreshTiming(config.Timings.tRFC, config.Timings.tREFI));
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC,
config.Timings.tREFI);
}
}
@@ -148,8 +148,8 @@ void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec)
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
{
config.Timings.refreshTimings.push_back(
RefreshTiming(config.Timings.tRFC, config.Timings.tREFI));
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC,
config.Timings.tREFI);
}
}

6
dram/src/core/configuration/TimingConfiguration.h
View File

@@ -10,12 +10,14 @@
#include <systemc.h>
#include "../utils/Utils.h"
#include <map>
namespace core{
struct RefreshTiming
{
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
RefreshTiming() {};
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {};
sc_time tRFC;
sc_time tREFI;
};
@@ -51,7 +53,7 @@ struct TimingConfiguration
sc_time tRFC; //min ref->act delay
sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI
std::vector<RefreshTiming> refreshTimings;
std::map<Bank, RefreshTiming> refreshTimings;//ensure that map is populated completely in memspecloader
//act and read/write commands remain for this timespan in history
sc_time tActHistory(){return tNAW;}

18
dram/src/core/refresh/RefreshManager.cpp
View File

@@ -13,8 +13,8 @@ using namespace tlm;
namespace core {
RefreshManager::RefreshManager(ControllerCore& controller) :
controller(controller), timing(controller.config.Timings.refreshTimings.at(0)), nextPlannedRefresh(
SC_ZERO_TIME), refreshPayloads(controller.config.NumberOfBanks)
controller(controller), timing(controller.config.Timings.refreshTimings[Bank(0)]), nextPlannedRefresh(
SC_ZERO_TIME)
{
setupTransactions();
planNextRefresh();
@@ -34,18 +34,19 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time
sc_assert(!isInvalidated(payload, time));
ScheduledCommand nextRefresh(Command::AutoRefresh, time, timing.tRFC,
DramExtension::getExtension(refreshPayloads.at(0)));
DramExtension::getExtension(refreshPayloads[Bank(0)]));
if (!controller.state.bankStates.allRowBuffersAreClosed())
{
ScheduledCommand precharge(Command::PrechargeAll, time, controller.config.Timings.tRP,
DramExtension::getExtension(refreshPayloads.at(0)));
DramExtension::getExtension(refreshPayloads[Bank(0)]));
controller.getCommandChecker(Command::PrechargeAll).delayToSatisfyConstraints(precharge);
nextRefresh.setStart(precharge.getEnd());
for (tlm::tlm_generic_payload& payload : refreshPayloads)
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payload = refreshPayloads[bank];
ScheduledCommand prechargeToSend(Command::PrechargeAll, precharge.getStart(),
controller.config.Timings.tRP, DramExtension::getExtension(payload));
controller.state.change(prechargeToSend);
@@ -57,8 +58,9 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time
//no precharge all
controller.state.bus.moveCommandToNextFreeSlot(nextRefresh);
}
for (tlm::tlm_generic_payload& payload : refreshPayloads)
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payload = refreshPayloads[bank];
Row currentrow = DramExtension::getExtension(payload).getRow();
DramExtension::getExtension(payload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks));
ScheduledCommand refreshToSend(Command::AutoRefresh, nextRefresh.getStart(), timing.tRFC,
@@ -75,7 +77,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time
void RefreshManager::planNextRefresh()
{
nextPlannedRefresh += timing.tREFI;
controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads.at(0));
controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads[Bank(0)]);
}
void RefreshManager::reInitialize(tlm::tlm_generic_payload& payload, sc_time time)
@@ -93,7 +95,7 @@ void RefreshManager::setupTransactions()
{
for (Bank bank : controller.getBanks())
{
setUpDummy(refreshPayloads.at(bank.ID()), bank);
setUpDummy(refreshPayloads[bank], bank);
}
}

2
dram/src/core/refresh/RefreshManager.h
View File

@@ -32,7 +32,7 @@ private:
ControllerCore& controller;
RefreshTiming& timing;
sc_time nextPlannedRefresh;
std::vector<tlm::tlm_generic_payload> refreshPayloads;
std::map<Bank, tlm::tlm_generic_payload> refreshPayloads;
void planNextRefresh();
void setupTransactions();

25
dram/src/core/refresh/RefreshManagerBankwise.cpp
View File

@@ -20,35 +20,35 @@ RefreshManagerBankwise::RefreshManagerBankwise(ControllerCore& controller) :
for (Bank bank : controller.getBanks())
{
refreshManagerForBanks.push_back(new RefreshManagerForBank(controller, bank));
refreshManagerForBanks[bank] = new RefreshManagerForBank(controller, bank);
}
}
RefreshManagerBankwise::~RefreshManagerBankwise()
{
for (RefreshManagerForBank* manager : refreshManagerForBanks)
for (Bank bank : controller.getBanks())
{
delete manager;
delete refreshManagerForBanks[bank];
}
}
bool RefreshManagerBankwise::hasCollision(const CommandSchedule& schedule)
{
RefreshManagerForBank& manager = *refreshManagerForBanks.at(schedule.getBank().ID());
RefreshManagerForBank& manager = *refreshManagerForBanks[schedule.getBank()];
return manager.hasCollision(schedule);
}
void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time)
{
sc_assert(!isInvalidated(payload, time));
RefreshManagerForBank& manager = *refreshManagerForBanks.at(
DramExtension::getExtension(payload).getBank().ID());
RefreshManagerForBank& manager =
*refreshManagerForBanks[DramExtension::getExtension(payload).getBank()];
manager.scheduleRefresh(time);
}
RefreshManagerBankwise::RefreshManagerForBank::RefreshManagerForBank(ControllerCore& controller,
Bank bank) :
controller(controller), timing(controller.config.Timings.refreshTimings.at(bank.ID())), bank(
controller(controller), timing(controller.config.Timings.refreshTimings[bank]), bank(
bank), nextPlannedRefresh(SC_ZERO_TIME)
{
setupTransaction();
@@ -89,7 +89,8 @@ void RefreshManagerBankwise::RefreshManagerForBank::scheduleRefresh(sc_time time
controller.state.bus.moveCommandToNextFreeSlot(nextRefresh);
controller.state.change(nextRefresh);
Row currentrow = DramExtension::getExtension(refreshPayload).getRow();
DramExtension::getExtension(refreshPayload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks));
DramExtension::getExtension(refreshPayload).setRow(
Row((currentrow.ID() + 1) % Configuration::getInstance().NumberOfBanks));
controller.wrapper.send(nextRefresh, refreshPayload);
planNextRefresh();
@@ -121,14 +122,14 @@ void RefreshManagerBankwise::RefreshManagerForBank::setupTransaction()
void RefreshManagerBankwise::reInitialize(tlm::tlm_generic_payload& payload, sc_time time)
{
refreshManagerForBanks.at(DramExtension::getExtension(payload).getBank().ID())->reInitialize(
payload, time);
refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]->reInitialize(payload,
time);
}
bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload& payload, sc_time time)
{
RefreshManagerForBank& manager = *refreshManagerForBanks.at(
DramExtension::getExtension(payload).getBank().ID());
RefreshManagerForBank& manager =
*refreshManagerForBanks[DramExtension::getExtension(payload).getBank()];
return manager.isInvalidated(time);
}

2
dram/src/core/refresh/RefreshManagerBankwise.h
View File

@@ -57,7 +57,7 @@ private:
};
ControllerCore& controller;
std::vector<RefreshManagerForBank*> refreshManagerForBanks;
std::map<Bank, RefreshManagerForBank*> refreshManagerForBanks;
};

23
dram/src/simulation/SimulationManager.cpp
View File

@@ -17,8 +17,8 @@ using namespace std;
namespace simulation {
Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices, bool silent) :
Simulation::Simulation(sc_module_name name, string pathToResources, string traceName,
DramSetup setup, std::vector<Device> devices, bool silent) :
traceName(traceName)
{
@@ -30,15 +30,18 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace
Configuration::memconfigUri = pathToResources + string("configs/memconfigs/") + setup.memconfig;
Configuration::memspecUri = pathToResources + string("configs/memspecs/") + setup.memspec;
TlmRecorder::getInstance().recordTracenames(devices[0].trace + "," + devices[1].trace);
TlmRecorder::getInstance().recordMemspec(Configuration::memspecUri);
TlmRecorder::getInstance().recordMemconfig(loadTextFileContents(Configuration::memconfigUri));
//setup dram
dram = new Dram<>("dram");
arbiter = new Arbiter<numberOfTracePlayers, 128>("arbiter");
controller = new Controller<>("controller");
//setup devices
for (auto& d : devices)
{
if (d.burstLength == 0)
d.burstLength = Configuration::getInstance().BurstLength;
}
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace,
devices[0].burstLength, this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace,
@@ -64,6 +67,11 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace
auto& dbg = DebugManager::getInstance();
dbg.addToWhiteList(whiteList);
dbg.setDebugFile(traceName + ".txt");
if (silent)
{
dbg.writeToConsole = false;
dbg.writeToFile = false;
}
}
Simulation::~Simulation()
@@ -77,8 +85,10 @@ Simulation::~Simulation()
void Simulation::startSimulation()
{
clock_t begin = clock();
cout<<"Starting simulation"<<endl;
DebugManager::getInstance().printDebugMessage(name(), "Starting simulation");
player1->start();
player2->start();
@@ -88,6 +98,7 @@ void Simulation::startSimulation()
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
DebugManager::getInstance().printDebugMessage(name(),
"Simulation took " + to_string(elapsed_secs) + " seconds");
cout<<"took "<<(elapsed_secs)<<endl;
}
void Simulation::tracePlayerFinishedCallback(string name)

63
dram/src/simulation/main.cpp
View File

@@ -19,7 +19,6 @@ using namespace std;
using namespace simulation;
string resources;
bool silent = false;
string pathOfFile(string file)
{
@@ -33,13 +32,13 @@ void startTraceAnalyzer(string traceName)
system(run_tpr.c_str());
}
bool runSimulation(string traceName, DramSetup setup, vector<Device> devices)
bool runSimulation(string resources, string traceName, DramSetup setup, vector<Device> devices)
{
int pid = fork();
int status = 0;
if (pid == 0)
{
Simulation simulation("sim", resources, traceName, setup, devices,silent);
Simulation simulation("sim", resources, traceName, setup, devices, true);
simulation.startSimulation();
return true;
}
@@ -53,8 +52,8 @@ bool batchTraces(DramSetup setup, vector<pair<string, string>> tracePairs)
for (pair<string, string> pair : tracePairs)
{
id++;
string traceName = "traceBatch" + to_string(id) + ".tdb";
if (runSimulation(traceName, setup, { Device(pair.first), Device(pair.second) }))
string traceName = "batch" + to_string(id) + ".tdb";
if (runSimulation(resources, traceName, setup, { Device(pair.first), Device(pair.second) }))
return true; //kill child
}
return false;
@@ -66,8 +65,8 @@ bool batchSetups(pair<string, string> tracePair, vector<DramSetup> setups)
for (auto& setup : setups)
{
id++;
string traceName = "setupBatch" + to_string(id) + ".tdb";
if (runSimulation(traceName, setup,
string traceName = "batch0" + to_string(id) + ".tdb";
if (runSimulation(resources, traceName, setup,
{ Device(tracePair.first), Device(tracePair.second) }))
return true; //kill child
}
@@ -76,40 +75,34 @@ bool batchSetups(pair<string, string> tracePair, vector<DramSetup> setups)
int sc_main(int argc, char **argv)
{
sc_set_time_resolution(1, SC_PS);
resources = pathOfFile(argv[0]) + string("/../resources/");
// DramSetup setup;
// setup.memconfig = "memconfig.xml";
// //setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
// setup.memspec = "MatzesWideIO.xml";
//
// vector<pair<string, string>> tracePairs;
// tracePairs.push_back(pair<string, string>("chstone-mips_32.stl", "chstone-motion_32.stl"));
//
// batchTraces(setup, tracePairs);
DramSetup setup;
setup.memconfig = "memconfig.xml";
setup.memspec = "MatzesWideIO.xml";
//setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
// DramSetup setup2;
// setup2.memconfig = "memconfig.xml";
// setup2.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
//batchSetups(tracePairs[0], { setup, setup2 });
DramSetup setup2;
setup2.memconfig = "memconfig.xml";
setup2.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml";
Device d1("chstone-motion_32.stl",4);
Device d2("empty.stl",4);
string dramSpec = "MatzesWideIO.xml";
vector<pair<string, string>> tracePairs;
tracePairs.push_back(pair<string, string>("trace.stl", "empty.stl"));
tracePairs.push_back(pair<string, string>("trace2.stl", "empty.stl"));
if(runSimulation("fifo.tdb",DramSetup("fifo.xml",dramSpec),{d1,d2}))
return 0;
if(runSimulation("fr_fcfs.tdb",DramSetup("fr_fcfs.xml",dramSpec),{d1,d2}))
return 0;
// if(runSimulation("fr_fcfs_unaware.tdb",DramSetup("fr_fcfs_unaware.xml",dramSpec),{d1,d2}))
// return 0;
// if(runSimulation("par_bs.tdb",DramSetup("par_bs.xml",dramSpec),{d1,d2}))
// return 0;
// if(runSimulation("par_bs_unaware.tdb",DramSetup("par_bs_unaware.xml",dramSpec),{d1,d2}))
// return 0;
//
// startTraceAnalyzer("fifo.tdb fr_fcfs.tdb fr_fcfs_unaware.tdb par_bs.tdb par_bs_unaware.tdb");
//batchTraces(setup, tracePairs);
//batchSetups(tracePairs[0], {setup});
string traceName("tpr.tdb");
string trace2 = "empty.stl";
string trace1 = "chstone-jpeg_32.stl";
trace1 = "trace.stl";
if (runSimulation(resources, traceName, setup, { Device(trace1), Device(trace2) }))
startTraceAnalyzer(traceName);
return 0;
}