diff --git a/dram/.cproject b/dram/.cproject index b4199db0..0ebeb50d 100644 --- a/dram/.cproject +++ b/dram/.cproject @@ -1,169 +1,27 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - make - - standalone - true - true - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + dram + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/dram/clean b/dram/clean index 66fe384d..0e2d6764 100755 --- a/dram/clean +++ b/dram/clean @@ -1,7 +1,7 @@ echo "Cleaning Up:" echo " -->remove *.txt" rm *.txt -echo " -->remove *.tdb-journal" +echo " -->remove *.tdb" rm *.tdb echo " -->remove *.tdb-journal" rm *.tdb-journal \ No newline at end of file diff --git a/dram/resources/configs/memconfigs/.gitignore b/dram/resources/configs/memconfigs/.gitignore new file mode 100644 index 00000000..c5a87587 --- /dev/null +++ b/dram/resources/configs/memconfigs/.gitignore @@ -0,0 +1 @@ +memconfig.xml \ No newline at end of file diff --git a/dram/resources/configs/memspecs/MatzesWideIO.xml b/dram/resources/configs/memspecs/MatzesWideIO.xml index 5108ebbe..d8fc4025 100644 --- a/dram/resources/configs/memspecs/MatzesWideIO.xml +++ b/dram/resources/configs/memspecs/MatzesWideIO.xml @@ -28,7 +28,8 @@ - + + diff --git a/dram/src/core/configuration/MemSpecLoader.cpp b/dram/src/core/configuration/MemSpecLoader.cpp index effa1eef..3f931833 100644 --- a/dram/src/core/configuration/MemSpecLoader.cpp +++ b/dram/src/core/configuration/MemSpecLoader.cpp @@ -99,8 +99,8 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.Timings.refreshTimings.clear(); for (unsigned int i = 0; i < config.NumberOfBanks; ++i) { - config.Timings.refreshTimings.push_back( - RefreshTiming(config.Timings.tRFC, config.Timings.tREFI)); + config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, + config.Timings.tREFI); } } @@ -148,8 +148,8 @@ void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec) config.Timings.refreshTimings.clear(); for (unsigned int i = 0; i < config.NumberOfBanks; ++i) { - config.Timings.refreshTimings.push_back( - RefreshTiming(config.Timings.tRFC, config.Timings.tREFI)); + config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, + config.Timings.tREFI); } } diff --git a/dram/src/core/configuration/TimingConfiguration.h b/dram/src/core/configuration/TimingConfiguration.h index 79ea3574..61ab2571 100644 --- a/dram/src/core/configuration/TimingConfiguration.h +++ b/dram/src/core/configuration/TimingConfiguration.h @@ -10,12 +10,14 @@ #include #include "../utils/Utils.h" +#include namespace core{ struct RefreshTiming { - RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {} + RefreshTiming() {}; + RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}; sc_time tRFC; sc_time tREFI; }; @@ -51,7 +53,7 @@ struct TimingConfiguration sc_time tRFC; //min ref->act delay sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI - std::vector refreshTimings; + std::map refreshTimings;//ensure that map is populated completely in memspecloader //act and read/write commands remain for this timespan in history sc_time tActHistory(){return tNAW;} diff --git a/dram/src/core/refresh/RefreshManager.cpp b/dram/src/core/refresh/RefreshManager.cpp index d421d257..7e784289 100644 --- a/dram/src/core/refresh/RefreshManager.cpp +++ b/dram/src/core/refresh/RefreshManager.cpp @@ -13,8 +13,8 @@ using namespace tlm; namespace core { RefreshManager::RefreshManager(ControllerCore& controller) : - controller(controller), timing(controller.config.Timings.refreshTimings.at(0)), nextPlannedRefresh( - SC_ZERO_TIME), refreshPayloads(controller.config.NumberOfBanks) + controller(controller), timing(controller.config.Timings.refreshTimings[Bank(0)]), nextPlannedRefresh( + SC_ZERO_TIME) { setupTransactions(); planNextRefresh(); @@ -34,18 +34,19 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time sc_assert(!isInvalidated(payload, time)); ScheduledCommand nextRefresh(Command::AutoRefresh, time, timing.tRFC, - DramExtension::getExtension(refreshPayloads.at(0))); + DramExtension::getExtension(refreshPayloads[Bank(0)])); if (!controller.state.bankStates.allRowBuffersAreClosed()) { ScheduledCommand precharge(Command::PrechargeAll, time, controller.config.Timings.tRP, - DramExtension::getExtension(refreshPayloads.at(0))); + DramExtension::getExtension(refreshPayloads[Bank(0)])); controller.getCommandChecker(Command::PrechargeAll).delayToSatisfyConstraints(precharge); nextRefresh.setStart(precharge.getEnd()); - for (tlm::tlm_generic_payload& payload : refreshPayloads) + for (Bank bank : controller.getBanks()) { + tlm_generic_payload& payload = refreshPayloads[bank]; ScheduledCommand prechargeToSend(Command::PrechargeAll, precharge.getStart(), controller.config.Timings.tRP, DramExtension::getExtension(payload)); controller.state.change(prechargeToSend); @@ -57,8 +58,9 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time //no precharge all controller.state.bus.moveCommandToNextFreeSlot(nextRefresh); } - for (tlm::tlm_generic_payload& payload : refreshPayloads) + for (Bank bank : controller.getBanks()) { + tlm_generic_payload& payload = refreshPayloads[bank]; Row currentrow = DramExtension::getExtension(payload).getRow(); DramExtension::getExtension(payload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks)); ScheduledCommand refreshToSend(Command::AutoRefresh, nextRefresh.getStart(), timing.tRFC, @@ -75,7 +77,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time void RefreshManager::planNextRefresh() { nextPlannedRefresh += timing.tREFI; - controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads.at(0)); + controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshPayloads[Bank(0)]); } void RefreshManager::reInitialize(tlm::tlm_generic_payload& payload, sc_time time) @@ -93,7 +95,7 @@ void RefreshManager::setupTransactions() { for (Bank bank : controller.getBanks()) { - setUpDummy(refreshPayloads.at(bank.ID()), bank); + setUpDummy(refreshPayloads[bank], bank); } } diff --git a/dram/src/core/refresh/RefreshManager.h b/dram/src/core/refresh/RefreshManager.h index e7896da2..46d5a33f 100644 --- a/dram/src/core/refresh/RefreshManager.h +++ b/dram/src/core/refresh/RefreshManager.h @@ -32,7 +32,7 @@ private: ControllerCore& controller; RefreshTiming& timing; sc_time nextPlannedRefresh; - std::vector refreshPayloads; + std::map refreshPayloads; void planNextRefresh(); void setupTransactions(); diff --git a/dram/src/core/refresh/RefreshManagerBankwise.cpp b/dram/src/core/refresh/RefreshManagerBankwise.cpp index 10b99668..cde123b7 100644 --- a/dram/src/core/refresh/RefreshManagerBankwise.cpp +++ b/dram/src/core/refresh/RefreshManagerBankwise.cpp @@ -20,35 +20,35 @@ RefreshManagerBankwise::RefreshManagerBankwise(ControllerCore& controller) : for (Bank bank : controller.getBanks()) { - refreshManagerForBanks.push_back(new RefreshManagerForBank(controller, bank)); + refreshManagerForBanks[bank] = new RefreshManagerForBank(controller, bank); } } RefreshManagerBankwise::~RefreshManagerBankwise() { - for (RefreshManagerForBank* manager : refreshManagerForBanks) + for (Bank bank : controller.getBanks()) { - delete manager; + delete refreshManagerForBanks[bank]; } } bool RefreshManagerBankwise::hasCollision(const CommandSchedule& schedule) { - RefreshManagerForBank& manager = *refreshManagerForBanks.at(schedule.getBank().ID()); + RefreshManagerForBank& manager = *refreshManagerForBanks[schedule.getBank()]; return manager.hasCollision(schedule); } void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time) { sc_assert(!isInvalidated(payload, time)); - RefreshManagerForBank& manager = *refreshManagerForBanks.at( - DramExtension::getExtension(payload).getBank().ID()); + RefreshManagerForBank& manager = + *refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]; manager.scheduleRefresh(time); } RefreshManagerBankwise::RefreshManagerForBank::RefreshManagerForBank(ControllerCore& controller, Bank bank) : - controller(controller), timing(controller.config.Timings.refreshTimings.at(bank.ID())), bank( + controller(controller), timing(controller.config.Timings.refreshTimings[bank]), bank( bank), nextPlannedRefresh(SC_ZERO_TIME) { setupTransaction(); @@ -89,7 +89,8 @@ void RefreshManagerBankwise::RefreshManagerForBank::scheduleRefresh(sc_time time controller.state.bus.moveCommandToNextFreeSlot(nextRefresh); controller.state.change(nextRefresh); Row currentrow = DramExtension::getExtension(refreshPayload).getRow(); - DramExtension::getExtension(refreshPayload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks)); + DramExtension::getExtension(refreshPayload).setRow( + Row((currentrow.ID() + 1) % Configuration::getInstance().NumberOfBanks)); controller.wrapper.send(nextRefresh, refreshPayload); planNextRefresh(); @@ -121,14 +122,14 @@ void RefreshManagerBankwise::RefreshManagerForBank::setupTransaction() void RefreshManagerBankwise::reInitialize(tlm::tlm_generic_payload& payload, sc_time time) { - refreshManagerForBanks.at(DramExtension::getExtension(payload).getBank().ID())->reInitialize( - payload, time); + refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]->reInitialize(payload, + time); } bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload& payload, sc_time time) { - RefreshManagerForBank& manager = *refreshManagerForBanks.at( - DramExtension::getExtension(payload).getBank().ID()); + RefreshManagerForBank& manager = + *refreshManagerForBanks[DramExtension::getExtension(payload).getBank()]; return manager.isInvalidated(time); } diff --git a/dram/src/core/refresh/RefreshManagerBankwise.h b/dram/src/core/refresh/RefreshManagerBankwise.h index 48b5f29f..34eac9ed 100644 --- a/dram/src/core/refresh/RefreshManagerBankwise.h +++ b/dram/src/core/refresh/RefreshManagerBankwise.h @@ -57,7 +57,7 @@ private: }; ControllerCore& controller; - std::vector refreshManagerForBanks; + std::map refreshManagerForBanks; }; diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index fb3f69b2..99bbfb69 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -17,8 +17,8 @@ using namespace std; namespace simulation { -Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup, - std::vector devices, bool silent) : +Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, + DramSetup setup, std::vector devices, bool silent) : traceName(traceName) { @@ -30,15 +30,18 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace Configuration::memconfigUri = pathToResources + string("configs/memconfigs/") + setup.memconfig; Configuration::memspecUri = pathToResources + string("configs/memspecs/") + setup.memspec; - TlmRecorder::getInstance().recordTracenames(devices[0].trace + "," + devices[1].trace); - TlmRecorder::getInstance().recordMemspec(Configuration::memspecUri); - TlmRecorder::getInstance().recordMemconfig(loadTextFileContents(Configuration::memconfigUri)); - //setup dram dram = new Dram<>("dram"); arbiter = new Arbiter("arbiter"); controller = new Controller<>("controller"); + //setup devices + for (auto& d : devices) + { + if (d.burstLength == 0) + d.burstLength = Configuration::getInstance().BurstLength; + } + player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, this); player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, @@ -64,6 +67,11 @@ Simulation::Simulation(sc_module_name name, string pathToResources, string trace auto& dbg = DebugManager::getInstance(); dbg.addToWhiteList(whiteList); dbg.setDebugFile(traceName + ".txt"); + if (silent) + { + dbg.writeToConsole = false; + dbg.writeToFile = false; + } } Simulation::~Simulation() @@ -77,8 +85,10 @@ Simulation::~Simulation() void Simulation::startSimulation() { + clock_t begin = clock(); + cout<<"Starting simulation"<start(); player2->start(); @@ -88,6 +98,7 @@ void Simulation::startSimulation() double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC; DebugManager::getInstance().printDebugMessage(name(), "Simulation took " + to_string(elapsed_secs) + " seconds"); + cout<<"took "<<(elapsed_secs)< devices) +bool runSimulation(string resources, string traceName, DramSetup setup, vector devices) { int pid = fork(); int status = 0; if (pid == 0) { - Simulation simulation("sim", resources, traceName, setup, devices,silent); + Simulation simulation("sim", resources, traceName, setup, devices, true); simulation.startSimulation(); return true; } @@ -53,8 +52,8 @@ bool batchTraces(DramSetup setup, vector> tracePairs) for (pair pair : tracePairs) { id++; - string traceName = "traceBatch" + to_string(id) + ".tdb"; - if (runSimulation(traceName, setup, { Device(pair.first), Device(pair.second) })) + string traceName = "batch" + to_string(id) + ".tdb"; + if (runSimulation(resources, traceName, setup, { Device(pair.first), Device(pair.second) })) return true; //kill child } return false; @@ -66,8 +65,8 @@ bool batchSetups(pair tracePair, vector setups) for (auto& setup : setups) { id++; - string traceName = "setupBatch" + to_string(id) + ".tdb"; - if (runSimulation(traceName, setup, + string traceName = "batch0" + to_string(id) + ".tdb"; + if (runSimulation(resources, traceName, setup, { Device(tracePair.first), Device(tracePair.second) })) return true; //kill child } @@ -76,40 +75,34 @@ bool batchSetups(pair tracePair, vector setups) int sc_main(int argc, char **argv) { sc_set_time_resolution(1, SC_PS); + resources = pathOfFile(argv[0]) + string("/../resources/"); -// DramSetup setup; -// setup.memconfig = "memconfig.xml"; -// //setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; -// setup.memspec = "MatzesWideIO.xml"; -// -// vector> tracePairs; -// tracePairs.push_back(pair("chstone-mips_32.stl", "chstone-motion_32.stl")); -// -// batchTraces(setup, tracePairs); + DramSetup setup; + setup.memconfig = "memconfig.xml"; + setup.memspec = "MatzesWideIO.xml"; + //setup.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; -// DramSetup setup2; -// setup2.memconfig = "memconfig.xml"; -// setup2.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; - //batchSetups(tracePairs[0], { setup, setup2 }); + DramSetup setup2; + setup2.memconfig = "memconfig.xml"; + setup2.memspec = "MICRON_4Gb_DDR4-1866_8bit_A.xml"; - Device d1("chstone-motion_32.stl",4); - Device d2("empty.stl",4); - string dramSpec = "MatzesWideIO.xml"; + vector> tracePairs; + tracePairs.push_back(pair("trace.stl", "empty.stl")); + tracePairs.push_back(pair("trace2.stl", "empty.stl")); - if(runSimulation("fifo.tdb",DramSetup("fifo.xml",dramSpec),{d1,d2})) - return 0; - if(runSimulation("fr_fcfs.tdb",DramSetup("fr_fcfs.xml",dramSpec),{d1,d2})) - return 0; -// if(runSimulation("fr_fcfs_unaware.tdb",DramSetup("fr_fcfs_unaware.xml",dramSpec),{d1,d2})) -// return 0; -// if(runSimulation("par_bs.tdb",DramSetup("par_bs.xml",dramSpec),{d1,d2})) -// return 0; -// if(runSimulation("par_bs_unaware.tdb",DramSetup("par_bs_unaware.xml",dramSpec),{d1,d2})) -// return 0; -// -// startTraceAnalyzer("fifo.tdb fr_fcfs.tdb fr_fcfs_unaware.tdb par_bs.tdb par_bs_unaware.tdb"); + //batchTraces(setup, tracePairs); + //batchSetups(tracePairs[0], {setup}); + + string traceName("tpr.tdb"); + + string trace2 = "empty.stl"; + string trace1 = "chstone-jpeg_32.stl"; + trace1 = "trace.stl"; + + if (runSimulation(resources, traceName, setup, { Device(trace1), Device(trace2) })) + startTraceAnalyzer(traceName); return 0; }