derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

addressmapping for ddr4

Browse Source
This commit is contained in:
robert
2014-04-20 22:16:32 +02:00
parent 354c871047
commit b75366edda
11 changed files with 188 additions and 193 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
dram/resources/configs/amconfigs/am_ddr4.xml
View File

@@ -1,27 +1,16 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!--
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<row from="15" to="26" />
<bank from="11" to="14" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
<!-- <channel from="27" to="28" />
<row from="14" to="26" />
<bytes from="10" to="13" />
<colum from="3" to="9" />
<bank from="0" to="2" /> -->
<!-- highest bank parallelism - high hits -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<colum from="9" to="18" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

18
dram/resources/configs/amconfigs/am_wideio.xml
View File

@@ -1,15 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!--
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
@@ -17,11 +7,5 @@
<bank from="11" to="13" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
<!-- <channel from="27" to="28" />
<row from="14" to="26" />
<bytes from="10" to="13" />
<colum from="3" to="9" />
<bank from="0" to="2" /> -->
</addressmap>
</dramconfig>

2
dram/resources/configs/memconfigs/fifo.xml
View File

@@ -4,7 +4,7 @@
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="FIFO" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>

2
dram/resources/configs/memconfigs/fr_fcfs.xml
View File

@@ -3,7 +3,7 @@
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />

2
dram/resources/configs/memconfigs/fr_fcfs_unaware.xml
View File

@@ -4,7 +4,7 @@
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>

2
dram/resources/configs/memconfigs/par_bs.xml
View File

@@ -4,7 +4,7 @@
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="PAR_BS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>

101
dram/resources/scripts/metrics.py
View File

@@ -42,58 +42,58 @@ def average_response_latency_in_ns(connection):
result = cursor.fetchone()
return round(result[0],1)
@metric
def median_response_latency_in_ns(connection):
cursor = connection.cursor()
cursor.execute("""SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
result = cursor.fetchone()
return round(result[0],1)
# @metric
# def median_response_latency_in_ns(connection):
# cursor = connection.cursor()
# cursor.execute("""SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
# result = cursor.fetchone()
# return round(result[0],1)
@metric
def max_response_latency_in_ns(connection):
cursor = connection.cursor()
cursor.execute("""SELECT max(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
result = cursor.fetchone()
return round(result[0],1)
# @metric
# def max_response_latency_in_ns(connection):
# cursor = connection.cursor()
# cursor.execute("""SELECT max(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
# result = cursor.fetchone()
# return round(result[0],1)
@metric
def min_response_latency_in_ns(connection):
cursor = connection.cursor()
cursor.execute("""SELECT min(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
result = cursor.fetchone()
return round(result[0],1)
# @metric
# def min_response_latency_in_ns(connection):
# cursor = connection.cursor()
# cursor.execute("""SELECT min(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
# result = cursor.fetchone()
# return round(result[0],1)
@metric
def stdDev_response_latency_in_ns(connection):
cursor = connection.cursor()
cursor.execute("""SELECT stdev(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
result = cursor.fetchone()
return round(result[0],1)
# @metric
# def stdDev_response_latency_in_ns(connection):
# cursor = connection.cursor()
# cursor.execute("""SELECT stdev(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """)
# result = cursor.fetchone()
# return round(result[0],1)
@threadMetric
def average_response_latency_in_ns(connection, thread):
cursor = connection.cursor()
query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """
# @threadMetric
# def average_response_latency_in_ns(connection, thread):
# cursor = connection.cursor()
# query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """
cursor.execute(query, {"Thread": thread})
result = cursor.fetchone()
return round(result[0],1)
# cursor.execute(query, {"Thread": thread})
# result = cursor.fetchone()
# return round(result[0],1)
@threadMetric
def median_response_latency_in_ns(connection, thread):
cursor = connection.cursor()
query = """SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """
# @threadMetric
# def median_response_latency_in_ns(connection, thread):
# cursor = connection.cursor()
# query = """SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases
# ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """
cursor.execute(query, {"Thread": thread})
result = cursor.fetchone()
return round(result[0],1)
# cursor.execute(query, {"Thread": thread})
# result = cursor.fetchone()
# return round(result[0],1)
@metric
def number_of_activates(connection):
@@ -116,7 +116,6 @@ def accesses_per_activate(connection):
result = cursor.fetchone()
return round(result[0]*1.0/number_of_activates(connection),1)
def timeInPowerStates(connection):
totalTimeAllBanks = getTraceLength(connection)*getNumberOfBanks(connection)
cursor = connection.cursor()
@@ -216,14 +215,14 @@ def calculateMetrics(pathToTrace):
print("{0}: {1}".format(res[0],res[1]))
calculatedMetrics.append(res)
for thread in getThreads(connection):
for metric in threadMetrics:
res = ("Thread " + str(thread) + " " + metric.__name__.replace("_"," "), metric(connection, thread))
print("{0}: {1}".format(res[0],res[1]))
calculatedMetrics.append(res)
# for thread in getThreads(connection):
# for metric in threadMetrics:
# res = ("Thread " + str(thread) + " " + metric.__name__.replace("_"," "), metric(connection, thread))
# print("{0}: {1}".format(res[0],res[1]))
# calculatedMetrics.append(res)
calculatedMetrics.extend(passRatio(connection))
calculatedMetrics.extend(timeInPowerStates(connection))
#calculatedMetrics.extend(timeInPowerStates(connection))
connection.close()
return calculatedMetrics

126
dram/resources/scripts/stlGenerator.py Normal file → Executable file
View File

@@ -31,26 +31,26 @@ class DramConfigReader:
print(self.endBits)
class StlReader:
__dramConfigReader = DramConfigReader()
# __dramConfigReader = DramConfigReader()
def onesMask(self, numberOfOnes):
result = 0
for i in range(numberOfOnes):
result = result | 1 << i
return result
# def onesMask(self, numberOfOnes):
# result = 0
# for i in range(numberOfOnes):
# result = result | 1 << i
# return result
def parseAttributeFromAddress(self, address, element):
return (address >> self.__dramConfigReader.startBits[element]) & self.onesMask(self.__dramConfigReader.endBits[element] - self.__dramConfigReader.startBits[element] + 1)
# def parseAttributeFromAddress(self, address, element):
# return (address >> self.__dramConfigReader.startBits[element]) & self.onesMask(self.__dramConfigReader.endBits[element] - self.__dramConfigReader.startBits[element] + 1)
def formatStlLine(self, line):
try:
found = re.search('0x[0-9,a-f]+', line).group(0)
address = int(found, 16)
decodedAddress = '[Channel: {0} Bank: {0} Row:{1} Col:{2}]'.format(self.parseAttributeFromAddress(address, 'channel'),
self.parseAttributeFromAddress(address, 'bank'), self.parseAttributeFromAddress(address, 'row'), self.parseAttributeFromAddress(address, 'colum'))
return line.replace("\n", " ") + decodedAddress
except AttributeError:
return ''
# def formatStlLine(self, line):
# try:
# found = re.search('0x[0-9,a-f]+', line).group(0)
# address = int(found, 16)
# decodedAddress = '[Channel: {0} Bank: {0} Row:{1} Col:{2}]'.format(self.parseAttributeFromAddress(address, 'channel'),
# self.parseAttributeFromAddress(address, 'bank'), self.parseAttributeFromAddress(address, 'row'), self.parseAttributeFromAddress(address, 'colum'))
# return line.replace("\n", " ") + decodedAddress
# except AttributeError:
# return ''
def printStlPretty(self, filename):
f = open(filename)
@@ -58,62 +58,62 @@ class StlReader:
#print(self.formatStlLine(line))
found = re.search('0x[0-9,a-f]+', line).group(0)
address = int(found, 16)
print(format(address, '032b') + " " + self.formatStlLine(line))
print(format(address, '032b')) #+ " " + self.formatStlLine(line))
class StlGenerator:
__actions = []
__time = 0
__dramConfigReader = DramConfigReader()
# class StlGenerator:
# __actions = []
# __time = 0
# __dramConfigReader = DramConfigReader()
def clear(self):
self.__actions = []
self.__time = 0
# def clear(self):
# self.__actions = []
# self.__time = 0
def setTime(self, time):
self.__time = time
# def setTime(self, time):
# self.__time = time
def addAction(self, bank, row, channel=0, RD_WR='read'):
tupel = (self.__time, RD_WR, self.__generateAdress(channel, bank, row))
self.__actions.append(tupel)
# def addAction(self, bank, row, channel=0, RD_WR='read'):
# tupel = (self.__time, RD_WR, self.__generateAdress(channel, bank, row))
# self.__actions.append(tupel)
def setTimeAndAddAction(self, time, bank, row, channel=0, RD_WR='read'):
self.setTime(self, time)
self.addAction(self, bank, row, channel, RD_WR)
# def setTimeAndAddAction(self, time, bank, row, channel=0, RD_WR='read'):
# self.setTime(self, time)
# self.addAction(self, bank, row, channel, RD_WR)
def addLoad(self, banks, rows, channel=0, RD_WR='read'):
for bank in banks:
for row in rows:
self.addAction(bank, row, channel, RD_WR)
# def addLoad(self, banks, rows, channel=0, RD_WR='read'):
# for bank in banks:
# for row in rows:
# self.addAction(bank, row, channel, RD_WR)
def setTimeAndAddLoad(self, time, banks, rows, channel=0, RD_WR='read'):
self.setTime(self, time)
self.addLoad(banks, rows, channel, RD_WR)
# def setTimeAndAddLoad(self, time, banks, rows, channel=0, RD_WR='read'):
# self.setTime(self, time)
# self.addLoad(banks, rows, channel, RD_WR)
def generateStl(self, filename):
f = open(filename, 'w')
tmp = []
for tupel in self.__actions:
tmp.append('{0}: {1} {2:#x}'.format(tupel[0], tupel[1], tupel[2]))
result = '\n'.join(tmp)
f.write(result)
f.close()
print(
'<---------------------- Generated stl {0} ---------------------->'.format(filename))
print(result)
print(
'<---------------------- End generated stl ---------------------->'.format(filename))
# def generateStl(self, filename):
# f = open(filename, 'w')
# tmp = []
# for tupel in self.__actions:
# tmp.append('{0}: {1} {2:#x}'.format(tupel[0], tupel[1], tupel[2]))
# result = '\n'.join(tmp)
# f.write(result)
# f.close()
# print(
# '<---------------------- Generated stl {0} ---------------------->'.format(filename))
# print(result)
# print(
# '<---------------------- End generated stl ---------------------->'.format(filename))
def __generateAdress(self, channel, bank, row):
if(channel > self.__dramConfigReader.maxValues['channel']):
raise(BaseException('Channel argument out of range'))
if(bank > self.__dramConfigReader.maxValues['bank']):
raise(BaseException('Bank argument out of range'))
if(row > self.__dramConfigReader.maxValues['row']):
raise(BaseException('Row argument out of range'))
return (channel << self.__dramConfigReader.startBits['channel']) | (bank << self.__dramConfigReader.startBits['bank']) | (row << self.__dramConfigReader.startBits['row'])
# def __generateAdress(self, channel, bank, row):
# if(channel > self.__dramConfigReader.maxValues['channel']):
# raise(BaseException('Channel argument out of range'))
# if(bank > self.__dramConfigReader.maxValues['bank']):
# raise(BaseException('Bank argument out of range'))
# if(row > self.__dramConfigReader.maxValues['row']):
# raise(BaseException('Row argument out of range'))
# return (channel << self.__dramConfigReader.startBits['channel']) | (bank << self.__dramConfigReader.startBits['bank']) | (row << self.__dramConfigReader.startBits['row'])
def __init__(self):
pass
# def __init__(self):
# pass
if __name__ == '__main__':

35
dram/resources/simulations/first.xml
View File

@@ -1,16 +1,33 @@
<simulation id = "first">
<!-- <memspec>JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml</memspec>
<addressmapping>am_wideioFourBanks.xml</addressmapping>
-->
<memspec>MICRON_4Gb_DDR4-2400_8bit_A.xml</memspec>
<addressmapping>am_ddr4.xml</addressmapping>
<simulation id = "firstchstone">
<memspec>DDR4.xml</memspec>
<!-- <addressmapping>am_lowPara.xml</addressmapping> -->
<addressmapping>am_highPara.xml</addressmapping>
<!-- <addressmapping>am_lowHits.xml</addressmapping> -->
<!-- <addressmapping>am_highHits.xml</addressmapping> -->
<memconfigs>
<memconfig>fr_fcfs.xml</memconfig>
<!-- <memconfig>fr_fcfs_bankwise.xml</memconfig>
<memconfig>fr_fcfs.xml</memconfig>
<memconfig>fr_fcfs_unaware.xml</memconfig>
<!-- <memconfig>fifo.xml</memconfig>
--> <!-- <memconfig>par_bs.xml</memconfig> -->
<!-- <memconfig>fr_fcfs_bankwise.xml</memconfig>
--> </memconfigs>
<trace-setups>
<trace-setup id="1">
<device >chstone-jpeg_32.stl</device>
<device >chstone-sha_32.stl</device>
<device >chstone-aes_32.stl</device>
</trace-setup>
<trace-setup id="2">
<device >mediabench-h263decode_32.stl</device>
<device >mediabench-g721encode_32.stl</device>
</trace-setup>
<trace-setup id="3">
<device >mediabench-fractal_32.stl</device>
<device >chstone-aes_32.stl</device>
</trace-setup>
<trace-setup id="4">
<device >mediabench-h263decode_32.stl</device>
<device >chstone-aes_32.stl</device>
</trace-setup>
</trace-setups>
</simulation>

36
dram/src/common/xmlAddressdecoder.cpp
View File

@@ -17,15 +17,15 @@ xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI)
unsigned int to;
// get channel:
TiXmlElement* channel = addressmap->FirstChildElement("channel");
from = getAttribute<unsigned int>(channel, "from");
to = getAttribute<unsigned int>(channel, "to");
channelShift = from;
channelMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
channelSize = pow(2.0, to - from + 1.0);
// TiXmlElement* channel = addressmap->FirstChildElement("channel");
//
//
// from = getAttribute<unsigned int>(channel, "from");
// to = getAttribute<unsigned int>(channel, "to");
//
// channelShift = from;
// channelMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
// channelSize = pow(2.0, to - from + 1.0);
// get row:
TiXmlElement* row = addressmap->FirstChildElement("row");
@@ -58,14 +58,14 @@ xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI)
columSize = pow(2.0, to - from + 1.0);
// get bytes:
TiXmlElement* bytes = addressmap->FirstChildElement("bytes");
// TiXmlElement* bytes = addressmap->FirstChildElement("bytes");
//
// from = getAttribute<unsigned int>(bytes, "from");
// to = getAttribute<unsigned int>(bytes, "to");
from = getAttribute<unsigned int>(bytes, "from");
to = getAttribute<unsigned int>(bytes, "to");
bytesShift = from;
bytesMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
bytesSize = pow(2.0, to - from + 1.0);
// bytesShift = from;
// bytesMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
// bytesSize = pow(2.0, to - from + 1.0);
}
else
{
@@ -80,7 +80,7 @@ xmlAddressDecoder::~xmlAddressDecoder()
void xmlAddressDecoder::getNode(unsigned int addr, node * n)
{
n->channel = (addr & channelMask) >> channelShift;
n->channel = 0;
n->row = (addr & rowMask) >> rowShift;
n->bank = (addr & bankMask) >> bankShift;
n->colum = (addr & columMask) >> columShift;
@@ -122,5 +122,5 @@ unsigned int xmlAddressDecoder::getNumberOfColumsPerRow()
unsigned int xmlAddressDecoder::getNumberOfBytesPerColumn()
{
return bytesSize;
return 1;
}

20
dram/src/simulation/SimulationManager.cpp
View File

@@ -63,11 +63,13 @@ void SimulationManager::runSimulations()
{
string memconfig = getFileName(dramSetup.memconfig);
string memspec = getFileName(dramSetup.memspec);
string addressmappig = getFileName(dramSetup.addressmapping);
for (auto& traceSetup : batch.traceSetups)
{
runSimulation(exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + memconfig + "-" + memspec + ".tdb",
dramSetup, traceSetup.second);
runSimulation(
exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + memconfig + "-" + memspec + "-" +
addressmappig + ".tdb", dramSetup, traceSetup.second);
}
}
}
@@ -80,17 +82,21 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation)
batch.simulationName = simulation->Attribute("id");
string memspecUri;
string addressmappingUri = simulation->FirstChildElement("addressmapping")->GetText();
string addressmappingUri;
for (XMLElement* element = simulation->FirstChildElement("memspec"); element != NULL;
element = element->NextSiblingElement("memspec"))
{
memspecUri = element->GetText();
for (XMLElement* element = simulation->FirstChildElement("memconfigs")->FirstChildElement("memconfig"); element != NULL;
element = element->NextSiblingElement("memconfig"))
for (XMLElement* element = simulation->FirstChildElement("addressmapping"); element != NULL;
element = element->NextSiblingElement("addressmapping"))
{
batch.dramSetups.push_back(DramSetup(element->GetText(), memspecUri, addressmappingUri));
addressmappingUri = element->GetText();
for (XMLElement* element = simulation->FirstChildElement("memconfigs")->FirstChildElement("memconfig");
element != NULL; element = element->NextSiblingElement("memconfig"))
{
batch.dramSetups.push_back(DramSetup(element->GetText(), memspecUri, addressmappingUri));
}
}
}