diff --git a/dram/resources/configs/amconfigs/am_ddr4.xml b/dram/resources/configs/amconfigs/am_ddr4.xml index 73d9cb36..22bf01b2 100755 --- a/dram/resources/configs/amconfigs/am_ddr4.xml +++ b/dram/resources/configs/amconfigs/am_ddr4.xml @@ -1,27 +1,16 @@ - - - - - - - - - - + + + + + + + + + + + + + diff --git a/dram/resources/configs/amconfigs/am_wideio.xml b/dram/resources/configs/amconfigs/am_wideio.xml index 7494e586..48416d24 100755 --- a/dram/resources/configs/amconfigs/am_wideio.xml +++ b/dram/resources/configs/amconfigs/am_wideio.xml @@ -1,15 +1,5 @@ - + @@ -17,11 +7,5 @@ - - diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml index e0c9501c..16e9bcb2 100644 --- a/dram/resources/configs/memconfigs/fifo.xml +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -4,7 +4,7 @@ - + diff --git a/dram/resources/configs/memconfigs/fr_fcfs.xml b/dram/resources/configs/memconfigs/fr_fcfs.xml index 55831e10..b10a2818 100644 --- a/dram/resources/configs/memconfigs/fr_fcfs.xml +++ b/dram/resources/configs/memconfigs/fr_fcfs.xml @@ -3,7 +3,7 @@ - + diff --git a/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml b/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml index 1da98872..55831e10 100644 --- a/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml +++ b/dram/resources/configs/memconfigs/fr_fcfs_unaware.xml @@ -4,7 +4,7 @@ - + diff --git a/dram/resources/configs/memconfigs/par_bs.xml b/dram/resources/configs/memconfigs/par_bs.xml index 2cc90b3a..c27fd9d9 100644 --- a/dram/resources/configs/memconfigs/par_bs.xml +++ b/dram/resources/configs/memconfigs/par_bs.xml @@ -4,7 +4,7 @@ - + diff --git a/dram/resources/scripts/metrics.py b/dram/resources/scripts/metrics.py index 59318a6f..1a1769b2 100644 --- a/dram/resources/scripts/metrics.py +++ b/dram/resources/scripts/metrics.py @@ -42,58 +42,58 @@ def average_response_latency_in_ns(connection): result = cursor.fetchone() return round(result[0],1) -@metric -def median_response_latency_in_ns(connection): - cursor = connection.cursor() - cursor.execute("""SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) - result = cursor.fetchone() - return round(result[0],1) +# @metric +# def median_response_latency_in_ns(connection): +# cursor = connection.cursor() +# cursor.execute("""SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases +# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) +# result = cursor.fetchone() +# return round(result[0],1) -@metric -def max_response_latency_in_ns(connection): - cursor = connection.cursor() - cursor.execute("""SELECT max(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) - result = cursor.fetchone() - return round(result[0],1) +# @metric +# def max_response_latency_in_ns(connection): +# cursor = connection.cursor() +# cursor.execute("""SELECT max(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases +# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) +# result = cursor.fetchone() +# return round(result[0],1) -@metric -def min_response_latency_in_ns(connection): - cursor = connection.cursor() - cursor.execute("""SELECT min(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) - result = cursor.fetchone() - return round(result[0],1) +# @metric +# def min_response_latency_in_ns(connection): +# cursor = connection.cursor() +# cursor.execute("""SELECT min(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases +# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) +# result = cursor.fetchone() +# return round(result[0],1) -@metric -def stdDev_response_latency_in_ns(connection): - cursor = connection.cursor() - cursor.execute("""SELECT stdev(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) - result = cursor.fetchone() - return round(result[0],1) +# @metric +# def stdDev_response_latency_in_ns(connection): +# cursor = connection.cursor() +# cursor.execute("""SELECT stdev(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases +# ON phases.transact = transactions.ID WHERE PhaseName='RESP' """) +# result = cursor.fetchone() +# return round(result[0],1) -@threadMetric -def average_response_latency_in_ns(connection, thread): - cursor = connection.cursor() - query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """ +# @threadMetric +# def average_response_latency_in_ns(connection, thread): +# cursor = connection.cursor() +# query = """SELECT avg(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases +# ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """ - cursor.execute(query, {"Thread": thread}) - result = cursor.fetchone() - return round(result[0],1) +# cursor.execute(query, {"Thread": thread}) +# result = cursor.fetchone() +# return round(result[0],1) -@threadMetric -def median_response_latency_in_ns(connection, thread): - cursor = connection.cursor() - query = """SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases - ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """ +# @threadMetric +# def median_response_latency_in_ns(connection, thread): +# cursor = connection.cursor() +# query = """SELECT median(PhaseBegin-timeOfGeneration)/1000 FROM transactions INNER JOIN Phases +# ON phases.transact = transactions.ID WHERE PhaseName='RESP' AND TThread = :Thread """ - cursor.execute(query, {"Thread": thread}) - result = cursor.fetchone() - return round(result[0],1) +# cursor.execute(query, {"Thread": thread}) +# result = cursor.fetchone() +# return round(result[0],1) @metric def number_of_activates(connection): @@ -116,7 +116,6 @@ def accesses_per_activate(connection): result = cursor.fetchone() return round(result[0]*1.0/number_of_activates(connection),1) - def timeInPowerStates(connection): totalTimeAllBanks = getTraceLength(connection)*getNumberOfBanks(connection) cursor = connection.cursor() @@ -216,14 +215,14 @@ def calculateMetrics(pathToTrace): print("{0}: {1}".format(res[0],res[1])) calculatedMetrics.append(res) - for thread in getThreads(connection): - for metric in threadMetrics: - res = ("Thread " + str(thread) + " " + metric.__name__.replace("_"," "), metric(connection, thread)) - print("{0}: {1}".format(res[0],res[1])) - calculatedMetrics.append(res) + # for thread in getThreads(connection): + # for metric in threadMetrics: + # res = ("Thread " + str(thread) + " " + metric.__name__.replace("_"," "), metric(connection, thread)) + # print("{0}: {1}".format(res[0],res[1])) + # calculatedMetrics.append(res) calculatedMetrics.extend(passRatio(connection)) - calculatedMetrics.extend(timeInPowerStates(connection)) + #calculatedMetrics.extend(timeInPowerStates(connection)) connection.close() return calculatedMetrics diff --git a/dram/resources/scripts/stlGenerator.py b/dram/resources/scripts/stlGenerator.py old mode 100644 new mode 100755 index 66f25dde..2fbe5373 --- a/dram/resources/scripts/stlGenerator.py +++ b/dram/resources/scripts/stlGenerator.py @@ -31,26 +31,26 @@ class DramConfigReader: print(self.endBits) class StlReader: - __dramConfigReader = DramConfigReader() + # __dramConfigReader = DramConfigReader() - def onesMask(self, numberOfOnes): - result = 0 - for i in range(numberOfOnes): - result = result | 1 << i - return result + # def onesMask(self, numberOfOnes): + # result = 0 + # for i in range(numberOfOnes): + # result = result | 1 << i + # return result - def parseAttributeFromAddress(self, address, element): - return (address >> self.__dramConfigReader.startBits[element]) & self.onesMask(self.__dramConfigReader.endBits[element] - self.__dramConfigReader.startBits[element] + 1) + # def parseAttributeFromAddress(self, address, element): + # return (address >> self.__dramConfigReader.startBits[element]) & self.onesMask(self.__dramConfigReader.endBits[element] - self.__dramConfigReader.startBits[element] + 1) - def formatStlLine(self, line): - try: - found = re.search('0x[0-9,a-f]+', line).group(0) - address = int(found, 16) - decodedAddress = '[Channel: {0} Bank: {0} Row:{1} Col:{2}]'.format(self.parseAttributeFromAddress(address, 'channel'), - self.parseAttributeFromAddress(address, 'bank'), self.parseAttributeFromAddress(address, 'row'), self.parseAttributeFromAddress(address, 'colum')) - return line.replace("\n", " ") + decodedAddress - except AttributeError: - return '' + # def formatStlLine(self, line): + # try: + # found = re.search('0x[0-9,a-f]+', line).group(0) + # address = int(found, 16) + # decodedAddress = '[Channel: {0} Bank: {0} Row:{1} Col:{2}]'.format(self.parseAttributeFromAddress(address, 'channel'), + # self.parseAttributeFromAddress(address, 'bank'), self.parseAttributeFromAddress(address, 'row'), self.parseAttributeFromAddress(address, 'colum')) + # return line.replace("\n", " ") + decodedAddress + # except AttributeError: + # return '' def printStlPretty(self, filename): f = open(filename) @@ -58,62 +58,62 @@ class StlReader: #print(self.formatStlLine(line)) found = re.search('0x[0-9,a-f]+', line).group(0) address = int(found, 16) - print(format(address, '032b') + " " + self.formatStlLine(line)) + print(format(address, '032b')) #+ " " + self.formatStlLine(line)) -class StlGenerator: - __actions = [] - __time = 0 - __dramConfigReader = DramConfigReader() +# class StlGenerator: +# __actions = [] +# __time = 0 +# __dramConfigReader = DramConfigReader() - def clear(self): - self.__actions = [] - self.__time = 0 +# def clear(self): +# self.__actions = [] +# self.__time = 0 - def setTime(self, time): - self.__time = time +# def setTime(self, time): +# self.__time = time - def addAction(self, bank, row, channel=0, RD_WR='read'): - tupel = (self.__time, RD_WR, self.__generateAdress(channel, bank, row)) - self.__actions.append(tupel) +# def addAction(self, bank, row, channel=0, RD_WR='read'): +# tupel = (self.__time, RD_WR, self.__generateAdress(channel, bank, row)) +# self.__actions.append(tupel) - def setTimeAndAddAction(self, time, bank, row, channel=0, RD_WR='read'): - self.setTime(self, time) - self.addAction(self, bank, row, channel, RD_WR) +# def setTimeAndAddAction(self, time, bank, row, channel=0, RD_WR='read'): +# self.setTime(self, time) +# self.addAction(self, bank, row, channel, RD_WR) - def addLoad(self, banks, rows, channel=0, RD_WR='read'): - for bank in banks: - for row in rows: - self.addAction(bank, row, channel, RD_WR) +# def addLoad(self, banks, rows, channel=0, RD_WR='read'): +# for bank in banks: +# for row in rows: +# self.addAction(bank, row, channel, RD_WR) - def setTimeAndAddLoad(self, time, banks, rows, channel=0, RD_WR='read'): - self.setTime(self, time) - self.addLoad(banks, rows, channel, RD_WR) +# def setTimeAndAddLoad(self, time, banks, rows, channel=0, RD_WR='read'): +# self.setTime(self, time) +# self.addLoad(banks, rows, channel, RD_WR) - def generateStl(self, filename): - f = open(filename, 'w') - tmp = [] - for tupel in self.__actions: - tmp.append('{0}: {1} {2:#x}'.format(tupel[0], tupel[1], tupel[2])) - result = '\n'.join(tmp) - f.write(result) - f.close() - print( - '<---------------------- Generated stl {0} ---------------------->'.format(filename)) - print(result) - print( - '<---------------------- End generated stl ---------------------->'.format(filename)) +# def generateStl(self, filename): +# f = open(filename, 'w') +# tmp = [] +# for tupel in self.__actions: +# tmp.append('{0}: {1} {2:#x}'.format(tupel[0], tupel[1], tupel[2])) +# result = '\n'.join(tmp) +# f.write(result) +# f.close() +# print( +# '<---------------------- Generated stl {0} ---------------------->'.format(filename)) +# print(result) +# print( +# '<---------------------- End generated stl ---------------------->'.format(filename)) - def __generateAdress(self, channel, bank, row): - if(channel > self.__dramConfigReader.maxValues['channel']): - raise(BaseException('Channel argument out of range')) - if(bank > self.__dramConfigReader.maxValues['bank']): - raise(BaseException('Bank argument out of range')) - if(row > self.__dramConfigReader.maxValues['row']): - raise(BaseException('Row argument out of range')) - return (channel << self.__dramConfigReader.startBits['channel']) | (bank << self.__dramConfigReader.startBits['bank']) | (row << self.__dramConfigReader.startBits['row']) +# def __generateAdress(self, channel, bank, row): +# if(channel > self.__dramConfigReader.maxValues['channel']): +# raise(BaseException('Channel argument out of range')) +# if(bank > self.__dramConfigReader.maxValues['bank']): +# raise(BaseException('Bank argument out of range')) +# if(row > self.__dramConfigReader.maxValues['row']): +# raise(BaseException('Row argument out of range')) +# return (channel << self.__dramConfigReader.startBits['channel']) | (bank << self.__dramConfigReader.startBits['bank']) | (row << self.__dramConfigReader.startBits['row']) - def __init__(self): - pass +# def __init__(self): +# pass if __name__ == '__main__': diff --git a/dram/resources/simulations/first.xml b/dram/resources/simulations/first.xml index ea5f585a..5e26992b 100644 --- a/dram/resources/simulations/first.xml +++ b/dram/resources/simulations/first.xml @@ -1,16 +1,33 @@ - - - MICRON_4Gb_DDR4-2400_8bit_A.xml - am_ddr4.xml + +DDR4.xml + +am_highPara.xml + + + - fr_fcfs.xml - + - chstone-jpeg_32.stl + chstone-sha_32.stl + chstone-aes_32.stl + + + mediabench-h263decode_32.stl + mediabench-g721encode_32.stl + + + mediabench-fractal_32.stl + chstone-aes_32.stl + + + mediabench-h263decode_32.stl + chstone-aes_32.stl diff --git a/dram/src/common/xmlAddressdecoder.cpp b/dram/src/common/xmlAddressdecoder.cpp index 84342e25..4e460075 100644 --- a/dram/src/common/xmlAddressdecoder.cpp +++ b/dram/src/common/xmlAddressdecoder.cpp @@ -17,15 +17,15 @@ xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI) unsigned int to; // get channel: - TiXmlElement* channel = addressmap->FirstChildElement("channel"); - - - from = getAttribute(channel, "from"); - to = getAttribute(channel, "to"); - - channelShift = from; - channelMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); - channelSize = pow(2.0, to - from + 1.0); +// TiXmlElement* channel = addressmap->FirstChildElement("channel"); +// +// +// from = getAttribute(channel, "from"); +// to = getAttribute(channel, "to"); +// +// channelShift = from; +// channelMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); +// channelSize = pow(2.0, to - from + 1.0); // get row: TiXmlElement* row = addressmap->FirstChildElement("row"); @@ -58,14 +58,14 @@ xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI) columSize = pow(2.0, to - from + 1.0); // get bytes: - TiXmlElement* bytes = addressmap->FirstChildElement("bytes"); +// TiXmlElement* bytes = addressmap->FirstChildElement("bytes"); +// +// from = getAttribute(bytes, "from"); +// to = getAttribute(bytes, "to"); - from = getAttribute(bytes, "from"); - to = getAttribute(bytes, "to"); - - bytesShift = from; - bytesMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); - bytesSize = pow(2.0, to - from + 1.0); +// bytesShift = from; +// bytesMask = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); +// bytesSize = pow(2.0, to - from + 1.0); } else { @@ -80,7 +80,7 @@ xmlAddressDecoder::~xmlAddressDecoder() void xmlAddressDecoder::getNode(unsigned int addr, node * n) { - n->channel = (addr & channelMask) >> channelShift; + n->channel = 0; n->row = (addr & rowMask) >> rowShift; n->bank = (addr & bankMask) >> bankShift; n->colum = (addr & columMask) >> columShift; @@ -122,5 +122,5 @@ unsigned int xmlAddressDecoder::getNumberOfColumsPerRow() unsigned int xmlAddressDecoder::getNumberOfBytesPerColumn() { - return bytesSize; + return 1; } diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index ae0121ee..bdf4ac95 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -63,11 +63,13 @@ void SimulationManager::runSimulations() { string memconfig = getFileName(dramSetup.memconfig); string memspec = getFileName(dramSetup.memspec); + string addressmappig = getFileName(dramSetup.addressmapping); for (auto& traceSetup : batch.traceSetups) { - runSimulation(exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + memconfig + "-" + memspec + ".tdb", - dramSetup, traceSetup.second); + runSimulation( + exportPath + "/" + batch.simulationName + "/" + traceSetup.first + "-" + memconfig + "-" + memspec + "-" + + addressmappig + ".tdb", dramSetup, traceSetup.second); } } } @@ -80,17 +82,21 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation) batch.simulationName = simulation->Attribute("id"); string memspecUri; - string addressmappingUri = simulation->FirstChildElement("addressmapping")->GetText(); + string addressmappingUri; for (XMLElement* element = simulation->FirstChildElement("memspec"); element != NULL; element = element->NextSiblingElement("memspec")) { memspecUri = element->GetText(); - - for (XMLElement* element = simulation->FirstChildElement("memconfigs")->FirstChildElement("memconfig"); element != NULL; - element = element->NextSiblingElement("memconfig")) + for (XMLElement* element = simulation->FirstChildElement("addressmapping"); element != NULL; + element = element->NextSiblingElement("addressmapping")) { - batch.dramSetups.push_back(DramSetup(element->GetText(), memspecUri, addressmappingUri)); + addressmappingUri = element->GetText(); + for (XMLElement* element = simulation->FirstChildElement("memconfigs")->FirstChildElement("memconfig"); + element != NULL; element = element->NextSiblingElement("memconfig")) + { + batch.dramSetups.push_back(DramSetup(element->GetText(), memspecUri, addressmappingUri)); + } } }