derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

merged

Browse Source
This commit is contained in:
robert
2014-04-13 11:54:01 +02:00
parent e354fb5652 2c0f2c95a3
commit 856db2fde8
17 changed files with 293 additions and 173 deletions
Download Patch File Download Diff File Expand all files Collapse all files

0
dram/resources/configs/addressConfig.xml → dram/resources/configs/amconfigs/am_ddr4.xml
View File

27
dram/resources/configs/amconfigs/am_wideio.xml Executable file
View File

@@ -0,0 +1,27 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!--
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
<!-- <channel from="27" to="28" />
<row from="14" to="26" />
<bytes from="10" to="13" />
<colum from="3" to="9" />
<bank from="0" to="2" /> -->
</addressmap>
</dramconfig>

4
dram/resources/configs/memconfigs/fr_fcfs.xml
View File

@@ -3,8 +3,8 @@
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="100" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>

11
dram/resources/configs/memconfigs/fr_fcfs_bankwise.xml Normal file
View File

@@ -0,0 +1,11 @@
<memspec>
<memconfig>
<parameter id="bankwiseLogic" type="bool" value="1" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="100" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
</memconfig>
</memspec>

133
dram/resources/scripts/tests.py
View File

@@ -32,8 +32,7 @@ def getClock(connection):
class DramConfig(object):
memoryType = ""
bankwiseRefresh = False
bankwisePowerdown = False
bankwiseLogic = False
clk = 0
unitOfTime = ""
dataRate = 0
@@ -66,10 +65,10 @@ class DramConfig(object):
def readConfigFromFiles(self, connection):
print("parsing stuff and stuff")
print("Parsing dram configuration")
memspec = getMemspec(connection)
bankwisePowerdown = bankwiseRefresh = getValueFromConfigXML(getMemconfig(connection), "bankwiseLogic")
bankwiseLogic = getValueFromConfigXML(getMemconfig(connection), "bankwiseLogic")
clk = getClock(connection)
self.clk = clk[0]
self.unitOfTime = clk[1].lower()
@@ -187,84 +186,80 @@ def commands_are_clockaligned(connection):
result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk)))
return TestSuceeded()
# @test
# def commandbus_slots_are_used_once(connection):
# """Checks that no two phases on the command bus start at the same time"""
# cursor = connection.cursor()
@test
def commandbus_slots_are_used_once(connection):
"""Checks that no two phases on the command bus start at the same time"""
cursor = connection.cursor()
# if dramconfig.bankwisePowerdown and dramconfig.bankwiseRefresh:
# excludedPhases = "('REQ','RESP','PRE_ALL')"
# elif (not dramconfig.bankwisePowerdown and dramconfig.bankwiseRefresh):
# excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF')"
# elif dramconfig.bankwisePowerdown and not dramconfig.bankwiseRefresh:
# excludedPhases = "('REQ','RESP','PRE_ALL','AUTO_REFRESH')"
# else:
# excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF','AUTO_REFRESH')"
if dramconfig.bankwiseLogic:
excludedPhases = "('REQ','RESP','PRE_ALL')"
else:
excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF','AUTO_REFRESH')"
# query = """SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count
# FROM Phases WHERE PhaseName NOT IN """ + excludedPhases + """ AND phasebegin>0 GROUP BY phaseBegin) WHERE count>1"""
# cursor.execute(query)
# result = cursor.fetchone()
# if(result != None):
# return TestFailed("Slot on commandbus at time {0} is used multiple times".format(formatTime(result[0])))
# return TestSuceeded()
# @test
# def command_sequences_are_valid(connection):
# cursor = connection.cursor()
# cursor.execute("SELECT group_concat(phaseName),transact FROM phases GROUP BY transact")
# validSequences = set(['AUTO_REFRESH','PDNA','PDNP','SREF',
# 'PRE,AUTO_REFRESH', 'PRE_ALL,AUTO_REFRESH',
# 'REQ,RD,RESP', 'REQ,WR,RESP', 'REQ,RDA,RESP', 'REQ,WRA,RESP',
# 'REQ,ACT,RD,RESP', 'REQ,ACT,WR,RESP', 'REQ,ACT,RDA,RESP', 'REQ,ACT,WRA,RESP',
# 'REQ,PRE,ACT,RD,RESP', 'REQ,PRE,ACT,WR,RESP', 'REQ,PRE,ACT,RDA,RESP', 'REQ,PRE,ACT,WRA,RESP'
# ])
# for currentRow in cursor:
# commandSequence = currentRow[0]
# if(commandSequence not in validSequences):
# return TestFailed("Transaction {0} generated invalid command sequence {1}".format(currentRow[1], commandSequence))
query = """SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count
FROM Phases WHERE PhaseName NOT IN """ + excludedPhases + """ AND phasebegin>0 GROUP BY phaseBegin) WHERE count>1"""
# return TestSuceeded()
cursor.execute(query)
result = cursor.fetchone()
if(result != None):
return TestFailed("Slot on commandbus at time {0} is used multiple times".format(formatTime(result[0])))
return TestSuceeded()
# @test
# def row_buffer_is_used_correctly(connection):
# cursor = connection.cursor()
# query = """SELECT PhaseName, phases.ID FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE TBank=:bank
# AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin"""
@test
def command_sequences_are_valid(connection):
cursor = connection.cursor()
cursor.execute("SELECT group_concat(phaseName),transact FROM phases GROUP BY transact")
# for bankNumber in range(dramconfig.numberOfBanks):
# cursor.execute(query,{"bank": bankNumber})
validSequences = set(['AUTO_REFRESH','PDNA','PDNP','SREF',
'PRE,AUTO_REFRESH', 'PRE_ALL,AUTO_REFRESH',
'REQ,RD,RESP', 'REQ,WR,RESP', 'REQ,RDA,RESP', 'REQ,WRA,RESP',
'REQ,ACT,RD,RESP', 'REQ,ACT,WR,RESP', 'REQ,ACT,RDA,RESP', 'REQ,ACT,WRA,RESP',
'REQ,PRE,ACT,RD,RESP', 'REQ,PRE,ACT,WR,RESP', 'REQ,PRE,ACT,RDA,RESP', 'REQ,PRE,ACT,WRA,RESP'
])
for currentRow in cursor:
commandSequence = currentRow[0]
if(commandSequence not in validSequences):
return TestFailed("Transaction {0} generated invalid command sequence {1}".format(currentRow[1], commandSequence))
return TestSuceeded()
@test
def row_buffer_is_used_correctly(connection):
cursor = connection.cursor()
query = """SELECT PhaseName, phases.ID FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE TBank=:bank
AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin"""
for bankNumber in range(dramconfig.numberOfBanks):
cursor.execute(query,{"bank": bankNumber})
# rowBufferIsClosed = True
# #phases that precharge the bank
# prechargingPhases = set(['PRE','PRE_ALL','RDA','WRA'])
# #phases that require the bank to be precharged
# accessingPhases = set(['RD,RDA,WR,WRA,SREF,AUTO_REFRESH'])
rowBufferIsClosed = True
#phases that precharge the bank
prechargingPhases = set(['PRE','PRE_ALL','RDA','WRA'])
#phases that require the bank to be precharged
accessingPhases = set(['RD,RDA,WR,WRA,SREF,AUTO_REFRESH'])
# for currentRow in cursor:
for currentRow in cursor:
# if(currentRow[0] in accessingPhases and rowBufferIsClosed == True):
# return TestFailed("Phase {0}({1}) acesses a closed rowbuffer".format(currentRow[1], currentRow[0]))
if(currentRow[0] in accessingPhases and rowBufferIsClosed == True):
return TestFailed("Phase {0}({1}) acesses a closed rowbuffer".format(currentRow[1], currentRow[0]))
# if(currentRow[0] == 'ACT'):
# if(rowBufferIsClosed == True):
# rowBufferIsClosed = False
# else:
# return TestFailed("Phase {0}({1}) activates an already activated rowbuffer".format(currentRow[1],currentRow[0]))
if(currentRow[0] == 'ACT'):
if(rowBufferIsClosed == True):
rowBufferIsClosed = False
else:
return TestFailed("Phase {0}({1}) activates an already activated rowbuffer".format(currentRow[1],currentRow[0]))
# if(currentRow[0] in prechargingPhases):
# if(rowBufferIsClosed == True and currentRow[0] != 'PRE_ALL'):
# return TestFailed("Phase {0}({1}) closes an already closed rowbuffer".format(currentRow[1],currentRow[0]))
# else:
# rowBufferIsClosed = True
if(currentRow[0] in prechargingPhases):
if(rowBufferIsClosed == True and currentRow[0] != 'PRE_ALL'):
return TestFailed("Phase {0}({1}) closes an already closed rowbuffer".format(currentRow[1],currentRow[0]))
else:
rowBufferIsClosed = True
# return TestSuceeded()
return TestSuceeded()
# @test

13
dram/resources/simulations/first.xml Normal file
View File

@@ -0,0 +1,13 @@
<simulation>
<memspec>MICRON_4Gb_DDR4-1866_8bit_A.xml</memspec>
<addressmapping>am_wideio.xml</addressmapping>
<memconfigs>
<memconfig>fr_fcfs.xml</memconfig>
<memconfig>fr_fcfs_bankwise.xml</memconfig>
</memconfigs>
<trace-setups>
<trace-setup id="1">
<device >chstone-jpeg_32.stl</device>
</trace-setup>
</trace-setups>
</simulation>

3
dram/src/common/DebugManager.cpp
View File

@@ -16,7 +16,7 @@ void DebugManager::printDebugMessage(string sender, string message)
if (writeToConsole)
cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << endl;
if (writeToFile)
if (writeToFile && debugFile)
debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message << "\n";
}
#endif
@@ -36,7 +36,6 @@ void DebugManager::addToWhiteList(vector<string> senders)
DebugManager::DebugManager() :
writeToConsole(true), writeToFile(true)
{
debugFile.open("debug.txt");
}
void DebugManager::setDebugFile(std::string filename)

1
dram/src/common/TlmRecorder.cpp
View File

@@ -255,6 +255,5 @@ void TlmRecorder::closeConnection()
printDebugMessage("tlmPhaseRecorder:\tEnd Recording");
sqlite3_close(db);
db = NULL;
std::cout<<"connection closed"<<endl;
}

1
dram/src/common/Utils.cpp
View File

@@ -7,6 +7,7 @@
using namespace std;
using namespace tinyxml2;
void reportFatal(std::string sender, std::string message)
{
SC_REPORT_FATAL(sender.c_str(), message.c_str());

21
dram/src/common/Utils.h
View File

@@ -17,6 +17,8 @@
#include "third_party/tinyxml2.h"
#include <iomanip>
constexpr const char headline[] = "=========================================================";
template<typename Key, typename Val>
Val getElementFromMap(std::map<Key, Val>& m, Key key)
{
@@ -39,16 +41,19 @@ bool isIn(const T& value, const std::vector<T>& collection)
return false;
}
static inline void loadbar(unsigned int x, unsigned int n, unsigned int w = 50, unsigned int granularity=1)
static inline void loadbar(unsigned int x, unsigned int n, unsigned int w = 50, unsigned int granularity = 1)
{
if ( (x != n) && (x % (n/100*granularity) != 0) ) return;
if ((x != n) && (x % (n / 100 * granularity) != 0))
return;
float ratio = x/(float)n;
unsigned int c = (ratio * w);
std::cout << std::setw(3) << round(ratio*100) << "% [";
for (unsigned int x=0; x<c; x++) std::cout << "=";
for (unsigned int x=c; x<w; x++) std::cout << " ";
std::cout << "]\r" << std::flush;
float ratio = x / (float) n;
unsigned int c = (ratio * w);
std::cout << std::setw(3) << round(ratio * 100) << "% [";
for (unsigned int x = 0; x < c; x++)
std::cout << "=";
for (unsigned int x = c; x < w; x++)
std::cout << " ";
std::cout << "]\r" << std::flush;
}
void reportFatal(std::string sender, std::string message);

15
dram/src/core/TimingCalculation.cpp
View File

@@ -61,17 +61,22 @@ sc_time getExecutionTime(Command command, tlm::tlm_generic_payload& payload)
}
else if (command == Command::Write || command == Command::WriteA)
{
sc_time lengthOnDataStrobe = getBurstLengthOnDataStrobe(payload.get_streaming_width());
if (Configuration::getInstance().DataRate == 1)
lengthOnDataStrobe -= Configuration::getInstance().Timings.clk;
sc_time lockTime;
Configuration& config = Configuration::getInstance();
if(config.DataRate == 1)
lockTime = getBurstLengthOnDataStrobe(payload.get_streaming_width()) - config.Timings.clk;
else //special case DDR4 -> always 4 clocks
{
lockTime = config.Timings.clk * config.BurstLength / config.DataRate;
}
if (command == Command::Write)
{
return config.tWL + lengthOnDataStrobe;
return config.Timings.tWL + lockTime;
}
else
{
return config.tWL + lengthOnDataStrobe + config.tWR;
return config.Timings.tWL + lockTime + config.Timings.tWR;
}
}
else if (command == Command::PrechargeAll)

6
dram/src/simulation/MemoryManager.cpp
View File

@@ -6,6 +6,7 @@
*/
#include "MemoryManager.h"
#include "../common/DebugManager.h"
#include <iostream>
using namespace std;
@@ -22,9 +23,8 @@ MemoryManager::~MemoryManager()
delete payload;
numberOfFrees++;
}
cout << "Memory Manager: Number of allocated payloads: " << numberOfAllocations << std::endl;
cout << "Memory Manager: Number of freed payloads: " << numberOfFrees << std::endl;
DebugManager::getInstance().printDebugMessage("MemomryManager","Number of allocated payloads: " + to_string(numberOfAllocations));
DebugManager::getInstance().printDebugMessage("MemomryManager","Number of freed payloads: " + to_string(numberOfFrees));
}
gp* MemoryManager::allocate()

98
dram/src/simulation/Simulation.cpp
View File

@@ -20,31 +20,8 @@ using namespace std;
namespace simulation {
Simulation::Simulation(string name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices, bool silent) :
traceName(traceName), senderName(name)
void Simulation::setupDebugManager(bool silent, const string& traceName)
{
xmlAddressDecoder::addressConfigURI = pathToResources + string("configs/addressConfig.xml");
TlmRecorder::dbName = traceName;
TlmRecorder::sqlScriptURI = pathToResources + string("scripts/createTraceDB.sql");
Configuration::memconfigUri = pathToResources + string("configs/memconfigs/") + setup.memconfig;
Configuration::memspecUri = pathToResources + string("configs/memspecs/") + setup.memspec;
TlmRecorder::getInstance().recordMemconfig(setup.memconfig);
TlmRecorder::getInstance().recordMemspec(setup.memspec);
dram = new Dram<>("dram");
arbiter = new Arbiter<numberOfTracePlayers, 128>("arbiter");
controller = new Controller<>("controller");
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].burstLength, this);
TlmRecorder::getInstance().recordTracenames(devices[0].trace + "," + devices[1].trace);
player1->iSocket.bind(arbiter->tSockets[0]);
player2->iSocket.bind(arbiter->tSockets[1]);
arbiter->iSocket.bind(controller->tSocket);
controller->iSocket.bind(dram->tSocket);
vector<string> whiteList;
if (!silent)
@@ -52,12 +29,11 @@ Simulation::Simulation(string name, string pathToResources, string traceName, Dr
whiteList.push_back(controller->name());
whiteList.push_back(player2->name());
whiteList.push_back(player1->name());
whiteList.push_back(this->senderName);
whiteList.push_back(this->name());
whiteList.push_back(TlmRecorder::senderName);
whiteList.push_back(ControllerCore::senderName);
whiteList.push_back(PowerDownManagerBankwise::senderName);
}
auto& dbg = DebugManager::getInstance();
dbg.addToWhiteList(whiteList);
dbg.setDebugFile(traceName + ".txt");
@@ -66,12 +42,49 @@ Simulation::Simulation(string name, string pathToResources, string traceName, Dr
dbg.writeToConsole = false;
dbg.writeToFile = false;
}
}
Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices, bool silent) :
traceName(traceName), dramSetup(setup)
{
SC_THREAD(stop);
xmlAddressDecoder::addressConfigURI = pathToResources + string("configs/amconfigs/") + setup.addressmapping;
TlmRecorder::dbName = traceName;
TlmRecorder::sqlScriptURI = pathToResources + string("scripts/createTraceDB.sql");
Configuration::memconfigUri = pathToResources + string("configs/memconfigs/") + setup.memconfig;
Configuration::memspecUri = pathToResources + string("configs/memspecs/") + setup.memspec;
TlmRecorder::getInstance().recordMemconfig(setup.memconfig);
TlmRecorder::getInstance().recordMemspec(setup.memspec);
dram = new Dram<>("dram");
arbiter = new Arbiter<NumberOfTracePlayers, 128>("arbiter");
controller = new Controller<>("controller");
player1 = new TracePlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].burstLength, this);
player2 = new TracePlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].burstLength, this);
player3 = new TracePlayer<>("player3", pathToResources + string("traces/") + devices[2].trace, devices[2].burstLength, this);
player4 = new TracePlayer<>("player4", pathToResources + string("traces/") + devices[3].trace, devices[3].burstLength, this);
TlmRecorder::getInstance().recordTracenames(devices[0].trace + "," + devices[1].trace + "," + devices[2].trace + "," + devices[3].trace);
player1->iSocket.bind(arbiter->tSockets[0]);
player2->iSocket.bind(arbiter->tSockets[1]);
player3->iSocket.bind(arbiter->tSockets[2]);
player4->iSocket.bind(arbiter->tSockets[3]);
arbiter->iSocket.bind(controller->tSocket);
controller->iSocket.bind(dram->tSocket);
setupDebugManager(silent, traceName);
totalTransactions = getNumberOfLines(pathToResources + string("traces/") + devices[0].trace);
totalTransactions += getNumberOfLines(pathToResources + string("traces/") + devices[1].trace);
cout << "Total transactions: " << totalTransactions << endl;
remainingTransactions = totalTransactions;
totalTransactions += getNumberOfLines(pathToResources + string("traces/") + devices[2].trace);
totalTransactions += getNumberOfLines(pathToResources + string("traces/") + devices[3].trace);
remainingTransactions = totalTransactions;
}
Simulation::~Simulation()
@@ -81,15 +94,23 @@ Simulation::~Simulation()
delete controller;
delete player1;
delete player2;
delete player3;
delete player4;
}
void Simulation::start()
{
cout << "Starting simulation:" << endl;
report("\n\nStarting simulation:");
report(headline);
report(" -> setup: \t\t" + getFileName(traceName));
report(" -> memspec: \t\t" + Configuration::getInstance().MemoryId);
report(" -> transactions: \t" + to_string(totalTransactions));
cout << endl;
simulationStartTime = clock();
DebugManager::getInstance().printDebugMessage(senderName, "Starting simulation");
player1->start();
player2->start();
player3->start();
player4->start();
sc_set_stop_mode(SC_STOP_FINISH_DELTA);
sc_start();
}
@@ -98,22 +119,29 @@ void inline Simulation::transactionFinished()
{
remainingTransactions--;
loadbar(totalTransactions - remainingTransactions, totalTransactions);
if(remainingTransactions == 0)
if (remainingTransactions == 0)
{
stop();
cout << endl;
terminateSimulation.notify();
}
}
void Simulation::stop()
{
wait(terminateSimulation);
report("\nTerminating simulation");
controller->terminateSimulation();
DebugManager::getInstance().printDebugMessage(senderName, "Terminating simulation");
wait(sc_time(50, SC_NS));
TlmRecorder::getInstance().closeConnection();
sc_stop();
double elapsed_secs = double(clock() - simulationStartTime) / CLOCKS_PER_SEC;
DebugManager::getInstance().printDebugMessage(senderName, "Simulation took " + to_string(elapsed_secs) + " seconds");
cout << "\nSimulation took: " << (elapsed_secs) << endl;
report("Simulation took " + to_string(elapsed_secs) + " seconds");
}
void Simulation::report(string message)
{
DebugManager::getInstance().printDebugMessage(this->name(), message);
cout << message << endl;
}
unsigned int Simulation::getNumberOfLines(string uri)

22
dram/src/simulation/Simulation.h
View File

@@ -21,9 +21,10 @@ namespace simulation {
struct DramSetup
{
DramSetup():memconfig(""),memspec(""){}
DramSetup(std::string memconfig, std::string memspec) : memconfig(memconfig), memspec(memspec) {}
DramSetup(std::string memconfig, std::string memspec, std::string addressmapping) : memconfig(memconfig), memspec(memspec), addressmapping(addressmapping) {}
std::string memconfig;
std::string memspec;
std::string addressmapping;
};
struct Device
@@ -36,10 +37,11 @@ struct Device
unsigned int burstLength;
};
class Simulation: public ISimulation
class Simulation: public ISimulation, public sc_module
{
public:
Simulation(string name, string pathToResources, string traceName, DramSetup setup,
SC_HAS_PROCESS(Simulation);
Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices, bool silent = false);
~Simulation();
@@ -47,22 +49,30 @@ public:
void stop();
void inline transactionFinished() override;
constexpr static unsigned int NumberOfTracePlayers = 4;
private:
constexpr static unsigned int numberOfTracePlayers = 2;
std::string traceName;
std::string senderName;
DramSetup dramSetup;
sc_event terminateSimulation;
Dram<> *dram;
Arbiter<numberOfTracePlayers, 128> *arbiter;
Arbiter<NumberOfTracePlayers, 128> *arbiter;
Controller<> *controller;
TracePlayer<> *player1;
TracePlayer<> *player2;
TracePlayer<> *player3;
TracePlayer<> *player4;
unsigned int totalTransactions;
unsigned int remainingTransactions;
clock_t simulationStartTime;
unsigned int getNumberOfLines(string uri);
void report(std::string message);
void setupDebugManager(bool silent, const string& traceName);
};
} /* namespace simulation */

103
dram/src/simulation/SimulationManager.cpp
View File

@@ -25,19 +25,47 @@ SimulationManager::~SimulationManager()
void SimulationManager::loadSimulationFromXML(string uri)
{
simulationName = getFileName(uri);
cout << "\n\nLoad Simulation-Batch:"<<endl;
cout << headline<< endl;
cout << "\t-> load simulation from .."<<endl;
XMLDocument doc;
loadXML(uri, doc);
XMLElement* simulation = doc.FirstChildElement("simulation");
cout << "\t-> parsing simulation object .."<<endl;
simulationName = getFileName(uri);
parseXML(doc);
cout << "\t-> checking paths .."<<endl;
checkPaths();
cout << "\t-> simulation loaded successfully!\n"<<endl;
printSimulationBatch();
}
void SimulationManager::runSimulations()
{
system(string("mkdir -p " + simulationName).c_str());
for (auto& dramSetup : dramSetups)
{
string memconfig = getFileName(dramSetup.memconfig);
for (auto& traceSetup : traceSetups)
{
runSimulation(simulationName + "/" + memconfig + "-" + traceSetup.first + ".tdb", dramSetup, traceSetup.second);
}
}
}
void SimulationManager::parseXML(XMLDocument& doc)
{
XMLElement* simulation = doc.FirstChildElement("simulation");
string memspecUri = simulation->FirstChildElement("memspec")->GetText();
string addressmappingUri = simulation->FirstChildElement("addressmapping")->GetText();
for (XMLElement* element = simulation->FirstChildElement("memconfigs")->FirstChildElement("memconfig"); element != NULL;
element = element->NextSiblingElement("memconfig"))
{
dramSetups.push_back(DramSetup(element->GetText(), memspecUri));
dramSetups.push_back(DramSetup(element->GetText(), memspecUri, addressmappingUri));
}
for (XMLElement* element = simulation->FirstChildElement("trace-setups")->FirstChildElement("trace-setup"); element != NULL;
@@ -45,23 +73,6 @@ void SimulationManager::loadSimulationFromXML(string uri)
{
addTraceSetup(element);
}
checkPaths();
}
void SimulationManager::runSimulations()
{
system(string("mkdir " + simulationName).c_str());
printSimulationBatch();
int i = 0;
for (auto dramSetup : dramSetups)
{
for (auto traceSetup : traceSetups)
{
i++;
runSimulation(simulationName+"/tpr" + to_string(i) + ".tdb", dramSetup, traceSetup);
}
}
}
void SimulationManager::checkPaths()
@@ -75,7 +86,7 @@ void SimulationManager::runSimulation(string traceName, DramSetup dramSetup, vec
int status = 0;
if (pid == 0)
{
Simulation* simulation = new Simulation("sim", resources, traceName, dramSetup, traceSetup);
Simulation* simulation = new Simulation("sim", resources, traceName, dramSetup, traceSetup, silent);
simulation->start();
delete simulation;
_Exit(0);
@@ -84,27 +95,10 @@ void SimulationManager::runSimulation(string traceName, DramSetup dramSetup, vec
waitpid(pid, &status, 0);
}
void SimulationManager::printSimulationBatch()
{
cout << "Simulation Batch:\n##################" << endl;
for (DramSetup& s : dramSetups)
{
cout << s.memspec << " - " << s.memconfig << endl;
}
cout << endl;
for (vector<Device>& s : traceSetups)
{
cout << "Simulation:\n";
for (Device d : s)
cout << "\t(" << d.burstLength << ") " << d.trace << ";" << endl;
cout << endl;
}
}
void SimulationManager::startTraceAnalyzer()
{
string p = getenv("trace");
string run_tpr = p + " -f " + simulationName;
string run_tpr = p + " -f " + simulationName + "&";
system(run_tpr.c_str());
}
@@ -115,7 +109,34 @@ void SimulationManager::addTraceSetup(tinyxml2::XMLElement* element)
{
devices.push_back(Device(device->GetText(), device->IntAttribute("bl")));
}
traceSetups.push_back(devices);
while(devices.size()<Simulation::NumberOfTracePlayers)
{
devices.push_back(Device());
}
traceSetups.emplace(element->Attribute("id"), devices);
}
void SimulationManager::report(string message)
{
//DebugManager::getInstance().printDebugMessage("Simulation Manager", message);
//if (DebugManager::getInstance().writeToConsole == false)
cout << message << endl;
}
void SimulationManager::printSimulationBatch()
{
for (DramSetup& s : dramSetups)
{
cout << s.memspec << " - " << s.memconfig << endl;
}
cout << endl;
for (auto& s : traceSetups)
{
cout << "trace-setup " + s.first + ":\n";
for (Device d : s.second)
cout << "\t(" << d.burstLength << ") " << d.trace << ";" << endl;
cout << endl;
}
}
}

7
dram/src/simulation/SimulationManager.h
View File

@@ -10,6 +10,7 @@
#include <vector>
#include <string>
#include <map>
#include "Simulation.h"
#include "../common/third_party/tinyxml2.h"
@@ -25,17 +26,21 @@ public:
void runSimulations();
void startTraceAnalyzer();
bool silent = false;
private:
std::string simulationName;
std::vector<simulation::DramSetup> dramSetups;
std::vector<std::vector<Device>> traceSetups;
std::map<std::string, std::vector<Device>> traceSetups;
std::string resources;
void runSimulation(std::string traceName, DramSetup dramSetup, std::vector<Device> traceSetup);
void addTraceSetup(tinyxml2::XMLElement* element);
void parseXML(tinyxml2::XMLDocument& doc);
void checkPaths();
void printSimulationBatch();
void report(std::string message);
};
} /* namespace simulation */

1
dram/src/simulation/main.cpp
View File

@@ -39,6 +39,7 @@ int sc_main(int argc, char **argv)
SimulationManager manager(resources);
manager.loadSimulationFromXML(resources + "/simulations/" + simulationToRun);
manager.silent = true;
manager.runSimulations();
manager.startTraceAnalyzer();